
CONTENTS (continued)
Control/Status
Address
Bus
Select
..............
.
Read/Write
Data
Bus
Data
Request
In/Data
Request
Out
......
.
Da
ta
St
robe
In/Da
ta
St
robe
Ou
t
........
.
HP-IB
Interface
IC
.,
................
.
Microprocessor
.....
HP-IB
Address
Switch
Channel
Status
...
Sel
f Tes t Swi
tches
.......................................
.
Self
Test
Display
. . . . . . . . . . . . . . . . . . . . . .
..............
.
DMA
Ga
te
Array
IC . . . . . . . . . . . . . . . . . . . . . .
.....
.
RAM
...........
......................
.
..............
.
EXEC
EPROM
. . . .
..
......................
.
..............
.
DOC
0
EPROM
.........................................
.
DOC
1 E
PROM
..................................
, . . . . .
Address
Multiplexer
........................................
.
Clocks
And
Control
Logic
....................................
.
ROM
Sw
i t ch . . . . . . . . . . . . . . . _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers
Typical
HOC
Transaction
.....................................
.
DOC
PCA-A2
.................................................
.
HOC/DOC
Commu
ni
cat
ion
..................
. . . . . . . . . . . . . . . .
Control/Status
Data
and
Address
Buses
.....................
.
Read/Wri
te
Data
Bus
.....................................
.
Receiver/Driver
........................................
.
Transceivers
..........................
.
..............
.
DOC/Disc
Drive
A1
Communication
.............
.
..............
.
Controller
IC and
Register
Decode Logic
.......
.
..............
.
HDA
Desc r
ipt
ion
PROM
.....................................
.
Self-Test
Register
.......................
.
.........
.
GPC
Register
...........................................
.
DOC
Err
0 rs
Reg
i s t er
.....................................
.
PUPO
Register
...........................
.
.....
.
Disc
Controller
IC
....................
.
.........
.
Phase-
Loc
ked
Loop
IC
.......................................
.
Latch
...................................................
.
DMA
Handshake Cont
rol
......................................
.
Clock
Generator
.........................................
.
Write
Precompensation
....................................
.
Disc
Drive
A1
.............................................
.
Disc
Drive
A1/DDC
Control
Communication
......................
.
Input
Buffers
..........................................
.
Output
Drivers
..........................................
.
Disc
Drive
A1/DDC
Data
Communication
........................
.
Microprocessor
and
PLA
.....................................
.
Microprocessor/PLA
Control
Signals
..........................
.
Clock
Generator
...........................................
.
Head-Disc
Module
..........................................
.
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-9
....
,3-10
3-10
3-10
3-10
3-10
3-11
3-11
3-11
3-11
3-12
3-12
3-12
3-12
3-12
3-12
3-12
3-13
3-13
3-13
3-13
3-13
3-14
3-14
3-14
3-14
3-15
3-15
3-15
3-15
3-15
Actuator
.....
............................
3-15
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