Hunt Engineering HERON User manual

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Camera Link Area-scan Camera Interface using the FPGA5
v2.2 R.Williams 28-04-05
The HERON-FPGA and HERON-IO families are ranges of HERON modules with FPGAs, often
combined with some interface capability. The HERON-FPGA family in particular provides an FPGA
along with a large number of signals routed to general-purpose connectors. These modules are suitable for
connecting to digital cameras, where the control of the camera and image capture can be performed by the
FPGA fitted to the module.
For the development of the FPGA function, HUNT ENGINEERING provides a Hardware Interface
Layer written in VHDL. This layer allows developers to focus on the application-specific parts of the
system. All of the module hardware should be accessed using parts from the library.
Through the Camera Link Area-scan Camera example HUNT ENGINEERING provides a structured
starting point for the development of an area-scan camera interface. The example includes several
components suitable for processing a stream of camera data. It is intended to be a generic tutorial, so does
not address any camera specific issues.
History
Rev 1.0 Adapted from the examples for HERON-FPGA3 and HERON-FPGA4
Rev 2.1 Updated high frequency de-serializer
Rev 2.2 Removed reference to specific ISE versions

2
Concepts
FPGA devices are programmable hardware, which can be configured to meet the needs of your system.
As with a microprocessor, the function of the FPGA is controlled entirely by the program – and by the
peripherals the FPGA is connected to.
A HERON module has access to FIFOs for communicating with other modules in the system – there
may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or
level-shifting buffers, allowing it to interface to the real world.
The HERON-FPGA family use Xilinx re-configurable logic devices. These can be programmed at low
level, but can also be programmed using high level blocks, such as FIR filters, FFT transforms and so
on. This process is covered in a separate paper.
The Camera Link Area-scan Example
Every HERON-FPGA module is provided with a Hardware Interface Layer that makes it simple for a
user’s FPGA design to access the hardware. Some of the HERON-FPGA modules also have a Camera
Link area-scan camera interface example entitled “CamLink_Cam”. For the rest of this document we
will discuss the Camera Link area-scan camera example provided for the Virtex-II version of the
HERON-FPGA5.
Camera Link is a communication interface that was specifically developed by camera and frame-grabber
manufacturers for use with vision applications. Camera Link works in one of three different
configurations, Base, Medium and Full. The Camera Link example has been developed specifically for
the Base Configuration only. Using this configuration however, it is possible to support cameras from
8-bit pixel resolutions up to 24-bit RGB.
Please note, in order to correctly interface to Camera Link, the FPGA must be able to connect to
LVDS signals. The Virtex-II FPGA IO standards include LVDS support, while the Spartan-II FPGA
IO standards do not. As a result Spartan-II versions of HERON-FPGA modules cannot be used with
the Camera Link example. You can refer to the later sections on ‘Signal Voltage Levels’ for more
information on the requirements of connecting to LVDS.
The “CamLink_Cam” example is supplied as a project for ISE. It contains the top-level design, and
user constraints that define the pinning of the FPGA and timing of the clocks.
The code for the camera interface is implemented in the User Application source file, user_ap1.vhd,
and the files below that. The part of the design tree that includes the files hsb1.vhd and below contains
a set of registers that are programmed over the HSB message interface in order to control camera
interface operation. The HSB interface also provides a mechanism for transmitting and receiving RS-
232 messages between the Camera Link camera and the FPGA camera interface. The part of the design
tree that includes the file clink.vhd and below contains the Camera Link interface. The file camera.vhd
contains generic camera processing functions. All of these files can be modified to make your own
camera interface.
Although the FPGA can be used to capture and process image data without the need for a DSP, the
standard IP outputs full rate image data. This cannot be sent to a Host PC without providing a buffer
that takes care of the “burst” nature of PCI transactions. So for this example we actually capture images
into the memory of a DSP module, then use the DSP to format that into the Windows ‘.bmp’ format
and write it to the hard drive of the host PC using Server/Loader functions.
So in addition to the FPGA example, there is a software example that can be run on a DSP. This
program is provided as a set of two C source files and three header files. The program performs four
tasks. The first task is to set up the camera interface over the HSB interface. The second task is to send
and receive a series of RS-232 messages between the FPGA and camera. Thirdly an image is captured
by the FPGA module, transmitted through a HERON-FIFO and received on the DSP. Finally a series
of bitmap creation functions are called to create a Bitmap file (image.bmp) from the captured image.

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The created file can then be viewed by host system imaging software.
This tutorial assumes that the version of ISE design tool you are using is the same as the version of the
camera-link example. There are application notes on the HUNT ENGINEERING CD that describe
how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if
you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools
other tan ISE’ that you can refer to.

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What the Bit-stream Does
The Camera Link Area-scan Camera example provided on the HUNT ENGINEERING CD includes
bit-streams that can be loaded directly onto the Virtex-II, HERON-FPGA5 module. These bit-streams
implement a generic area-scan camera interface, with automatic frame-size and region of interest
detection and programmable region of interest for capture, and frame capture control.
The bit-streams are provided for connecting to a camera that operates using Camera Link. There are
two versions of the bit-stream. One bitstream for cameras operating at 24MHz and below and another
bitstream for cameras working at 25MHz or above.
The VHDL provided in the ‘CamLink_Cam’ example includes source code for two different frequency
Camera Link de-serializers. Each de-serializer design works with a different range of camera pixel clock
frequency. The appropriate frequency range de-serializer must be used based on the pixel clock
frequency of the camera you are using.
For the cameras with pixel clocks of 24MHz or below, the bitstream ending ‘_lf’ must be used. This
bitstream has been built with the Low Frequency Camera Link de-serializer. For the cameras with pixel
clock of 25MHz and above the bitstream ending ‘_hf’ must be used. This bitstream has been built with
the High Frequency Camera Link de-serializer.
For the examples that follow, one of the standard bit-streams supplied on the CD will be downloaded
to your module, depending on your module type. When using one of these standard bit-streams, it will
be necessary to understand what that bit-stream is doing.

5
Functional Block Diagram
Camera Link
Area-scan Signal
Interface
Capture
Region of
Interest
Frame
Control
Output Packing
and
Synchronisation
511x32
CoreGen
FIFO
HERON FIFO
Write Interface
HERON
Interface
HSB
Message
Interface
Area-scan
Camera
Conn.A
&
Conn.B
RS-232
Interface
Automatic Region of
Interest Detection

6
Camera Inputs
The Camera Link interface transmits camera control and data signals using the LVDS signalling
standard. In order to interface to LVDS signals the correct input and output buffer components must
be used in the FPGA design. This is done inside the file ‘top.vhd’. The module expects as inputs one
LVDS camera clock and four LVDS camera data lines. The module drives as outputs four LVDS
camera control signals. In addition to these signals, the module receives one RS232 input from the
camera and transmits one RS232 output to the camera.
The example bit-streams require the camera signals to be provided on Connector A and Connector B
of the HERON-FPGA5. The connections that are required are shown in the table below.
Connector A/B Camera Link Signal
CONN_A0 X0−
CONN_A1 X0+
CONN_A2 X1−
CONN_A3 X1+
CONN_A4 X2−
CONN_A5 X2+
CONN_A6 Xclk−
CONN_A7 Xclk+
CONN_A8 X3−
CONN_A9 X3+
CONN_B0 SerTC−
CONN_B1 SerTc+
CONN_B2 SerTFG−
CONN_B3 SerTFG+
CONN_B4 CC1−
CONN_B5 CC1+
CONN_B6 CC2−
CONN_B7 CC2+
CONN_B8 CC3−
CONN_B9 CC3+
CONN_B10 CC4−
CONN_B11 CC4+

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Signal Voltage Levels
The Camera Link standard uses Low Voltage Differential Signalling (LVDS) for the electrical interface
layer. The LVDS signalling standard is as the name suggests, differential. Therefore, one LVDS
connection will involve a positive signal and a negative signal complement. In order to correctly
connect to LVDS a Xilinx FPGA must be used that supports the LVDS standard.
HERON-FPGA modules are available with either Spartan-II or Virtex-II family devices fitted. The
Spartan-II family does not support LVDS signalling however, while the Virtex-II does. As a
consequence of this, only Virtex-II HERON-FPGA modules may be used with the Camera Link
example.
Please note: a 100R series resistor is required for every LVDS input to the Virtex-II FPGA5. This is
required to ensure correct operation. On the FPGA5 this simply requires the fitting of 100R resistor
packs to the reverse side of the board. Please ensure that if you intend to use your HERON-FPGA5
module for implementing a Camera Link interface that you specify the inclusion of the 100R
termination resistor packs for your board when you place the order.
The 100R termination resistor packs are shown on the underside of the board, in the picture above.
They must be fitted to the sites for Connector A of the HERON-FPGA5 such that each Camera Link
signal pair is terminated with 100R between the positive signal and negative signal of the pair.
If when you ordered your HERON-FPGA5 module you did not inform HUNT ENGINEERING
that you would be interfacing to Camera Link cameras, then your board will not have these resistors
fitted. In this case you can either contact HUNT ENGINEERING to discuss having the resistor packs
fitted at the factory, or alternatively you can fit the resistor packs yourself. Please note, although HUNT
ENGINEERING is happy for you to fit the resistors yourself, any damage done to the board in doing
so is not covered under the warranty.

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Camera Speeds
The bit-streams supplied by HUNT ENGINEERING have been specified for operation using a
Camera pixel clock frequency of 50MHz or less. There are two versions of the bitstream, one built
using a Low Frequency de-serializer for pixel clocks up to 24MHz and one built using a High
Frequency de-serializer for pixel clocks above 24MHz.
The Camera Link standard uses ‘Channel Link’ for the physical layer. Channel Link consists of a driver
and receiver pair. The driver accepts 28 bits of data and a clock. The data is serialised 7:1 into four data
streams and transmitted with a dedicated clock over 5 LVDS pairs. The receiver accepts the four LVDS
data streams and clock and then recreates the original 28-bit data stream along with the clock.
For those users who have cameras with pixel clocks above 50MHz the User Constraints File for the
project needs to be modified to reflect the particular operating frequency. When this has been done the
bitstream should be regenerated and the place and route report file checked to see those time-
specifications were met.

9
Automatic Region of Interest Detection
The module AUTO_ROI performs automatic region of interest detection. The module allows the
frame size and active areas of the image to be automatically detected and read over the HSB message
interface.
This information, if used, enables the controlling software to automatically calculate the window for the
capture region of interest process by using values that directly relate to the observed operation of the
camera.
Capture Region of Interest
The module ROI performs a region of interest operation by using a pixel counter and a line counter,
along with a pixel start position, pixel stop position, line start position and line stop position.
The pixel start, pixel stop, line start and line stop values are all programmed over the HSB message
interface. Each of these values can be pre-calculated using the Automatic Region of Interest logic, or
they can be set directly from values supplied by the user.
Frame Control
After the capture region of interest has processed each frame, whether that frame will be output or not
depends on the frame-control component. The continuous mode and N-frames mode are programmed
over the HSB message interface.
Output Packing and Synchronisation
One word, equal to 0 is added at the end of each camera line, apart from the last line of a frame, where
one word with all bits set high (the value FFFFFFFFh) is added to indicate end of frame. In order to
avoid the synchronisation values being present in the data, the bottom byte of camera data is modified
to prevent the values 00h and FFh (a value of 00h will become 01h and a value of FFh will become
FEh).
CoreGen FIFO and HERON FIFO Interface
After the data has been processed by the output packing and synchronisation component, the data is
fed into a Core-generator generated FIFO. The FIFO is a 32-bit word, 511 word deep asynchronous
FIFO built using Block RAM.
When there is any data in the CoreGen FIFO, it is read out and placed in the HERON FIFO Write
Interface. The FIFO number used for output is programmed over the HSB message interface. If the
HERON FIFO becomes full, eventually the CoreGen FIFO will become full and camera data will be
lost. If the CoreGen FIFO becomes full, LED0 will become illuminated.
RS-232 Interface
Camera Link provides two LVDS pairs for serial communication between the ‘frame grabber’ and
camera. The first LVDS pair ‘SerTC+/SerTC−’ is provided for communication To the Camera (TC)
and the second pair ‘SerTFG+/SerTFG−’ is provided for communication To the Frame-Grabber
(TFG).
The RS-232 Interface is connected to HSB. This enables HSB messages to be used to send RS-232
commands to the camera and receive camera status information back. The RS-232 Interface uses a 16-
byte transmit buffer and a 16-byte receive buffer. These buffers allow RS-232 transmission to be

10
decoupled from HSB.
The Baud rate of the RS-232 connection can be programmed over HSB.
HSB Control Registers
The following table defines the control registers that can be set by sending messages to the FPGA
using HSB.
HSB Address
Byte (decimal) Register Function Description
0 Pixel Start 0 Register LSB of pixel start register for Capture
Region Of Interest (register is 12bits)
1 Pixel Start 1 Register Top 4 bits of pixel start register for Capture
Region Of Interest (register is 12bits)
2 Pixel Stop 0 Register LSB of pixel stop register for Capture
Region Of Interest (register is 12bits)
3 Pixel Stop 1 Register Top 4 bits of pixel stop register for Capture
Region Of Interest (register is 12bits)
4 Line Start 0 Register LSB of line start register for Capture Region
Of Interest (register is 12bits)
5 Line Start 1 Register Top 4 bits of line start register for Capture
Region Of Interest (register is 12bits)
6 Line Stop 0 Register LSB of line stop register for Capture Region
Of Interest (register is 12bits)
7 Line Stop 1 Register Top 4 bits of line stop register for Capture
Region Of Interest (register is 12bits)
8 Frame Control Register Set number of frames to capture and send
(range 1 to 15, value set in bottom 4-bits)
Or, set bit 4 for continuous capture (i.e.
write 0x10)
9 Camera Control Register Bit 0 is used to directly set Camera Link
Camera Control 1 (CC1).
Bit 1 is used to directly set Camera Link
Camera Control 2 (CC2).
Bit 2 is used to directly set Camera Link
Camera Control 3 (CC3).
Bit 3 is used to directly set Camera Link
Camera Control 4 (CC4).
Bit 4 is used to control the ODD-ONLY
function. When this bit is set high only odd
pixels are output in each line, and only odd
lines are output in each frame.
Bit 5 is used to set the polarity of the
Camera Link control signals, FVAL, LVAL
and DVAL. Set to 0 if all signals are active
low. Set to 1 if all signals are active high.

11
HSB Address
Byte (decimal) Register Function Description
9 Camera Control Register Bit 6 is used to indicate whether the
connected camera provides a Camera Link
DVAL signal. Set to 0 if no DVAL signal is
provided. Set to 1 if a DVAL signal is
provided.
Bit 7 is used to reset the Auto-Region-of-
Interest logic. Set to 1 to assert reset and
then set to 0 to de-assert reset.
10 FIFO Number Register One Hot setting for the HERON Output
FIFO number that the data will be sent on.
11 Camera Mode Register Bits 0 to 3 MUST always be written with the value
4.
Bits 4 and 5 are used to control a data shift which
is required when using 10 or 12 bit Camera Link
cameras, as follows:
Bit 5 Bit4 Function Data Shift
0 0 8-bit camera none
0 1 10-bit camera right x 2
1 0 12-bit camera right x 4
1 1 14-bit camera right x 6
12 Baud Rate Register Bottom 4 bits of this register are used to set
Baud rate of the RS-232 interface as
follows: 0000 4800
0001 9600
0010 19200
0011 38400
0100 115200
13 Transmit Data Register A write to this register will place the data in
the next free position of the RS-232
transmit buffer.

12
The following table defines the status registers that can be read from the FPGA using HSB.
HSB Address
Byte (decimal) Register Function Description
0 First Pixel 0 Register Returns the bottom byte of the ‘First-Pixel’
value generated by the Auto-Region-of-
Interest logic.
1 First Pixel 1 Register Bits 0 to 3 return the top 4-bits of the ‘First-
Pixel’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 6 are undefined.
Bit 7 returns the state of the Auto-Region-
of-Interest Logic. 0 indicates that the Auto-
ROI values cannot be used. 1 indicates the
Auto-ROI values are valid and safe to use.
2 Last Pixel 0 Register Returns the bottom byte of the ‘Last-Pixel’
value generated by the Auto-Region-of-
Interest logic.
3 Last Pixel 1 Register Bits 0 to 3 return the top 4-bits of the ‘Last-
Pixel’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 are undefined.
4 First Line 0 Register Returns the bottom byte of the ‘First-Line’
value generated by the Auto-Region-of-
Interest logic.
5 First Line 1 Register Bits 0 to 3 return the top 4-bits of the ‘First-
Line’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 indicate bit activity in the 24-bit
‘Base Configuration’ Camera Link data
(from bit 23 down to bit 0), as follows:
Bit set high Indicates
4 Activity in bit 9
5 Activity in bit 11
6 Activity in bit 13
7 Activity in bit 15
6 Last Line 0 Register Returns the bottom byte of the ‘Last-Line’
value generated by the Auto-Region-of-
Interest logic.
7 Last Line 1 Register Bits 0 to 3 return the top 4-bits of the ‘Last-
Line’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 are undefined.
13 Transmit Data and
Status Register
A read from this register returns the
number of free spaces in the transmit
buffer.

13
HSB Address
Byte (decimal) Register Function Description
14 Receive Data Register A read from this register returns the next data
byte available in the RS-232 receive buffer.
15 Receive Status Register A read from this register returns the
number of data bytes in the RS-232 receive
buffer.
16 Pixel Total 0 Register Returns the bottom byte of the ‘Pixel-Total’
value generated by the Auto-Region-of-
Interest logic.
17 Pixel Total 1 Register Bits 0 to 3 return the top 4-bits of the
‘Pixel-Total’ value generated by the Auto-
Region-of-Interest logic.
Bits 4 to 7 return zero.
18 Line Total 0 Register Returns the bottom byte of the ‘Line-Total’
value generated by the Auto-Region-of-
Interest logic.
19 Line Total 1 Register Bits 0 to 3 return the top 4-bits of the ‘Line-
Total’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 return zero.

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Running the Tutorial
This tutorial covers downloading a Camera Link area-scan camera interface into the application FPGA
of a HERON-FPGA5, followed by building and running the example DSP program to capture and
store an image captured by the camera interface. To run the tutorial, follow this sequence:
1) Select “Getting Started” from the Hunt Engineering CD menu, then “to start using FPGA
modules and tools….”, then “Examples & IP by Function” and finally select “Camera Link
Area-scan Camera Interface (FPGA5)”. This should be how you reached this document.
On the same screen, click on the word “Files” to the right of “Camera Link Area-scan
Camera Interface”. Windows Explorer will open in the \fpga\fpga5v1 directory of the CD.
Here you will see a directory tree below the directory \CamLink_Cam. These are the files for
the Camera Link area-scan camera example.
There is also a zip file, which is a zip of the entire tree for this module type. This is provided
because restoring files from this zip file will restore files that are not set to read only. If you
simply copy the files from the CD you will need to set the files in the Camera example
directory so that they do not have the read only attribute set.
2) The next step is to program the FPGA by downloading the Camera example bit-stream. You
will need to do this whenever the FPGA program has been changed, or when the PC has
been powered off.
Select START !PROGRAMS !HUNT ENGINEERING !Program HERON-FPGA
You should see:-
Use the Detect button to find your FPGA module, and the Board and Slot should get filled in
for you. Then use the Browse button to select the bit-stream to use. You need to go to the
directory of the CD that you were just in, and enter the ‘Camera’ directory. Here there will be
several ‘.rbt’ files, which are the bit-stream files. The name shows the number of gates and the
package, e.g. 2v1000fg456.rbt is for a VirtexII 1Mgate FPGA in a FG456 package.
Be certain to use the appropriate file according to the pixel clock frequency of your camera.
Now select “Program FPGA” or “Program All” to download the bit-stream. The
configuration you have set up will be remembered for the next time so you do not have to go
through the browsing process every time.

15
Actually the program that does the downloading is an executable that will have been installed
in your %HEAPI_DIR%\utils directory and is called hrn_fpga.exe. This can be called directly
from your own program, or perhaps from your autoexec.bat file. The program takes all of the
options as command line parameters so that you will not have to answer prompts. Use
hrn_fpga -h to see the options.
The FPGA download program is also invoked if you are using the Server/Loader plug-in and
have not ticked the tick box ‘Skip FPGA’. The bit-stream file used is defined in the network
file being used.
A useful indicator is the “DONE” LED fitted to HERON modules that have an FPGA. It
will be on after power-up or during a reconfiguration, and will only go out if the FPGA is
programmed correctly. Check this to ensure the FPGA is programming correctly.
3) Now you need to understand how your system is set up. To run the example you will need to
have a DSP module in your system. The example defaults to a DSP module in slot 1 and a
HERON-FPGA5 in slot 2. Other slot positions may be used but if you do so, you will need
to modify the example.c source file and, in the case of the HEPC9, the Server/Loader
network file as well.
The DSP Example
Make a directory for the DSP example on your hard drive. In your Explorer window (from
stage1) change to the \fpga\fpga5v1\CamLink_Cam\dsp directory. Copy the all of the files
from there into the directory that you just made.
Now open Code Composer Studio and select the “Create new HERON-API Project” plug-in
to generate a new project for your DSP module. The project needs to be made around the
source file, example.c that was copied as described above. If you are not sure how to do this,
then refer to the “Getting started with C6000” section of the CD and the tutorials there.
After the project has been created, you will need to add the source file bmp.c to the project.
With this done the project should build without any other changes, unless you wish to test an
RS232 connection between your camera and the HERON-FPGA module. If you wish to test
RS232 you will need to edit the header file ‘rs232.h’ according to your camera type.
Please note, the example program has been written to capture a single frame using a region of
interest automatically created from the values output by the Automatic Region-of-Interest
logic, whatever your camera type.
What this means is that you should not need to modify any source code before building the
example. However, if when running the example you fail to get a picture then you should
consult the section at the end of this document that discusses camera differences and how the
Automatic Region of Interest logic functions.
Now you need to understand which FIFO number the DSP will use to access the FPGA, and
which FIFO number the FPGA will use to access the DSP.
HEPC9
For an HEPC9, you can use the heartconf utility to make the connections you want, or you
can use the default routing jumpers to make a simple connection. It is also possible to use the
Server/Loader plug-in to configure HEART via the network file it uses.
For this example, the Server/Loader network file will be used, but if you are interested in the
other methods, then for full instructions on using the heartconf utility, or setting the jumpers
please refer to the documentation for the HEPC9.
The example assumes that you have a HERON module in slot 1 and a HERON-FPGA5 in
slot 2. The network file provided connects FIFO 2 of slot 1 to FIFO 3 of slot 2. This works

16
with the settings used in the example.c source file.
In order to use a different combination of FIFOs, then the DSP_FIFONO and
FPGA_FIFONO #defines must be changed in the file example.c. Also the HEART
configuration must be changed in the network file.
When using a HEPC9, you could connect any FIFO you choose from the DSP module to the
FPGA module. In this example, the default values of FIFO 2 and FIFO 3 allow the same
software to work on a HEPC8, with the same slot assignments.
The following lines are taken from the network file provided.
# Using API
BD API HEP9A 0 0
#----------------------------------------------------------
# Nodes description
# ND BD_nb ND_NAME ND_Type CC-id HERON-ID filename(s)
#----------------------------------------------------------
ibc 0 ibc1 normal 0x06
pcif 0 host1 normal 0x05
c6 0 mod1 root 0x01 example.out
fpga 0 mod2 normal 0x02 2v1000fg456.rbt
#----------------------------------------------------------
# from:slot fifo to:slot fifo timeslot
#----------------------------------------------------------
heart host1 0 mod1 0 1
heart mod1 0 host1 0 1
heart mod1 2 mod2 3 1
heart mod2 3 mod1 2 1
For the network file to be correctly used to configure the FIFO connections, you need to
ensure that the Server/Loader plug-in has been correctly set up. Once the project has been
successfully built, start the Server-Loader plug-in.
In the plug-in, click on the Browse button and navigate to the directory to which the example
files were copied. Select the file named network and click open.
HEPC8
For an HEPC8 the connections are determined by which slots your modules are fitted to.
There will probably be a document shipped with your system that explains how your system is
configured, but if you have lost that or changed your configuration you will need to refer to
the user manual for the module carrier you are using to work it out.
For this example, the software assumes that the DSP module is in slot 1 and the HERON-
FPGA5 module is in slot 2. As such, the DSP will use FIFO 2 and the FPGA module will use
FIFO 3.
In order to use a different combination of FIFOs due to different slot positions, then the
DSP_FIFONO and FPGA_FIFONO #defines must be changed in the file example.c.

17
4) With the bit-stream downloaded to the FPGA, and the DSP example correctly configured and
built, the example program can be run. Before you do so, ensure that the camera is correctly
powered up and that the correct signal connections have been made between the camera and
Connectors A and B of the HERON-FPGA5.
Also ensure that the lens-cap has been removed from the camera and that the lens iris is at
least partially open. This is required to ensure that the Automatic Region of Interest functions
correctly as it calculates image areas by detecting active parts of the image.
The program needs to be run using the HUNT ENGINEERING Server/Loader plug-in.
The program will be run by clicking on the Start S/L button. If there is no tick in the ‘Skip
FPGA’ box, then the FPGA of the HERON-FPGA5 will be re-configured according to the
.rbt file specified in the network file. For this example, we have already configured the FPGA
(this can be checked by looking at the DONE LED of the HERON-FPGA5 to see that it is
off), so it will be better at this point to tick the box ‘Skip FPGA’.
When the program runs, it will reset the Automatic Region-of-Interest logic and begin to
detect the frame size and active area of the image. When this information has been obtained it
will then send all of the set-up information required over HSB. This information includes
setting the pixel-start, pixel-stop, line-start and line-stop values required by the capture region-
of-interest, as well as setting the mode of operation to 4x8, and programming the HERON
Output FIFO number according to the value of the FPGA_FIFONO #define in example.c.
When all of the HSB configuration messages have been sent, the program will request one
frame of data by sending the value 1 to the FRAMES input of the FRAME_CONTROL
component (again over HSB).
This frame will then be received by the DSP on the FIFO set by the DSP_FIFONO #define.
The pointer of the buffer the frame was stored to is then passed to the bitmap creation
functions and a bitmap file will be made. The name of the bitmap file will be ‘image.bmp’.
When the program has completed and the Server/Loader indicates program execution has
finished, this file can be viewed to see the image that was captured.
Assuming that an image has been successfully captured, you may continue either with developing your
DSP application to further process the image, or you may modify the FPGA program to perform image
processing inside the FPGA.
If you have been unsuccessful in capturing an image please refer to the last section of this document,
which discusses common errors and how to resolve them.
The following sections of this document describe the VHDL components that are provided in the
example, as well as explaining what you will need to consider in order to modify the FPGA program.

18
The FPGA Program
At this stage you should have been able to run the Camera Link Area-scan Camera example on the
FPGA and DSP and should have captured and viewed an image. If an image was successfully captured,
then at this stage you will probably need to further develop the FPGA program. The following assumes
that you are using the Xilinx ISE tool-set.
This part of the tutorial will show you how you can make some very simple modifications to the FPGA
program.
The example projects for ISE are shipped on the HUNT ENGINEERING CD. Using these projects
will allow you to run the complete design flow, from RTL-VHDL source files to the proper bit-stream,
ready to download on your HERON-FPGA board.
No special skills are required to do this.
However, if you want to write your own code and start designing your own application, you must make
sure that you have acquired the proper level of expertise in:
* VHDL language
* Digital Design
* Xilinx FPGAs
* ISE environment and design flow
Proper training courses exist which can help you acquire quickly the required skills and techniques.
Search locally for courses in your local language.
You may also visit ALSE's Web site where you will find design tips, useful links, design examples, etc…
at : http://www.alse-fr.com (then click on the "English version" banner).
Preparing ISE
Make sure ISE is properly installed with the XST-VHDL flow and ad-hoc device support.
Copying the examples from the HUNT ENGINEERING CD
On the HUNT ENGINEERING CD, under the directory “fpga” you can find directories for each
module type. In the case of the HERON-FPGA5 the correct directory is “fpga5v1”.
There are two ways that you can copy the files from the CD.
The directory tree with the VHDL sources, bit-streams etc can be copied directly from the CD to the
directory of your choice. In this case there is no need to copy the .zip file, but the files will be copied to
your hard drive with the same read only attribute that they have on the CD. In this case all files in the
“CamLink_Cam” directory need to be changed to have read/write permissions. It is a good idea to
leave the permissions of the “Common” directory set to read only to prevent the accidental
modification of these files. Please note, the Camera Link example uses a separate version of the
“Common” directory. This is because the file “top.vhd” has been modified to include LVDS IO
buffers for the connection to the Camera Link camera.
To make the process more convenient we have provided the zip file, which is a zipped image of the
same tree you can see on the CD. If you “unzip” this archive to a directory of your choice, you will
have the file permissions already set correctly.

19
Opening the Camera Project
In the tree that you have just copied from the CD, open the CamLink_Cam sub-directory. You should
see some further sub-directories.
* Common holds the common project files, including a modified version of Top.vhd.
* CamLink_Ex holds the Camera Link example
Below the CamLink_Ex directory you should see the following sub-directories.
* ISE holds the ISE project files
* Src holds the application-specific source files
Open the Xilinx ISE Project Navigator. If a project pops up (from a previous run), then close it. Use
File !Open Project.
You need to select the correct file with the .npl extension from the ISE directory under the
CamLink_Ex directory.
After some internal processing, the "Sources window" of the Project Navigator will display the internal
hierarchy of the Camera project.
If you are encountering errors at this stage, you should verify that:
The Camera example files have been correctly copied onto your hard disk, and especially the
\CamLink_Cam\Common and \CamLink_Cam\CamLink_Ex\Src directories.
The correct version of ISE has been successfully installed. Be sure to have installed XST VHDL
synthesis and the support for the correct FPGA families.
Project's Functional Parameters
Double click on "user_ap"in the Sources window. This opens the VHDL colour-coded text editor
so that you can see the part of the project where you can enter your own design.
The first code that you will see at the beginning of this file is a VHDL Package named "config"
which is used to configure the design files according to the application's requirements. See the next
section of this manual for a description of these items.
Below the package section, you will see the User_Ap1's VHDL code.
This is where you will insert your own code when you make your own design.
We provide a system which is built in such a way that the user should not edit any file other than
User_Ap (and the entities that this module instantiates).
In particular, the user should NOT modify the HE_* files,
even when creating new designs for the FPGA.

20
Setting up the Configuration Package
At the top of the user_ap1.vhd file there are the settings that you can use to affect your design (in this
case the camera example). The idea is that settings that are often changed are found here.
1. High or Low Frequency De-serialisation
The example is set by default, to use “low frequency” de-serialisation. That is, the logic used to de-
serialise the incoming camera data will only operate at pixel clocks up to 24MHz. Above this frequency
the “high frequency” de-serialiser logic must be used.
To use the low frequency de-serialiser set USE_LOW_FREQ_DESERIALISER to "True". In this
case, the Camera Link pixel clock frequency (Xclk) must be below 24 MHz. To use the high frequency
de-serialiser set USE_LOW_FREQ_DESERIALISER to “False”. In this case the pixel clock frequency
(Xclk) must be above 24MHz.
2. Divide External Clock by 2
The example uses the 100Mhz oscillator that is fitted to the module. It generates the FIFO clock either
directly from this 100Mhz, or divides it by 2 to generate a 50Mhz FIFO clock. Unfortunately the
HEPC8 module carrier cannot support a clock as high as 100Mhz, and the HEPC9 carrier cannot
support a clock as low as 50Mhz.
Set this parameter to "True" if you want to divide the external clock by two and use this as your main
Clock.
If you are using an HEPC8 carrier board, set DIV2_FCLK to "True".
If you are using an HEPC9 carrier board, set DIV2_FCLK to "False".
3. FIFO Clocks
You must decide whether you will have a single common clock for driving the input and output FIFOs.
Normally a design is simpler if the same clock is used for input and output FIFOs, but the module
design allows you to use different frequencies or phases if that is more convenient for the design of
your system. Whether you use a common clock or separate clocks will affect your design, but it also
affects the use of clocks in the Hardware Interface Layer.
Set FCLK_G_DOMAIN to True if you have the same clock driving both FIFOs.
This is the default option for the Examples. If you are unsure, select this choice.
Then, you must know whether your clocks are running slower than 60MHz or not.
Set HIGH_FCLK_G to True if your global clock is running at 60MHz or above. In this case an HF
DLL will be used in the FIFO clocks to ensure the proper timing.
Set HIGH_FCLK_G to False otherwise. In this case the HF DLL does not work, and indeed no DLL
is necessary.
Set FCLK_G_DOMAIN to False is you have a different clock driving each FIFO.
This option should be reserved to advanced users familiar with the management of multiple clock
domains systems.
Then, you must know whether your clocks are running slower than 60 MHz or not.
Set HIGH_FCLK_RD to True if your Input FIFO clock is running at 60MHz or above, so that the
HF DLL will be used for the input FIFO clock.
Set HIGH_FCLK_RD to False otherwise, so no DLL will be used for the input FIFO clock.
Set HIGH_FCLK_WR to True if your Output FIFO clock is running at 60MHz or above, so that the
HF DLL will be used for the output FIFO clock.
Set HIGH_FCLK_WR to False otherwise, so that no DLL will be used for the output FIFO clock.