2
Concepts
FPGA devices are programmable hardware, which can be configured to meet the needs of your system.
As with a microprocessor, the function of the FPGA is controlled entirely by the program – and by the
peripherals the FPGA is connected to.
A HERON module has access to FIFOs for communicating with other modules in the system – there
may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or
level-shifting buffers, allowing it to interface to the real world.
The HERON-FPGA family use Xilinx re-configurable logic devices. These can be programmed at low
level, but can also be programmed using high level blocks, such as FIR filters, FFT transforms and so
on. This process is covered in a separate paper.
The Camera Link Area-scan Example
Every HERON-FPGA module is provided with a Hardware Interface Layer that makes it simple for a
user’s FPGA design to access the hardware. Some of the HERON-FPGA modules also have a Camera
Link area-scan camera interface example entitled “CamLink_Cam”. For the rest of this document we
will discuss the Camera Link area-scan camera example provided for the Virtex-II version of the
HERON-FPGA5.
Camera Link is a communication interface that was specifically developed by camera and frame-grabber
manufacturers for use with vision applications. Camera Link works in one of three different
configurations, Base, Medium and Full. The Camera Link example has been developed specifically for
the Base Configuration only. Using this configuration however, it is possible to support cameras from
8-bit pixel resolutions up to 24-bit RGB.
Please note, in order to correctly interface to Camera Link, the FPGA must be able to connect to
LVDS signals. The Virtex-II FPGA IO standards include LVDS support, while the Spartan-II FPGA
IO standards do not. As a result Spartan-II versions of HERON-FPGA modules cannot be used with
the Camera Link example. You can refer to the later sections on ‘Signal Voltage Levels’ for more
information on the requirements of connecting to LVDS.
The “CamLink_Cam” example is supplied as a project for ISE. It contains the top-level design, and
user constraints that define the pinning of the FPGA and timing of the clocks.
The code for the camera interface is implemented in the User Application source file, user_ap1.vhd,
and the files below that. The part of the design tree that includes the files hsb1.vhd and below contains
a set of registers that are programmed over the HSB message interface in order to control camera
interface operation. The HSB interface also provides a mechanism for transmitting and receiving RS-
232 messages between the Camera Link camera and the FPGA camera interface. The part of the design
tree that includes the file clink.vhd and below contains the Camera Link interface. The file camera.vhd
contains generic camera processing functions. All of these files can be modified to make your own
camera interface.
Although the FPGA can be used to capture and process image data without the need for a DSP, the
standard IP outputs full rate image data. This cannot be sent to a Host PC without providing a buffer
that takes care of the “burst” nature of PCI transactions. So for this example we actually capture images
into the memory of a DSP module, then use the DSP to format that into the Windows ‘.bmp’ format
and write it to the hard drive of the host PC using Server/Loader functions.
So in addition to the FPGA example, there is a software example that can be run on a DSP. This
program is provided as a set of two C source files and three header files. The program performs four
tasks. The first task is to set up the camera interface over the HSB interface. The second task is to send
and receive a series of RS-232 messages between the FPGA and camera. Thirdly an image is captured
by the FPGA module, transmitted through a HERON-FIFO and received on the DSP. Finally a series
of bitmap creation functions are called to create a Bitmap file (image.bmp) from the captured image.
