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Concepts
FPGA devices are programmable hardware, which can be configured to meet the needs of your system.
As with a microprocessor, the function of the FPGA is controlled entirely by the program – and by the
peripherals the FPGA is connected to.
A HERON module has access to FIFOs for communicating with other modules in the system – there
may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or
level-shifting buffers, allowing it to interface to the real world.
The HERON-FPGA family use Xilinx re-configurable logic devices. These can be programmed at low
level, but can also be programmed using high level blocks, such as FIR filters, FFT transforms and so
on. This process is covered in a separate paper.
The RS-422 Area-scan Example
Every HERON-FPGA module is provided with a Hardware Interface Layer that makes it simple for a
user’s FPGA design to access the hardware. Some of the HERON-FPGA modules also have an
areascan camera interface example entitled “RS422_Cam”. For the rest of this document we will
discuss the RS-422 areascan camera example provided for the HERON-FPGA12.
The “RS422_Cam” example is supplied as a project for ISE. It contains the top-level design, and user
constraints that define the pinning of the FPGA and timing of the clocks.
The code for the camera interface is implemented in the User Application source file, user_ap1.vhd,
and the files below that. The part of the design tree that includes the files hsb1.vhd and below contains
a set of registers that are programmed over the HSB message interface in order to control camera
interface operation. The file camera.vhd contains generic camera processing functions. All of these files
can be modified to make your own camera interface.
Although the FPGA can be used to capture and process image data without the need for a DSP, the
standard IP outputs full rate image data. This cannot be sent to a Host PC without providing a buffer
that takes care of the “burst” nature of PCI transactions. So for this example we actually capture images
into the memory of a DSP module, then use the DSP to format that into the Windows ‘.bmp’ format
and write it to the hard drive of the host PC using Server/Loader functions.
So in addition to the FPGA example, there is a software example that can be run on a DSP. This
program is provided as a set of two C source files and three header files. The program performs three
tasks. The first task is to set up the camera interface over the HSB interface. Secondly an image is
captured by the FPGA module, transmitted through a HERON-FIFO and received on the DSP.
Finally a series of bitmap creation functions are called to create a Bitmap file (image.bmp) from the
captured image. The created file can then be viewed by host system imaging software.
This tutorial assumes that the version of ISE design tool you are using is the same as the version of the
camera-link example. There are application notes on the HUNT ENGINEERING CD that describe
how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if
you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools
other than ISE’ that you can refer to.
