Hunt Engineering RS-422 User manual

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RS-422 Area-scan Camera Interface using the FPGA12
V1.0 R.Williams 26-08-05
The HERON-FPGA and HERON-IO families are ranges of HERON modules with FPGAs, often
combined with some interface capability. The HERON-FPGA family in particular provides an FPGA
along with a large number of signals routed to general-purpose connectors. These modules are suitable for
connecting to digital cameras, where the control of the camera and image capture can be performed by the
FPGA fitted to the module.
For the development of the FPGA function, HUNT ENGINEERING provides a Hardware Interface
Layer written in VHDL. This layer allows developers to focus on the application-specific parts of the
system. All of the module hardware should be accessed using parts from the library.
Through the RS-422 Area-scan Camera example HUNT ENGINEERING provides a structured starting
point for the development of an area-scan camera interface. The example includes several components
suitable for processing a stream of camera data. It is intended to be a generic tutorial, so does not address
any camera specific issues.
History
Rev 1.0 Adapted from the example for HERON-FPGA9 (PW)

2
Concepts
FPGA devices are programmable hardware, which can be configured to meet the needs of your system.
As with a microprocessor, the function of the FPGA is controlled entirely by the program – and by the
peripherals the FPGA is connected to.
A HERON module has access to FIFOs for communicating with other modules in the system – there
may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or
level-shifting buffers, allowing it to interface to the real world.
The HERON-FPGA family use Xilinx re-configurable logic devices. These can be programmed at low
level, but can also be programmed using high level blocks, such as FIR filters, FFT transforms and so
on. This process is covered in a separate paper.
The RS-422 Area-scan Example
Every HERON-FPGA module is provided with a Hardware Interface Layer that makes it simple for a
user’s FPGA design to access the hardware. Some of the HERON-FPGA modules also have an
areascan camera interface example entitled “RS422_Cam”. For the rest of this document we will
discuss the RS-422 areascan camera example provided for the HERON-FPGA12.
The “RS422_Cam” example is supplied as a project for ISE. It contains the top-level design, and user
constraints that define the pinning of the FPGA and timing of the clocks.
The code for the camera interface is implemented in the User Application source file, user_ap1.vhd,
and the files below that. The part of the design tree that includes the files hsb1.vhd and below contains
a set of registers that are programmed over the HSB message interface in order to control camera
interface operation. The file camera.vhd contains generic camera processing functions. All of these files
can be modified to make your own camera interface.
Although the FPGA can be used to capture and process image data without the need for a DSP, the
standard IP outputs full rate image data. This cannot be sent to a Host PC without providing a buffer
that takes care of the “burst” nature of PCI transactions. So for this example we actually capture images
into the memory of a DSP module, then use the DSP to format that into the Windows ‘.bmp’ format
and write it to the hard drive of the host PC using Server/Loader functions.
So in addition to the FPGA example, there is a software example that can be run on a DSP. This
program is provided as a set of two C source files and three header files. The program performs three
tasks. The first task is to set up the camera interface over the HSB interface. Secondly an image is
captured by the FPGA module, transmitted through a HERON-FIFO and received on the DSP.
Finally a series of bitmap creation functions are called to create a Bitmap file (image.bmp) from the
captured image. The created file can then be viewed by host system imaging software.
This tutorial assumes that the version of ISE design tool you are using is the same as the version of the
camera-link example. There are application notes on the HUNT ENGINEERING CD that describe
how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if
you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools
other than ISE’ that you can refer to.

3
What the Bit-stream Does
The RS-422 Area-scan Camera example provided on the HUNT ENGINEERING CD includes bit-
streams that can be loaded directly onto the HERON-FPGA12. These bit-streams implement a generic
area-scan camera interface, with automatic frame-size and region of interest detection and
programmable region of interest for capture, and frame capture control. The bit-streams are provided
for connecting to a camera that operates using RS-422.
For the examples that follow, one of the standard bit-streams supplied on the CD will be downloaded
to your module, depending on your module type. When using one of these standard bit-streams, it will
be necessary to understand what that bit-stream is doing.
Functional Block Diagram
Area-scan
Signal
Interface
Region of
Interest
Frame
Control
Output Packing
and
Synchronisation
511x32
CoreGen FIFO HERON FIFO
Write Interface
HERON
Interface
HSB
Message
Interface
Area-scan
Camera Conn.
A Automatic Region of
Interest Detection

4
Camera Inputs
The first major functional block in the Camera example is the VHDL module AREASCAN. This
module is used to directly interface to the signals of the camera that you are using. This module expects
as inputs, a Line-Valid signal, a Frame-Valid signal, a Pixel Strobe (Clock), an optional Data-Valid signal
and between one to four bytes of data.
The example bit-streams have been built to work with one byte of camera data, along with the line-
valid, frame-valid, optional data-valid and pixel-strobe control signals. These signals must all be
provided on Connector A of the HERON-FPGA12. The connections that are required are shown in
the table below.
Connector A Camera Signal
CONN_A0 D0
CONN_A1 D1
CONN_A2 D2
CONN_A3 D3
CONN_A4 D4
CONN_A5 D5
CONN_A6 D6
CONN_A7 D7
CONN_A9 Data-Valid (optional)
CONN_A10 Line-Valid
CONN_A11 Frame-Valid
CONN_A12 Pixel-Strobe

5
Signal Voltage Levels
The example connects to the RS-422 signals of your digital camera by connecting the positive signal of
the differential pair to the appropriate signal on Connector A. The negative signal from the differential
signal pair should be left unconnected. Any available ‘Ground’ connections provided by your camera
should be connected to the GND pins of Connector A.
The Virtex-4 FX FPGA does not allow the direct connection of 5V inputs to I/O pins. As RS-422 uses
5V levels, the camera signals cannot be directly connected to the Virtex-4 FPGA. In order to resolve
this 5V compatibility issue, 100R series resistors are required on all inputs to the FPGA. This is
required to ensure correct operation.
On the FPGA12 this simply requires the fitting of resistor packs to the reverse side of the board. Please
ensure that if you intend to use the Virtex-4 FX HERON-FPGA12 module for implementing an RS-
422 camera interface that you specify the inclusion of the series resistors for your board when you place
the order.
The location of the resistor packs is shown in the picture below (the picture shows the underside of the
board). The resistor packs are normally fitted as 0R resistors (marked with 000 on the pack). For the
use of 5V signals these must be fitted as 100R (package marked 101) to the sites for Connectors A and
B of the HERON-FPGA12 such that each signal has 100R in series between the camera signal and the
FPGA.
If when you ordered your HERON-FPGA12 module you did not inform HUNT ENGINEERING
that you would be interfacing to 5V RS-422 signals, then your board will not have these resistors fitted.
In this case you can either contact HUNT ENGINEERING to discuss having the resistors fitted at the
factory, or alternatively you can fit the resistors yourself. Please note, although HUNT
ENGINEERING is happy for you to fit the resistors yourself, any damage done to the board in doing
so is not covered under the warranty.

6
Camera Speeds
The bitstreams supplied by HUNT ENGINEERING have been specified for operation using a
Camera Strobe frequency (pixel clock) of 50Mhz or less. It may be possible to improve on this if you
are making your own design when you should edit the .ucf file and compile iteratively to determine
what is possible in your own design.
Automatic Region of Interest Detection
The module AUTO_ROI performs automatic region of interest detection. The module allows the
frame size and active areas of the image to be automatically detected and read over the HSB message
interface.
This information, if used, enables the controlling software to automatically calculate the window for the
capture region of interest process by using values that directly relate to the observed operation of the
camera.
Capture Region of Interest
The module ROI performs a region of interest operation by using a pixel counter and a line counter,
along with a pixel start position, pixel stop position, line start position and line stop position.
The pixel start, pixel stop, line start and line stop values are all programmed over the HSB message
interface. Each of these values can be pre-calculated using the Automatic Region of Interest logic, or
they can be set directly from values supplied by the user.
Frame Control
After the capture region of interest has processed each frame, whether that frame will be output or not
depends on the frame-control component. The continuous mode and N-frames mode are programmed
over the HSB message interface.
Output Packing and Synchronisation
One word, equal to 0 is added at the end of each camera line, apart from the last line of a frame, where
one word with all bits set high (the value FFFFFFFFh) is added to indicate end of frame. In order to
avoid the synchronisation values being present in the data, the bottom byte of camera data is modified
to prevent the values 00h and FFh (a value of 00h will become 01h and a value of FFh will become
FEh).
CoreGen FIFO and HERON FIFO Interface
After the data has been processed by the output packing and synchronisation component, the data is
fed into a Core-generator generated FIFO. The FIFO is a 32-bit word, 511 word deep asynchronous
FIFO built using Block RAM.
When there is any data in the CoreGen FIFO, it is read out and placed in the HERON FIFO Write
Interface. The FIFO number used for output is programmed over the HSB message interface. If the
HERON FIFO becomes full, eventually the CoreGen FIFO will become full and camera data will be
lost. If the CoreGen FIFO becomes full, LED0 will become illuminated.

7
HSB Control Registers
The following table defines the control registers that can be set by sending messages to the FPGA
using HSB.
HSB Address
Byte (decimal) Register Function Description
0 Pixel Start 0 Register LSB of pixel start register for Capture Region
Of Interest (register is 12bits)
1 Pixel Start 1 Register Top 4 bits of pixel start register for Capture
Region Of Interest (register is 12bits)
2 Pixel Stop 0 Register LSB of pixel stop register for Capture Region
Of Interest (register is 12bits)
3 Pixel Stop 1 Register Top 4 bits of pixel stop register for Capture
Region Of Interest (register is 12bits)
4 Line Start 0 Register LSB of line start register for Capture Region
Of Interest (register is 12bits)
5 Line Start 1 Register Top 4 bits of line start register for Capture
Region Of Interest (register is 12bits)
6 Line Stop 0 Register LSB of line stop register for Capture Region
Of Interest (register is 12bits)
7 Line Stop 1 Register Top 4 bits of line stop register for Capture
Region Of Interest (register is 12bits)
8 Frame Control Register Set number of frames to capture and send
(range 1 to 15, value set in bottom 4-bits) Or,
set bit 4 for continuous capture (i.e. write
0x10)
9 Camera Control Register Bit 0 is used to directly set camera control
output 0 on CONN_A13 (Connector A).
Bit 1 is used to directly set camera control
output 1 on CONN_A14 (Connector A).
Bit 4 is used to control the ODD-ONLY
function. When this bit is set high only odd
pixels are output in each line, and only odd
lines are output in each frame.
Bit 5 is used to set the polarity of the camera
control signals, FVAL, LVAL and DVAL.
Set to 0 if all signals are active low. Set to 1 if
all signals are active high.
10 FIFO Number Register One Hot setting for the HERON Output
FIFO number that the data will be sent on.

8
HSB Address
Byte (decimal) Register Function Description
11 Camera Mode Register Bits 0 to 3 MUST always be written with the value
4.
Bits 4 and 5 are used to control a data shift which is
required when using 10 or 12 bit cameras, as
follows:
Bit 5 Bit4 Function Data Shift
0 0 8-bit camera none
0 1 10-bit camera right x 2
1 0 12-bit camera right x 4
1 1 14-bit camera right x 6

9
The following table defines the status registers that can be read from the FPGA using HSB.
HSB Address
Byte (decimal) Register Function Description
0 First Pixel 0 Register Returns the bottom byte of the ‘First-Pixel’
value generated by the Auto-Region-of-
Interest logic.
1 First Pixel 1 Register Bits 0 to 3 return the top 4-bits of the ‘First-
Pixel’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 6 are undefined.
Bit 7 returns the state of the Auto-Region-
of-Interest Logic. 0 indicates that the Auto-
ROI values cannot be used. 1 indicates the
Auto-ROI values are valid and safe to use.
2 Last Pixel 0 Register Returns the bottom byte of the ‘Last-Pixel’
value generated by the Auto-Region-of-
Interest logic.
3 Last Pixel 1 Register Bits 0 to 3 return the top 4-bits of the ‘Last-
Pixel’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 are undefined.
4 First Line 0 Register Returns the bottom byte of the ‘First-Line’
value generated by the Auto-Region-of-
Interest logic.
5 First Line 1 Register Bits 0 to 3 return the top 4-bits of the ‘First-
Line’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 indicate bit activity in the camera
data as follows:
Bit set high Indicates
4 Activity in bit 9
5 Activity in bit 11
6 Activity in bit 13
7 Activity in bit 15
6 Last Line 0 Register Returns the bottom byte of the ‘Last-Line’
value generated by the Auto-Region-of-
Interest logic.
7 Last Line 1 Register Bits 0 to 3 return the top 4-bits of the ‘Last-
Line’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 are undefined.

10
HSB Address
Byte (decimal) Register Function Description
16 Pixel Total 0 Register Returns the bottom byte of the ‘Pixel-Total’
value generated by the Auto-Region-of-
Interest logic.
17 Pixel Total 1 Register Bits 0 to 3 return the top 4-bits of the
‘Pixel-Total’ value generated by the Auto-
Region-of-Interest logic.
Bits 4 to 7 return zero.
18 Line Total 0 Register Returns the bottom byte of the ‘Line-Total’
value generated by the Auto-Region-of-
Interest logic.
19 Line Total 1 Register Bits 0 to 3 return the top 4-bits of the ‘Line-
Total’ value generated by the Auto-Region-
of-Interest logic.
Bits 4 to 7 return zero.

11
Running the Tutorial
This tutorial covers downloading a RS-422 area-scan camera interface into the application FPGA of a
HERON-FPGA12, followed by building and running the example DSP program to capture and store
an image captured by the camera interface. To run the tutorial, follow this sequence:
1) Select “Getting Started” from the Hunt Engineering CD menu, then “to start using FPGA
modules and tools….”, then “Examples & IP by Function” and finally select “RS422 Area-
scan Camera Interface”. This should be how you reached this document.
On the same screen, click on the word “Files” to the right of “RS-422 Area-scan Camera
Interface”. Windows Explorer will open in the \fpga\fpga12v1 directory of the CD. Here you
will see a directory tree below the directory \RS422_Cam. These are the files for the RS422
area-scan camera example.
There is also a zip file, which is a zip of the entire tree for this module type. This is provided
because restoring files from this zip file will restore files that are not set to read only. If you
simply copy the files from the CD you will need to set the files in the Camera example
directory so that they do not have the read only attribute set.
2) The next step is to program the FPGA by downloading the Camera example bit-stream. You
will need to do this whenever the FPGA program has been changed, or when the PC has
been powered off.
Select START !PROGRAMS !HUNT ENGINEERING !Program HERON-FPGA
You should see:-
Use the Detect button to find your FPGA module, and the Board and Slot should get filled in
for you. Then use the Browse button to select the bit-stream to use. You need to go to the
directory of the CD that you were just in, and enter the ‘Camera’ directory. Here there may be
several ‘.rbt’ files, which are the bit-stream files. The name shows the number of gates and the
package, e.g. 4vfx12ff668.rbt is for a Virtex-4 FX12 FPGA in a FF668 package.
Now select “Program FPGA” or “Program All” to download the bit-stream. The
configuration you have set up will be remembered for the next time so you do not have to go
through the browsing process every time.
Actually the program that does the downloading is an executable that will have been installed

12
in your %HEAPI_DIR%\utils directory and is called hrn_fpga.exe. This can be called directly
from your own program, or perhaps from your autoexec.bat file. The program takes all of the
options as command line parameters so that you will not have to answer prompts. Use
hrn_fpga -h to see the options.
The FPGA download program is also invoked if you are using the Server/Loader plug-in and
have not ticked the tick box ‘Skip FPGA’. The bit-stream file used is defined in the network
file being used.
A useful indicator is the “DONE” LED fitted to HERON modules that have an FPGA. It
will be on after power-up or during a reconfiguration, and will only go out if the FPGA is
programmed correctly. Check this to ensure the FPGA is programming correctly.
3) Now you need to understand how your system is set up. To run the example you will need to
have a DSP module in your system. The example defaults to a DSP module in slot 1 and a
HERON-FPGA12 in slot 2. Other slot positions may be used but if you do so, you will need
to modify the example.c source file and, the Server/Loader network file as well.
The DSP Example
Make a directory for the DSP example on your hard drive. In your Explorer window (from stage1)
change to the \fpga\fpga12v1\RS422_Cam\dsp directory. Copy the all of the files from there into the
directory that you just made.
Now open Code Composer Studio and select the “Create new HERON-API Project” plug-in to
generate a new project for your DSP module. The project needs to be made around the source file,
example.c that was copied as described above. If you are not sure how to do this, then refer to the
“Getting started with C6000” section of the CD and the tutorials there.
After the project has been created, you will need to add the source file bmp.c to the project.
Please note, the example program has been written to capture a single frame using a region of interest
automatically created from the values output by the Automatic Region-of-Interest logic, whatever your
camera type.
What this means is that you should not need to modify any source code before building the example.
However, if when running the example you fail to get a picture then you should consult the section at
the end of this document that discusses camera differences and how the Automatic Region of Interest
logic functions.
Now you need to understand which FIFO number the DSP will use to access the FPGA, and which
FIFO number the FPGA will use to access the DSP.
HEPC9
For an HEPC9, you can use the heartconf utility to make the connections you want, or you can use the
default routing jumpers to make a simple connection. It is also possible to use the Server/Loader plug-
in to configure HEART via the network file it uses.
For this example, the Server/Loader network file will be used, but if you are interested in the other
methods, then for full instructions on using the heartconf utility, or setting the jumpers please refer to
the documentation for the HEPC9.
The example assumes that you have a HERON module in slot 1 and a HERON-FPGA12 in slot 2.
The network file provided connects FIFO 2 of slot 1 to FIFO 3 of slot 2. This works with the settings
used in the example.c source file.
In order to use a different combination of FIFOs, then the DSP_FIFONO and FPGA_FIFONO
#defines must be changed in the file example.c. Also the HEART configuration must be changed in
the network file.
When using a HEPC9, you could connect any FIFO you choose from the DSP module to the FPGA

13
module.
The following lines are taken from the network file provided.
# Using API
BD API HEP9A 0 0
#----------------------------------------------------------
# Nodes description
# ND BD_nb ND_NAME ND_Type CC-id HERON-ID filename(s)
#----------------------------------------------------------
ibc 0 ibc1 normal 0x06
pcif 0 host1 normal 0x05
c6 0 mod1 root 0x01 example.out
fpga 0 mod2 normal 0x02 4vfx12ff668.rbt
#----------------------------------------------------------
# from:slot fifo to:slot fifo timeslot
#----------------------------------------------------------
heart host1 0 mod1 0 1
heart mod1 0 host1 0 1
heart mod1 2 mod2 3 1
heart mod2 3 mod1 2 1
For the network file to be correctly used to configure the FIFO connections, you need to ensure that
the Server/Loader plug-in has been correctly set up. Once the project has been successfully built, start
the Server-Loader plug-in.
In the plug-in, click on the Browse button and navigate to the directory to which the example files
were copied. Select the file named network and click open.
With the bit-stream downloaded to the FPGA, and the DSP example correctly configured and built,
the example program can be run. Before you do so, ensure that the camera is correctly powered up and
that the correct signal connections have been made between the camera and Connector A of the
HERON-FPGA12.
Also ensure that the lens-cap has been removed from the camera and that the lens iris is at least
partially open. This is required to ensure that the Automatic Region of Interest functions correctly as it
calculates image areas by detecting active parts of the image.
The program needs to be run using the HUNT ENGINEERING Server/Loader plug-in. The
program will be run by clicking on the Start S/L button. If there is no tick in the ‘Skip FPGA’ box,
then the FPGA of the HERON-FPGA12 will be re-configured according to the .rbt file specified in
the network file. For this example, we have already configured the FPGA (this can be checked by
looking at the DONE LED of the HERON-FPGA12 to see that it is off), so it will be better at this
point to tick the box ‘Skip FPGA’.
When the program runs, it will reset the Automatic Region-of-Interest logic and begin to detect the
frame size and active area of the image. When this information has been obtained it will then send all
of the set-up information required over HSB. This information includes setting the pixel-start, pixel-
stop, line-start and line-stop values required by the region-of-interest, as well as setting the mode of
operation to 4x8, and programming the HERON Output FIFO number according to the value of the

14
FPGA_FIFONO #define in example.c.
When all of the HSB configuration messages have been sent, the program will request one frame of
data by sending the value 1 to the FRAMES input of the FRAME_CONTROL component (again
over HSB).
This frame will then be received by the DSP on the FIFO set by the DSP_FIFONO #define. The
pointer of the buffer the frame was stored to is then passed to the bitmap creation functions and a
bitmap file will be made. The name of the bitmap file will be ‘image.bmp’. When the program has
completed and the Server/Loader indicates program execution has finished, this file can be viewed to
see the image that was captured.
Assuming that an image has been successfully captured, you may continue either with developing your
DSP application to further process the image, or you may modify the FPGA program to perform image
processing inside the FPGA.
If you have been unsuccessful in capturing an image please refer to the last section of this document,
which discusses common errors and how to resolve them.
The following sections of this document describe the VHDL components that are provided in the
example, as well as explaining what you will need to consider in order to modify the FPGA program.

15
The FPGA Program
At this stage you should have been able to run the RS-422 Area-scan Camera example on the FPGA
and DSP and should have captured and viewed an image. If an image was successfully captured, then at
this stage you will probably need to further develop the FPGA program. The following assumes that
you are using the Xilinx ISE tool-set.
This part of the tutorial will show you how you can make some very simple modifications to the FPGA
program.
The example projects for ISE Foundation are shipped on the HUNT ENGINEERING CD. Using
these projects will allow you to run the complete design flow, from RTL-VHDL source files to the
proper bit-stream, ready to download on your HERON-FPGA board.
No special skills are required to do this.
However, if you want to write your own code and start designing your own application, you must make
sure that you have acquired the proper level of expertise in:
* VHDL language
* Digital Design
* Xilinx FPGAs
* ISE environment and design flow
Proper training courses exist which can help you acquire quickly the required skills and techniques.
Search locally for courses in your local language.
Preparing ISE
Make sure ISE is properly installed with the XST-VHDL flow and ad-hoc device support.
Copying the examples from the HUNT ENGINEERING CD
On the HUNT ENGINEERING CD, under the directory “fpga” you can find directories for each
module type. In the case of the HERON-FPGA12 the correct directory is “fpga12v1”.
There are two ways that you can copy the files from the CD.
The directory tree with the VHDL sources, bit-streams etc can be copied directly from the CD to the
directory of your choice. In this case there is no need to copy the .zip file, but the files will be copied to
your hard drive with the same read only attribute that they have on the CD. In this case all files in the
“RS422_Cam” directory need to be changed to have read/write permissions. It is a good idea to leave
the permissions of the “Common” directory set to read only to prevent the accidental modification of
these files.
To make the process more convenient we have provided the zip file, which is a zipped image of the
same tree you can see on the CD. If you “unzip” this archive to a directory of your choice, you will
have the file permissions already set correctly.

16
Opening the Camera Project
In the tree that you have just copied from the CD, open the RS422_Cam sub-directory. You should see
some further sub-directories there.
* ISE holds the ISE project files
* Src holds the application-specific source files
Open the Xilinx ISE Project Navigator. If a project pops up (from a previous run), then close it. Use
File !Open Project.
You need to select the correct file with the .ise extension from the ISE directory under the Camera
directory. There may be several ise files for different versions of your module.
After some internal processing, the "Sources window" of the Project Navigator will display the internal
hierarchy of the Camera project.
If you are encountering errors at this stage, you should verify that:
The Camera example files have been correctly copied onto your hard disk, and especially the \Common
and RS422_Cam\Src directories.
The correct version of ISE has been successfully installed. Be sure to have installed XST VHDL
synthesis and the support for the correct FPGA families.
Project's Functional Parameters
Double click on "user_ap"in the Sources window. This opens the VHDL colour-coded text editor
so that you can see the part of the project where you can enter your own design.
The first code that you will see at the beginning of this file is a VHDL Package named "config"
which is used to configure the design files according to the application's requirements. See the next
section of this manual for a description of these items.
Below the package section, you will see the User_Ap1's VHDL code.
This is where you will insert your own code when you make your own design.
We provide a system which is built in such a way that the user should not edit any file other than
User_Ap (and the entities that this module instantiates).
In particular, the user should NOT modify the HE_* files,
even when creating new designs for the FPGA.

17
Setting up the Configuration Package
At the top of the user_ap1.vhd file there are the settings that you can use to affect your design (in this
case the camera example). The idea is that settings that are often changed are found here.
1. FIFO Clocks
You must decide whether you will have a single common clock for driving the input and output FIFOs.
Normally a design is simpler if the same clock is used for input and output FIFOs, but the module
design allows you to use different frequencies or phases if that is more convenient for the design of
your system. Whether you use a common clock or separate clocks will affect your design, but it also
affects the use of clocks in the Hardware Interface Layer.
Set FCLK_G_DOMAIN to True if you have the same clock driving both FIFOs.
This is the default option for the Examples. If you are unsure, select this choice.
In that case you provide a frequency for that clock on the signal SRC_FCLK_G. For module carriers
like the HEPC9, HECPCI9 and HERON-BASE2 this clock must be greater than or equal to 60Mhz
and less than or equal to 100Mhz. If you have another carrier card please check it’s user documentation
for the limits of it’s FIFO clock frequency.
The signal FCLK_G must then be used in your FPGA design as the correct phase of this clock to
sample the FIFO data with.
If you have different input and output FIFO clocks then select FCLK_G_DOMAIN as False and then
you use the individual SRC_FCLK signals to drive the frequencies and the FCLK signals to clock your
logic.
You also need to consider the timing constraints that are defined in the .ucf file for your design. Actually if
you use a time specification that is more strict than needed there is no problem, so the standard .ucf file have
the clocks specified at 100Mhz. If the project builds (as example1 does) with this specification it is still
guaranteed to work at lower clock speeds. If you add new clock nets into your design then you need to add
new timing constraints into your design.
Creating the Bitstream for the Camera Example
Once the project has been opened as described above:
1. In the "Sources in project" window (Project Navigator), highlight (single-click on) "top".
This is extremely important! Otherwise, nothing will work!
2. Double-click on the "Generate Programming File" item located in the "Processes for Current
Source".
This will trigger the following activity:
Complete synthesis, using all of the project's source files. Since warnings are generated at this
stage, you should see a yellow exclamation mark appear besides the "Synthesize" item in the
Processes window.
Complete Implementation:
- "Translation"
- Mapping
- Placing
- Routing
3. Creation of the bit-stream:
Note that this stage runs a Design-Rule-Check (DRC). The DRC can potentially detect anomalies
created by the Place-and-Route phase (especially with Virtex II ES parts).
When the processing ends, the proper bit-stream file, with extension ".rbt"can be found in the

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project directory.
4. In the "Pin Report" verify a few pins from the busses, to check that the ucf file has been used.
If you see different assignments, STOP HERE, and verify the UCF file selected for the project.
You can now download this file on your FPGA board and see how it works.
Note that the user_ap level includes a very large counter, which divides the main system clock and
drives the LED #4. It is then obvious to see if the part has been properly programmed and
downloaded: the LED should flash.
If the LED does not flash, try a hardware reset. The DLL used in the clock generation often does not
start until a hardware reset. If the LED still does not flash we recommend that you shut down the PC
or reprogram the device using a "safe" bit-stream. Otherwise, some electrical conflicts may happen
(see below).
Possible causes for the device failure to operate are:
1. Wrong (or no) UCF file. This happens (for example) if you select the XST-version of the UCF
with a Leonardo Spectrum (or Synplify) synthesis. The pin assignment for all the vectors (busses)
will be ignored, and these pins will be distributed in a quasi-random fashion!
2. Wrong parameters in the CONFIG package.
3. Design Error.
If nothing seems obvious, re-run the camera DSP example, then return to the original camera example.

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The FPGA Design
Camera Inputs
The first major functional block in the Camera example is the VHDL module AREASCAN. This
module is used to directly interface to the signals of the camera that you are using. This module expects
as inputs, a Line-Valid signal, a Frame-Valid signal, a Pixel Strobe (Clock), an optional Data-Valid signal
and between one to four bytes of data.
Signal Voltage levels
The example connects to the RS-422 signals of your digital camera by connecting the positive signal of
the differential pair to the appropriate signal on Connector A. The negative signal from the differential
signal pair should be left unconnected. Any available ‘Ground’ connections provided by your camera
should be connected to the GND pins of Connector A.
RS-422 uses 5V levels, so the camera signals cannot be directly connected to the FPGA. The
consequence of this is that 100R series resistors are required on all inputs to the FPGA. This is to
resolve the issue of 5V compatibility with the Virtex-4 FX FPGA, which does not allow the direct
connection of 5V inputs.
Please ensure that if you intend to use the HERON-FPGA12 for implementing an RS-422 camera
interface that you specify the inclusion of the series resistors for your board when you place the order.
Camera Speeds
The .ucf file for the example project contains a setting for TS_dio_a_12_ which is the pixel clock
speed. This clock domain is used for all of the image processing functions and the writing of the Core
Gen FIFO.
The AREASCAN component presents as outputs, a pixel stream organised as a pixel clock
(pixel_clock), data valid signal (dvalid_out), end-of-line signal (eol_out), end-of-frame signal (eof_out)
and data bus (data_out (31 downto 0)).

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Automatic Region of Interest Detection
Data output by the AREASCAN component is monitored by an automatic region of interest function.
This process counts the number of pixels in a line and number of lines in a frame to create the Pixel-
Total and Line-Total values.
The process also detects whether there are any dark (black) pixels on the left side, right side, top or
bottom of the image, creating First-Pixel, Last-Pixel, First-Line and Last-Line values respectively.
These six values can be read using the HSB message interface. This allows controlling software to
automatically detect where the active area of the image is. The values returned by the Automatic
Region-of-Interest can be used in calculating the values with which to program the Capture Region of
Interest.
The advantage of doing so over calculating the values by hand is that correct frame capture can be
guaranteed. For example, if a camera is operating with 400 pixels in a line and 500 lines in a frame, and
the region of interest and DSP read process (typically HeronRead) are expecting 512 pixels x 512 lines
from hand calculated values, then the capture process will never complete. This is because more data is
expected than can be generated in one frame by the camera.
Using the automatically calculated values, the frame capture should always complete, as the software
will be working with a frame size that is achievable. This is because the frame size used has been
calculated from monitoring what the camera produces.
Capture Region of Interest
Data output by the AREASCAN component is put through a programmable region of interest. The
module ROI performs a region of interest operation by using a pixel counter and a line counter, along
with a pixel start position, pixel stop position, line start position and line stop position.
Starting with the first pixel in each line of data, the pixel counter starts at 0 and counts up. If the
current pixel count is equal to or greater than the pixel start value, AND if the pixel count is less than
or equal to the pixel stop value then that pixel is output. All other pixels in the line will be discarded.
Similarly, starting with the first line in each frame of data, the line counter starts at 0 and counts up. If
the current line count is equal to or greater than the line start value, AND if the line count is less than
or equal to the line stop value then that line is output. All other lines in the frame will be discarded.
In the example the pixel start, pixel stop, line start and line stop values are all programmed over the
HSB message interface. The values used can be calculated from the values returned by the Automatic
Region of Interest logic.
Frame Control
The component FRAME_CONTROL controls when frames are output over the HERON FIFO
Write Interface. The FRAME_CONTROL component can operate in two ways. It can be set-up to
continuously output frames by setting the ‘continuous’ input high, or can be set-up to output between
N frames (where N is 1 to 15) by setting a value on the ‘frames’ bus input and asserting the load signal.
After the region of interest has processed each frame, whether that frame will be output or not depends
on the frame-control component. In the example the continuous mode and N-frames mode are
programmed over the HSB message interface.
Output Packing and Synchronisation
The component PACK_SYNC takes the frames that are output by the FRAME_CONTROL
component and packs the data ready for transmission through the HERON FIFOs. How the data is
packed will depend on the mode of camera operation.