IDT VersaClock 6E Operating instructions

1©2019 Integrated Device Technology, Inc. June 7, 2019
Register Descriptions
The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
VersaClock 6E clock generators.
For details of product operation, refer to the product datasheet.
VersaClock 6E Register Set
The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers (Figure 1). The non-volatile registers are One-Time
Programmable (OTP), and bit values can only be changed from 1 (unburned state) to 0.
The OTP registers include factory trim data and four user configuration tables (Figure 1,Table 3). This document does not describe the
format or methods for programming factory trim data, which is programmed by the factory before shipment.
Each configuration table contains all the information to set up the device's output frequencies. When these configuration tables are
programmed, the device will automatically load the RAM registers with the desired configuration on power-up. The device initializes in
either I2C mode or selection-pin mode, depending on the state of the OUT0/SELB_I2C pin on power-up, and remains in the selected
mode until power is toggled (Table 2). When powered up in I²C mode, the first configuration table, CFG0, is loaded. When powered up in
selection-pin mode, the SEL0 and SEL1 inputs are decoded to select one of the four configuration tables CFG0-CFG3.
The RAM registers (Table 4) include Status registers for read-back of the device's operating conditions in I2C mode.
Figure 1. Register Maps
Table 1. Automotive VersaClock 6E Product(s)
Product Description Package
5P49V60 5-Output VersaClock 6E (automotive, AEC-Q100) 24 pins
Automotive VersaClock®6E Register
Descriptions and Programming Guide

2©2019 Integrated Device Technology, Inc. June 7, 2019
Automotive VersaClock®6E Register Descriptions and Programming Guide
Contents
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
VersaClock 6E Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
User Configuration Table Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I2C Interface and Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
VersaClock 6E Family Power-Up Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
OTP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-System VersaClock 6E OTP Non-Volatile Programming via I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Default Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OTP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Factory Reserved Registers for Internal Use Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configuration Register Detail and Functionality Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Shutdown Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Case 1: Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Case 2: Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting Up a Low-Power Shutdown Mode through I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Crystal Load Capacitor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short Example of Programming Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PLL Pre-Divider Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PLL Fractional Feedback Divider and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PLL Loop Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fractional Output Dividers and Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Example of FOD calculation for SSCE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Divider Control Settings (Table 47 through Table 50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output Divider Integer Settings (Table 51 through Table 58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output Divider Fractional and Spread Settings (Table 59 through Table 94) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Output Divider Skew Integer and Fractional Part Registers Settings (Table 95 through Table 107) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock Output Configurations Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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Automotive VersaClock®6E Register Descriptions and Programming Guide
User Configuration Table Selection
At power-up, the voltage at OUT0_SEL_I2CB pin 24 is latched by the part and used to select the state of SEL0/SCL pin 9 and SEL1/SDA
pin 8 (Table 2).
If a weak pull-up (10kΩ) is placed on OUT0_SEL_I2CB, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select inputs,
SEL0 and SEL1. Connecting SEL0 and SEL1 to VDDD and/or GND selects one of 4 configuration register sets, CFG0 through CFG3,
which is then loaded into the non-volatile configuration registers to configure the clock synthesizer.
If a weak pull-down is placed on OUT0_SEL_I2CB (or if it is left floating to use internal pull-down), the pins SEL0 and SEL1 will be
configured as a I2C interface's SDA and SCL slave bus. Configuration register set CFG0 is always loaded into the non-volatile
configuration registers to configure the clock synthesizer. The host system can use the I2C bus to update the non-volatile configuration
registers to change the configuration, and to read status registers.
I2C Interface and Register Access
When powered up in I2C mode (Table 2), the device allows access to internal RAM registers (Table 4). The OTP registers (Table 3) are
programmed by loading the desired values into the RAM registers that shadow the target OTP registers (Table 4), and initiating the
internal programming sequence for the desired register range.
Users should not write to the Trim RAM in address range 0x01–0x0F, or the Test RAM in address range 0x6A–0x6F, and should only write
to the OTP Control in address range 0x70–0x7F when programming the OTP.
The RAM in address range 0x80–0x8F is not used by the device and may be used for any purpose.
Table 2. Power-Up Setting of Hardware Select Pin vs I2C Mode, and Default OTP Configuration Register
OUT0_SEL_I2CB Strap at
Power-Up SEL1/SDA pin SEL0/SCL pin Function
10kΩpull-up
0 0 OTP bank CFG0 used to initialize RAM configuration registers.
0 1 OTP bank CFG1 used to initialize RAM configuration registers.
1 0 OTP bank CFG2 used to initialize RAM configuration registers.
1 1 OTP bank CFG3 used to initialize RAM configuration registers.
10kΩpull-down or floating SDA SCL I2C bus enabled to access registers.
OTP bank CFG0 used to initialize RAM configuration registers.
Table 3. OTP Register Map Summary
Register Range OTP Register Block Name Register Block Description
0x000 OTP Control OTP burned status & I²C address setting.
0x001–0x00F Trim Presets Program default settings. See page 6.
0x010–0x069 CFG0 User configuration settings bank 0.
0x06A–0x0C3 CFG1 User configuration settings bank 1.
0x0C4–0x11D CFG2 User configuration settings bank 2.
0x11E–0x177 CFG3 User configuration settings bank 3.
0x178–0x1AF Factory Use Factory settings–do not over-program.

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Automotive VersaClock®6E Register Descriptions and Programming Guide
VersaClock 6E Family Power-Up Behavior
On power-up, the following RAM register loading sequence occurs:
1. The RAM registers always initialize to a hard-wired set of default values, which are also the 'Default register values' for OTP shown in
subsequent tables.
2. If OTP_ burned bit D7 = 0 in the OTP Control register (Table 7), this indicates that the both the Trim OTP tables and at least one of
the four OTP user configuration tables have been programmed.
• Factory programmed product is typically shipped in this condition. Device has factory trim performed and with required
customization written into OTP memory. IDT programs user customization at factory test. Please visit our website for device
customization request.
• Trim RAM data will be updated from the Trim OTP registers into the appropriate trim RAM registers, overwriting the initial default
values.
• Configuration data will be read from the one of the four OTP user configuration tables into the appropriate configuration RAM
registers, overwriting the initial default values. When powered up in I2C mode, the first configuration table, CFG0, is loaded. When
powered up in selection-pin mode, the SEL0 and SEL1 input pins are decoded to select one of the four configuration tables (Table
23).
• Initialization is now complete, and the part will operate per the configuration settings.
3. If OTP_ burned bit D7 = 1 in the OTP Control register (Table 7), this indicates that the four OTP user configuration tables are
unconfigured.
• Un-programmed product is shipped in this condition and ready for user self-program and customization.
• Configuration RAM data remains at the hard-wired set of default values.
• Initialization is now complete, and the part will operate per the default configuration settings.
• When powered up in I2C mode, the Configuration RAM registers can be written with the user's desired settings by the host system,
and the clock generator operated without ever programming any of the four OTP user configuration tables. Alternatively, the host
system (or a programming system) can program one of more of the four OTP user configuration tables, and also clear the OTP_
burned bit D7 in the OTP Control register (Table 7) to 0. The VersaClock 6E device will follow the behavior according to section 0
above for subsequent power ups.
Table 4. RAM Register Map Summary
Register Range RAM Register Block Corresponding OTP Register
Block Name Corresponding OTP Register Block Address Range
0x00 OTP Control OTP Control 0x000
0x01–0x0F Trim Trim 0x000–0x00F
0x10–0x1F Configuration–Main
CFG0
CFG1
CFG2
CFG3
0x010–0x069
0x06A–0x0C3
0x0C4–0x11D
0x11E–0x177
0x20–0x2F Configuration–CLK1
0x30–0x3F Configuration–CLK2
0x40–0x4F Configuration–CLK3
0x50–0x5F Configuration–CLK4
0x60–0x69 Configuration–Outputs
0x6A–0x6F Factory Use — —
0x70–0x7F OTP Control — —
0x80–0x8F Unused RAM — —
0x90–0x9F Factory Use — —

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Automotive VersaClock®6E Register Descriptions and Programming Guide
OTP Programming
The steps for OTP programming are given in Table 5. The procedure is to write the desired default data to the appropriate RAM registers,
and then to instruct the part to burn a desired register address range into OTP.
The RAM registers have an 8-bit register address (0x00 to 0x9F), while the user OTP registers have a 9-bit address (0x000 to 0x177).
This is because there are 4 banks of configuration data in OTP. The OTP addressing therefore extends across two RAM registers (Table
5). The 9-bit user start address is set by register 0x73[7:0] + 0x74[7]. The 9-bit user end address is set by register 0x75[7:0] + 0x76[7].
Table 5. OTP Programming Procedure
Step Procedure Notes
0Connect all VDD pins to a single 3.3V, with OUT0_SEL_I2CB pin
left floating. Power on the part in I²C mode.
1 Wait 100ms. Part power-up initialization.
2Write device RAM configuration registers 0x10 to 0x69 to the
desired state.
These RAM values will be programmed into OTP as new
default register values.
3 Write registers 0x73 to 0x78 following the procedure in Table 5. Set burn register source address range and destination register
bank CFG0, 1, 2, or 3.
4 Write register 0x72 = 0xF0. Reset burn bit.
5 Write register 0x72 = 0xF8. Burn the OTP range defined above.
6 Wait 500ms. Wait for burn to complete. Device stops acknowledging while
burning.
7 Write register 0x72 = 0xF0. Reset burn bit.
8 Write register 0x72 = 0xF8. Repeat the burn.
9 Wait 500ms. Wait for burn to complete. Device stops acknowledging while
burning.
10 Write register 0x72 = 0xF0. Reset burn bit.
11 Done programming. Programming complete.
12 Write register 0x72 = 0xF2. Perform margin read.
13 Write register 0x72 = 0xF0. Reset margin read bit.
14
Read register 0x9F:
If bit D1 = 0, programming was successful.
If bit D1 = 1, programming failed.
Test if OTP programming was successful.
15 Write register 0x9F = 0x00. Reset margin read status bit.
16 One configuration register bank (CFG0, 1, 2, or 3) is now burned.
To burn another bank, repeat the procedure from Step 2. Burn further configuration register banks if desired.
17
When all desired configuration register bank have been burned,
write device OTP Control register 0x00 with OTP_burned bit D7
clear.
Burn OTP Control register clearing OTP_burned bit D7. This
sets the part to load configuration data from OTP on power-up.
18 Exit. Done.

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Automotive VersaClock®6E Register Descriptions and Programming Guide
* Configuration CFG0 includes the Trim presets in 0x01 to 0x0F.
Use the steps in the following example as guidelines to program configuration 0 OTP registers:
1. Write the value from register address 0x00 to 0x69 (first bank) to RAM registers.
Starting at Address 0x00, write data: 61 F3 00 00 00 00 00 00 00 FF FD C0 00 B6 B4 92 A8 CC 81 80 00 03 8C 03 20 00 00 00 9F FF F0
80 00 81 00 00 00 00 00 00 00 00 04 00 01 01 90 00 00 8F 00 00 00 00 00 00 00 00 04 00 00 9C 40 00 00 81 02 00 00 00 00 00 00 00 04
00 00 00 C0 00 00 81 00 00 00 00 00 00 00 00 04 00 00 00 A0 00 3B 01 3B 00 BB 01 7B 01 FF FC
In above example, 61 is the value in register 0x00 that correspond to I2C address D4 and the trim presets are recommended defaults:
0x01–0x0F = “F3 00 00 00 00 00 00 00 FF FD C0 00 B6 B4 92".
In above example, a 25MHz crystal is expected, OUT0 is enabled, OUT1 is 50MHz LVCMOS, OUT2 is 10KHz LVCMOS, OUT3 is 100MHz
LVCMOSD and OUT4 is 125MHz LVDS. In case of 5P49V6967 and 5P49V6968, the OUT3 setting will determine the frequency of the
LP-HCSL outputs.
2. Write the following values to program the OTP with config0 and trim bits (Table 6):
• Reg Address (hex): 73 74 75 76 77 78
• Configuration 0: 00 4E 34 E1 00 00
3. Start Burn with Reg 0x72 set to F8.
4. Wait 500ms.
5. Reset Burn Start Bit 0x72 set to F0.
In-System VersaClock 6E OTP Non-Volatile Programming via I2C
For in-system programming of OTP, it is required to power the VDDA and VDDD pins from 3.3V. Other VDD pins can be powered from
1.8V, 2.5V or 3.3V, whatever is needed for the application.
Burning OTP requires a high internal voltage. The circuit responsible for generating the high internal voltage needs at least 3.3V to
generate a high enough internal voltage for reliable OTP burning with good data retention.
Default Register Values
The following tables have a column “Default Value”. These are values as they show in a 5P49V69xxA000, so called “blank” device that is
meant for field programming. When the device is still un-programmed, it runs a default mode with OUT0 enabled and OUT1 = 100MHz,
assuming a 25MHz crystal is connected. The default values are the register settings for this default mode.
Table 6. OTP Addressing For Programming
Register
User Start
Address[8:0]
Part-Select
Bit 0x73
Enable
Sub-block's
Test Mode
0x74
User End
Address[8:0]
Part-SelectBit
0x75
User End
Address[8:0]
Part-Select
Bits 0x76
BurnedRegister
Start Address
0x77
Read Register
Start Address
0x78
Registers
Burned To
OTP
OTP Control register 0x00 0x4E 0x00 0x61 0x00 0x00 0x00
Configuration CFG0* 0x00 0x4E 0x34 0xE1 0x00 0x00 0x00 to 0x69
Configuration CFG1 0x35 0x4E 0x61 0xE1 0x10 0x10 0x10 to 0x69
Configuration CFG2 0x62 0x4E 0x8E 0xE1 0x10 0x10 0x10 to 0x69
Configuration CFG3 0x8F 0x4E 0xBB 0xE1 0x10 0x10 0x10 to 0x69

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Automotive VersaClock®6E Register Descriptions and Programming Guide
OTP Control Register
The I2C slave address can be changed from the default 0xD4 to 0xD0 by programming the I2C_ADDR bit D0. Note that the I2C address
change occurs on the I2C ACK of the write transaction. An I2C write sequence to register 0x00 that changes the value of I2C_ADDR bit
D0 should be followed by an I2C STOP condition. Further I2C transactions to the part use the new address.
In the OTP Control Register (Table 7) bits can be set for the OTP Burn and OTP Trim status, VC6E or MEMS use and I2C address setting.
Four bits are left unused.
* The trim values are commonly written with default values and the OTP_TRIM bit is left at “1”.
Factory Reserved Registers for Internal Use Only
* Configuration Lock bits can be used to prevent future OTP burning that can modify OTP content.
Table 7. RAM0 0x00 – OTP Control Register
Bits Default Value Name Function
D7 1 OTP_burned
It's an active low state that indicates all the OTP burn process is done.
D7 = 1 tells the chip that OTP is not burned and it will run the default mode.
D7 = 0 tells the chip that OTP is burned and it will transfer OTP content to the registers for
operating settings.
D6 1 OTP_TRIM An active low state that indicates OTP trim part is burned.*
D5 1 Unused Unused.
D4 1 Unused Unused.
D3 1 Unused Unused.
D2 1 Unused Unused.
D1 1 Unused Unused.
D0 1 Device I2C_ADDR If I2C_ADDR = 0 then D0 and if I2C_ADDR = 1 then D4.
Table 8. RAM0 – 0x01: Factory Reserved Bits - Device ID for Chip Identification
Bits Default Value Name Function
D7 1 CFG0_LOCK* Set to “0” to disable burning OTP of Configuration 0.
D6 1 CFG1_LOCK* Set to “0” to disable burning OTP of Configuration 1.
D5 1 CFG2_LOCK* Set to “0” to disable burning OTP of Configuration 2.
D4 1 CFG3_LOCK* Set to “0” to disable burning OTP of Configuration 3.
D3 1 Unused Unused.
D2 1 Unused Unused.
D1 1 Reserved Factory reserved, leave at “1”.
D0 1 Reserved Factory reserved, leave at “1”.

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Automotive VersaClock®6E Register Descriptions and Programming Guide
Table 9. RAM0 – 0x02: Factory Reserved Bits - ADC Gain Setting
Bits Default Value Name Function
D7 0
ADC gain[7:0] ADC gain setting - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 10. RAM0 – 0x03: Factory Reserved Bits - ADC Gain Setting
Bits Default Value Name Function
D7 1
ADC gain[15:8] ADC gain setting - Factory reserved bits
D6 1
D5 1
D4 1
D3 1
D2 1
D1 1
D0 1
Table 11. RAM0 – 0x04: Factory Reserved Bits - ADC OFFSET
Bits Default Value Name Function
D7 0
ADC offset[7:0] ADC offset - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0

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Automotive VersaClock®6E Register Descriptions and Programming Guide
Table 12. RAM0 – 0x05: Factory reserved bits - ADC OFFSET
Bits Default Value Name Function
D7 0
ADC offset[15:8] ADC offset - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 13. RAM0 – 0x06: Factory Reserved Bits
Bits Default Value Name Function
D7 0
TEMPY[7:0] Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 14. RAM0 – 0x07: Factory Reserved Bits
Bits Default Value Name Function
D7 0
OFFSET_TBIN<7:0> Unused Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0

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Automotive VersaClock®6E Register Descriptions and Programming Guide
Table 15. RAM0 – 0x08: Factory Reserved Bits
Bits Default Value Name Function
D7 0
GAIN<7:0> Unused Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 16. RAM0 – 0x09: Factory Reserved Bits
Bits Default Value Name Function
D7 1
test[3:0] Factory reserved bits
D6 1
D5 1
D4 1
D3 1
NP[3:0] Factory reserved bits
D2 1
D1 1
D0 1
Table 17. RAM0 – 0x0A: Factory Reserved Bits
Bits Default Value Name Function
D7 1 Reserved
Factory reserved bits
D6 1 Reserved
D5 1 Reserved
D4 1 Reserved
D3 1 Reserved
D2 1 Reserved
D1 0 Reserved
D0 1 Reserved