Industrial Micro Systems 464 User manual
'-
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INDUSTRIAL
MICRO
SYSTEMS.
INC.
MODEL
464
64K
DYNAMIC RANDOM
ACCESS
MEMORY BOARD
***********************************.****************************************.*.
•2MHZ OR 4MHZ OPERATION •
8080
OR
Z80
OPERATION
•PARITY
CIRCUITRY
•
HIDDEN
REFRESH
(Ml
CYCLE)
•PHANTOM LINE
(pIN
67)
•
NO
WAIT
STATES
0•BANK
SELECT
LOGIC •
LOW
POWER
CONSUMPTION
V•FRONT PANEL COMPATIBLE
.6A
+8
VOLTS
•SELECTABLE PORT
ADDRESS
.ZA
+16
VOLTS
'---"
•
AVAILABLE
IN
HK.
48K.
OR
64K
.001A
-
-16
VOLTS
MOOELS
"-'
"
"-
GENERAL
PESCRIPTION
The
Model
464
Dynamic
Ram
Memory
Board
is
fully
buffered
and
uses 16K X 1
bit
dynamic memory
circuits.
The
boards
are
tested
and
burned
in
at
70
degrees
centigrade
under
diagnostic
test
to
insure
reliable
operarions.
The
464
board
may
be
ordered
as a
32K,
48K,
or
64K
memory
board.
In
each
of
these
configurations,
the
memory is
organized
into
16K
byte
banks.
Two
modes
of
operation
are
provided,
Normal Mode and Bank Mode.
In
the
normal
mode,
the
16K
byte
banks
occupy
contiguous
address space.
In
the
bank
mode
of
op~ation,
the
board
is
initially
disabled
and
each
16K
byte
bank
may
be
mapped
into
selected
quadrants
of
memory (see Bank
Selection),
The
464
board
provides
a
"Phantom
Line"
input
for
systems
with
ROM
memories which
utilize
this
feature.
The
user
may also
configure
the
board
to
accept
the
front
panel
deposit
signal,
M-WRITE.
\
INDUSTRIAL
MICRO
SYSTEMS.
INC.
D00464
REV A
8/12/80
Page
1
of
6
·--
The
464
board
features
a
parity
circuit
to
provide
increased
data
security.
A
parity
bit
is
written
during
every memory
write
such
that
the
total
number
of
"1"
bits
written
are
odd.
During
memory
reads
the
total
number
of
"1"
bits
are checked.
The
parity
error
is
set
if
the
number
of
"1"
bits
checked
are
even,
Parity
errors
during
memory reads
can
interrupt
or
stop
the
CPU. ALED
r-
indicator
on
the
board
is
lighted
to
indicate
the
error,
The
status
of
the
parity
circuit
may
be
read
J
from
the
memory
board's
I/O
Port.
CONFIGURING
THE
464
BOARD
PHANTOM LINE OACK JO)
The
phantom
signal
(pin
67)
shunt
is
etched
so
that
the
board
will
be
disabled
by
an
activated
Phantom
Line.
1£
this
is
not
desirable,
then
the
etch
connecting
the
two
pads
of
JD (PH) may
be
cut
on
the
rear
of
the
board.
aD
must
be
connected
when
using
the
464
board
with
Industrial
Micro
System
CPU
boards,)
Note:
The
Phantom
Line
affects
memory
read
operations
only.
Memory
write
operations
are
not
affected
by
the
Phantom
Line. . ,
EN
I/O
OACK JB)
-...J
THE
"EN
I/O"
(Enable I/O)
shunt
JB
must
be
installed
for
the
board
to
respond
to
I/O
commands.
This
will
be necessary
for
bank
mode
or
parity
operations.
I/O
SELECTION
OACK
JC)
The
selection
of
the
boards
I/O
address
is
done
on
jack
JC.
The
jack
is
labeled
0-7
(top
to
bottom)
for
the
respective
address
bits
(AO-A7)
of
the
I/O
address.
A
"1"
is
programmed
by remoyin¥ a
shunt.
Thus,
to
program
I/O
address
OFH
the
top
four
shunts
(0-3)
would
be
removed
("l's")
and
.J
the
bottom
four
shunts
(4-7)
would
be
installed
("O's"),
(Note
that
the
liEN
1/0"
shunt
must
be
on
for
the
board
to
respond
to
the
I/O
command.)
CPU
SELECTION
OACK
JF)
,i
The
8080
shunt
(JF)
should
be
installed
for
systems
using
8080
CPU's.
For
2-80
systems
this
shunt
should
be
removed.
FRONT
PANEL OACK JH)
If
the
464
board
is
to
be
used
with
an
"IMSAI"
front
panel,
the
shunt
JH
must
be
in
the
right-most
(FP)
position.
MEMORY
SPEED
OACK JA)
The
JA
shunt
controls
the
timing
of
the
memory
board.
The
H
position
is
for
200NS
RAMS
and
the
L
position
is
for
250NS
RAMS.
This
shunt
is
factory
installed
on
the
H
position
and normally
should
not
be
changed.
High
speed
operation
is
required
for
the
2-80
processor.
INDUSTRIAL
MICRO
SYSTEMS.
INC.
000464
REV A
8/12/80
Page
2
of
6
PARITY
INTERRUPT
OACK
JG)
Jack
JG
allows
selection
of
eight
different
responses
to
a
parity
error.
The
selections
are:
SHUNT
POSITION
VIl
VI2
VB
VI4
VI5
INT
NMI
RDY
S100 BUS PIN NO.
05
06
07
08
09
73
12
72
INTERRUPT
SELECTEp
VECTORED INTERRUPT 1
VECTORED INTERRUPT 2
VECTORED INTERRUPT 3
VECTORED INTERRUPT 4
VECTORED INTERRUPT 5
PINT Line
Non-maskable
INT
(Z-80
only)
PRDY Line (Parity
Error
Stops
CPU)
When
using
the
parity
error
circuit,
the
user
must
initially
write
into
all memory
locations
after
power
is
initially
applied
to
condition
all
the
parity
bits.
After
the
memory
is
initialized,
the
parity
error
circuit
must
be
reset.
The
parity
error
circuit
is
reset
by any
output
to
the
I/O
port
on
the
memory
board.
The
Power
On
Clear
signal
(POC
Pin
99
on
S100
bus)
also
resets
the
parity
error
circuit.
The
state
of
the
parity
circuit
may be sensed
by
reading
bit
"0"
of
the
I/O
port
on
the
memory
board.
A
"1"
bit
indicates
a
parity
error
has
occurred.
NORMAL/BANK
MODE
OACK
JE)
The
"bank"
mode
shunt
should
be
installed
only
if
the
board
is
to
be
used
in
the
Bank
Switched
mode.
In
this
mode
the
board
will
respond
to
all addresses
from
0000
to
FFFF
hex.
For
memories
that
are
to
be
bank selected,
this
shunt
should
be
installed.
NORMAL MODE
In
the
normal mode,
shunt
JE removed,
the
four
16K memory banks occupy
the
entire
16
bit
address
space
0000
thru
FFFF
hex.
In
this
mode, each 16K
bank
may be
controlled
individually
by an
output
to
the
board's
I/O
Port.
A
"one"
bit
disables
the
associated
bank.
Control
is
on a
bit
basis,
thus:
OUTPUT
DATA
CONTROLLED
MEMORY
BANK
(HEX)
BANK
MOPE
BIT
0
BIT
1
BIT 2
BIT
3
0000-3FFF
4000-7FFF
8000-BFFF
COOO-FFFF
(omitted
in
32K version)
(omitted
in
32K &48K
version)
In
the
Bank
Mode
(Shunt
JE installed)
the
board
responds ro a
combmation
of
bits
and
bank
selection
is
not
done
on
a
bit
basis.
Codes
are
provided
for
a
variety
of
configurations
defined
in
the
following
table.
Initially,
the
board
is
deselected
by
the
Power
On
Clear signal.
The
464
memory
can
be
used
in
a
16K,
32K or 48K
bank
selection
scheme. When
the
464
board
is ordered
in
a48K
configuration,
Bank 3
is
omitted.
When
ordered
in
a32K
configuration,
Banks 2
and
3
are
omitted.
INDUSTRIAL
MICRO
SYSTEMS,
INC.
000464
REV
A
8/12/80
Page
3
of
6
BANK MODE TABLE
OUTPUT
DATA
o
1
2
3
4
5
6
7
8
9
A
B
C
D
B
F
MEMORY MAPPING
All
Banks
Deselected
Banks
0&1
Occupy
Addresses
Banks
2&3
Occupy
Addresses
Banks
0,
1, &2Occupy
Addresses
Banks 0&1
Occupy
Addresses
Banks
2&3Occupy
Addresses
Bank
0Occupies Addresses
Bank
0
Occupies
Addresses
Bank
1Occupies Addresses
Bank
1Occupies
Addresses
Bank
2Occupies Addresses
Bank 3Occupies
Addresses
Bank
2Occupies
Addresses
Bank 3Occupies
Addresses
Bank
3Occupies
Addresses
Bank 3
Occupies
Addresses
8000-FFFF
(32K)
8000-FFFF
(32K)
OOOO-BFFF (48K)
0000-7FFF
(32K)
0000-7FFF
(32K)
COOO-FFFF (16K)
0000-3FFF
(l6K)
0000-3FFF
(l6K)
COOO-FFFF (16K)
0000-3FFF
(l6K)
0000-3FFF
(l6K)
COOO-FFFF (16K)
4000-7FFF
(l6K)
8000-BFFF
(l6K)
COOO-FFFF
(l6K)
.-
J
STANDARD CONFIGURATION
IMS
supplies
the
464
board
configured
as
follows:
JACK
DESCRIPTION
STANDARD
CONFIGURATION
JA Memory
Speed
H
Position
Shunted
JB
En
I/O
Open
JC
I/O
Selection
All
Positions
Shunted
JD
Phantom
Line
Shunted
(E
tch)
JB
Normal/Bank Mode
Open
JF
CPU
Selection
Open
JG
Parity
Interrupt
All
Open
JH
Front
Panel
Left
Position
Shunted
.,
Four
spare
shunts
are
installed
on
the
upper
pins
of
Jack
G.
These
pins
are
all
connected
by
etch
and
serve
as a
convenient
place
to
store
spare
shunts.
Note:
464
boards
shipped
in
systems
will
normally
be
configured
to
the
system requirements.
INDUSTRIAL
MICRO
SYSTEMS
INC.
000464
REV A
8/12/80
Page
4
of
6
RAS2
RASl
BANK
RAS3
RAsa
AM
S.
INC.
D00464
REV
A
8/12/80
Pale
5
of
6
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RAS3
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ARRAY
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8
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