Infineon Cypress EZ-BLE CYBLE-022001-00 User manual

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CYBLE-022001-00
EZ-BLE™ Creator Module
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-95662 Rev. *N Revised December 23, 2020
EZ-BLE™ Creator Module
General Description
The Cypress CYBLE-022001-00 is a fully certified and qualified
module supporting Bluetooth® Low Energy wireless
communication. The CYBLE-022001-00 is a turnkey solution
and includes onboard crystal oscillators, chip antenna, passive
components, and Cypress PSoC® 4 Bluetooth LE. Refer to the
PSoC 4 Bluetooth LE datasheet for additional details on the
capabilities of the PSoC 4 Bluetooth LE device used on this
module.
The CYBLE-022001-00 supports a number of peripheral
functions (ADC, timers, counters, PWM) and serial
communication protocols (I2C, UART, SPI) through its
programmable architecture. The CYBLE-022001-00 includes a
royalty-free Bluetooth LE stack compatible with Bluetooth 5.1
and provides up to 16 GPIOs in a small 10 × 10 × 1.80 mm
package.
The CYBLE-022001-00 is a complete solution and an ideal fit for
applications requiring Bluetooth LE wireless connectivity.
Module Description
■Module size: 10.0 mm ×10.0 mm × 1.80 mm (with shield)
■Bluetooth 5.1 single-mode module
■Industrial temperature range: –40 °C to +85 °C
■32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■128-KB flash memory, 16-KB SRAM memory
■Watchdog timer with dedicated internal low-speed oscillator
(ILO)
■Two-pin SWD for programming
■Up to 16 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output
■Certified to FCC, ISED, MIC, KC, ANATEL, and CE regulations
❐FCC ID: WAP2001
❐IC ID: 7922A-2001
❐MIC ID: 005-101007
❐KC ID: MSIP-CRM-Cyp-2001
■Bluetooth SIG 5.1 qualified
❐QDID: 141250
❐Declaration ID: U048555
Power Consumption
■TX output power: –18 dbm to +3 dbm
■Received signal strength indicator (RSSI) with 1-dB resolution
■TX current consumption of 15.6 mA (radio only, 0 dbm)
■RX current consumption of 16.4 mA (radio only)
■Low power mode support
❐Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on
❐Hibernate: 150 nA with SRAM retention
❐Stop: 60 nA with XRES wakeup
Functional Capabilities
■Up to 15 capacitive sensors for buttons or sliders with
best-in-class signal-to-noise ration (SNR) and liquid tolerance
■12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■Two serial communication blocks (SCBs) supporting I2C
(master/slave), SPI (master/slave), or UART
■Four dedicated 16-bit timer, counter, or PWM blocks
(TCPWMs)
■Programmable low voltage detect (LVD) from 1.8 V to 4.5 V
■I2S master interface
■Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
■Switches between Central and Peripheral roles on-the-go
■Standard Bluetooth Low Energy profiles and services for
interoperability
■Custom profile and service for specific use cases
Benefits
The CYBLE-022001-00 module is provided as a turnkey
solution, including all necessary hardware required to use
Bluetooth LE communication standards.
■Proven, qualified, and certified hardware design ready to use
■Small footprint (10 × 10 mm × 1.80 mm), perfect for space
constrained applications
■Reprogrammable architecture
■Fully certified module eliminates the time needed for design,
development and certification processes
■Bluetooth SIG qualified with QDID and Declaration ID
■Flexible communication protocol support
■PSoC Creator™ provides an easy-to-use integrated design
environment (IDE) to configure, develop, program, and test a
Bluetooth LE application

CYBLE-022001-00
Document Number: 001-95662 Rev. *N Page 2 of 41
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
■Overview: EZ-BLE Module Portfolio, Module Roadmap
■PSoC 4 BLE Silicon Datasheet
■Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
❐AN96841 - Getting Started with EZ-BLE Module
❐AN91267 - Getting Started with PSoC® 4 BLE
❐AN97060 - PSoC® 4 BLE and PRoC™ BLE - Over-The-Air
(OTA) Device Firmware Upgrade (DFU) Guide
❐AN91162 - Creating a BLE Custom Profile
❐AN91184 - PSoC® 4 BLE - Designing BLE Applications
❐AN92584 - Designing for Low Power and Estimating Battery
Life for BLE Applications
❐AN85951 - PSoC® 4 CapSense® Design Guide
❐AN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator Selec-
tion and Tuning Techniques
❐AN91445 - Antenna Design and RF Layout Guidelines
■Technical Reference Manual (TRM):
❐PRoC® BLE Technical Reference Manual
■Knowledge Base Articles
❐KBA97279 - Pin Mapping Differences Between the
EZ-BLE™ Creator Evaluation Board
(CYBLE-022001-EVAL) and the BLE Pioneer Kit (CY8CK-
IT-042-BLE)
❐KBA97094 - RF Regulatory Certifications for EZ-BLE™
Creator Module
❐KBA97095 - EZ-BLE™ Module Placement
❐KBA213976 - FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
❐KBA210802 - Queries on BLE Qualification and Declaration
Processes
❐KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
■Development Kits:
❐CYBLE-022001-EVAL, CYBLE-022001-00 Evaluation Board
❐CY8CKIT-042-BLE, Bluetooth® Low Energy Pioneer Kit
❐CY8CKIT-002, PSoC® MiniProg3 Program and Debug Kit
■Test and Debug Tools:
❐CYSmart, Bluetooth® LE Test and Debug Tool (Windows)
❐CYSmart Mobile, Bluetooth® LE Test and Debug Tool
(Android/iOS Mobile App)
Two Easy-To-Use Design Environments to Get You Started Quickly
PSoC® Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 Bluetooth LE, and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Bluetooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design Bluetooth LE applications. The Component incorporates a Bluetooth Core Specification v5.1 compliant Bluetooth LE
protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy
Sub-System (BLESS) hardware via the stack.
EZ-Serial™ BLE Firmware Platform
The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed
in Bluetooth LE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and
control signals through the module’s GPIOs, making it easy to add Bluetooth LE functionality quickly to existing designs.
Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for
User Manuals and instructions for getting started as well as detailed reference materials.
EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you
can download each EZ-BLE module’s firmware images on the EZ-Serial webpage.

CYBLE-022001-00
Document Number: 001-95662 Rev. *N Page 3 of 41
Technical Support
■Frequently Asked Questions (FAQs): Learn more about our Bluetooth LE ECO System.
■Forum: See if your question is already answered by fellow developers on the PSoC 4 Bluetooth LE forum.
■Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: [phone]. Select option 2 at the prompt.

CYBLE-022001-00
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Contents
Overview ............................................................................ 5
Module Description ......................................................5
Pad Connection Interface ................................................ 7
Recommended Host PCB Layout ...................................8
Digital and Analog Capabilities and Connections ....... 10
Power Supply Connections
and Recommended External Components ..................11
Power Connections ...................................................11
Connection Options ...................................................11
External Component Recommendation ....................11
Critical Components List ...........................................13
Antenna Design .........................................................13
Electrical Specification .................................................. 14
GPIO .........................................................................16
XRES .........................................................................18
Digital Peripherals .....................................................20
Serial Communication ...............................................22
Memory .....................................................................23
System Resources ....................................................23
Environmental Specifications ....................................... 28
Environmental Compliance .......................................28
RF Certification ..........................................................28
Safety Certification ....................................................28
Environmental Conditions ......................................... 28
ESD and EMI Protection ........................................... 28
Regulatory Information .................................................. 29
FCC ........................................................................... 29
ISED .......................................................................... 30
European R&TTE Declaration of Conformity ............30
MIC Japan ................................................................. 31
KC Korea ................................................................... 31
Anatel Brazil ..............................................................32
Packaging ........................................................................ 33
Ordering Information ...................................................... 35
Part Numbering Convention ......................................35
Acronyms ........................................................................ 36
Document Conventions ................................................. 36
Units of Measure ....................................................... 36
Document History Page ................................................. 37
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41

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Overview
Module Description
The CYBLE-022001-00 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate Bluetooth LE device) from various vendors to achieve the
Bluetooth LE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained.
Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters
(mm).
Table 1. Module Design Dimensions
See Figure 1 on page 6 for the mechanical reference drawing for CYBLE-022001-00.
Dimension Item Specification
Module dimensions Length (X) 10.00 ± 0.15 mm
Width (Y) 10.00 ± 0.15 mm
Antenna location dimensions Length (X) 7.00 ± 0.15 mm
Width (Y) 5.00 ± 0.15 mm
PCB thickness Height (H) 0.50 ± 0.10 mm
Shield height Height (H) 1.10 ± 0.10 mm
Maximum component height Height (H) 1.30-mm typical (chip antenna)
Total module thickness (bottom of module to highest component) Height (H) 1.80-mm typical

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Figure 1. Module Mechanical Drawing
Bottom View (Seen from Bottom)
Side View
Top View (See from Top)
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 8.

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Pad Connection Interface
As shown in the bottom view of Figure 1 on page 6, the CYBLE-022001-00 connects to the host board via solder pads on the back
of the module. Tab le 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-022001-00 module.
Figure 2. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress Bluetooth LE module is in a corner of the host board with the chip antenna located at the far
corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress Bluetooth LE module chip antenna should contain an
additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layers of the host
board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-022001-00 Chip Antenna
Table 2. Solder Pad Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 21 Solder Pads 0.71 mm 0.41 mm 0.76 mm
Host PCB Keep Out Area Around Chip Antenna

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Recommended Host PCB Layout
Figure 4, Figure 5, Figure 6, and Tab le 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-022001-00. Dimensions are in millimeters unless otherwise noted. Pad length of 0.91 mm (0.455 mm from center of the pad
on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-022001-00 Figure 5. Module Pad Location from Origin
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)

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Table 3 provides the center location for each solder pad on the CYBLE-022001-00. All dimensions are referenced to the center of the
solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
1 (0.26, 1.64) (10.24, 64.57)
2 (0.26, 2.41) (10.24, 94.88)
3 (0.26, 3.17) (10.24, 124.80)
4 (0.26, 3.93) (10.24, 154.72)
5 (0.26, 4.69) (10.24, 184.65)
6 (0.81, 9.74) (31.89, 383.46)
7 (1.57, 9.74) (61.81, 383.46)
8 (2.34, 9.74) (92.13, 383.46)
9 (3.10, 9.74) (122.05, 383.46)
10 (3.86, 9.74) (151.97, 383.46)
11 (4.62, 9.74) (181.89, 383.46)
12 (5.38, 9.74) (211.81, 383.46)
13 (6.15, 9.74) (242.13, 383.46)
14 (6.91, 9.74) (272.05, 383.46)
15 (7.67, 9.74) (301.97, 383.46)
16 (8.43, 9.74) (331.89, 383.46)
17 (9.19, 9.74) (361.81, 383.46)
18 (9.75, 8.50) (383.86, 334.65)
19 (9.75, 7.74) (383.86, 304.72)
20 (9.75, 6.98) (383.86, 274.80)
21 (9.75, 6.22) (383.86, 244.88)
Top View (Seen on Host PCB)

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Digital and Analog Capabilities and Connections
Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on
CYBLE-022001-00, the Bluetooth LE device port-pin, and denotes whether the function shown is available for each solder pad. Each
connection is configurable for a single option shown with a ✓.
Table 4. Solder Pad Connection Definitions
Solder Pad
Number
Device
Port Pin UART SPI I2CTCPWM[2,3] Cap- Sense
WCO
Out
ECO
Out LCD SWD GPIO
1GND
[4] Ground Connection
2P4.1
[5] ✓(SCB1_CTS) ✓(SCB1_MISO) ✓(TCPWM0_N) ✓(Sensor/
CTANK)✓✓
3P5.1✓(SCB1_TX) ✓(SCB1_SCLK) ✓(SCB1_SCL) ✓(TCPWM3_N) ✓(Sensor) ✓✓ ✓
4P5.0✓(SCB1_RX) ✓(SCB1_SS0) ✓(SCB1_SDA) ✓(TCPWM3_P) ✓(Sensor) ✓✓
5V
DDR Radio Power Supply (1.9V to 5.5V)
6P1.6✓(SCB0_RTS)✓(SCB0_SS0) ✓(TCPWM) ✓(Sensor) ✓✓
7P0.7✓(SCB0_CTS) ✓(SCB0_SCLK) ✓(TCPWM) ✓(Sensor) ✓✓
(SWDCLK) ✓
8P0.4✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM) ✓(Sensor) ✓✓ ✓
9P0.5✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL) ✓(TCPWM) ✓(Sensor) ✓✓
10 GND Ground Connection
11 P0.6 ✓(SCB0_RTS) ✓(SCB0_SS0) ✓(TCPWM) ✓(Sensor) ✓✓
(SWDIO) ✓
12 P1.7 ✓(SCB0_CTS) ✓(SCB0_SCLK) ✓(TCPWM) ✓(Sensor) ✓✓
13 VDD Digital Power Supply Input (1.71 to 5.5V)
14 XRES External Reset Hardware Connection Input
15 P3.5 ✓(SCB1_TX) ✓(SCB1_SCL) ✓(TCPWM) ✓(Sensor) ✓✓
16 P3.4 ✓(SCB1_RX) ✓(SCB1_SDA) ✓(TCPWM) ✓(Sensor) ✓✓
17 P3.7 ✓(SCB1_CTS) ✓(TCPWM) ✓(Sensor) ✓✓ ✓
18 P1.4 ✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM) ✓(Sensor) ✓✓
19 P1.5 ✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL) ✓(TCPWM) ✓(Sensor) ✓✓
20 P3.6 ✓(SCB1_RTS) ✓(TCPWM) ✓(Sensor) ✓✓
21 P4.0[6] ✓(SCB1_RTS) ✓(SCB1_MOSI) ✓(TCPWM0_P) ✓(CMOD)✓✓
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive
or negative polarity. TCPWM connections on ports 4 and 5 are direct and can only be used with the specified TCPWM block and polarity specified above.
4. The main board needs to connect both GND connections (Pad 1 and Pad 10) on the module to the common ground of the system.
5. When using the capacitive sensing functionality, Pad 2 (P4.1) can be connected to a CTANK capacitor (located off of Cypress Bluetooth LE Module). CTank should
be used if implementing a shield layer on the capacitive sensor. If used, this capacitor should be placed as close to the module as possible.
6. When using the capacitive sensing functionality, Pad 21 (P4.0) must be connected to a CMOD capacitor (located off of Cypress Bluetooth LE Module). The value
of this capacitor is 2.2 nF and should be placed as close to the module as possible.
7. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator

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Power Supply Connections and Recommended External Components
Power Connections
The CYBLE-022001-00 contains two power supply connections,
VDD and VDDR. The VDD connection supplies power for both
digital and analog device operation. The VDDR connection
supplies power for the device radio.
VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts
a supply range of 1.9 V to 5.5 V. These specifications can be
found in Table 9. The maximum power supply ripple for both
power connections on the module is 100 mV, as shown in
Table 7.
The power supply ramp rate of VDD must be equal to or greater
than that of VDDR.
Connection Options
Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply.
2. Independent supply: Power VDD and VDDR separately.
External Component Recommendation
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-022001-00.
Figure 8 details the recommended host schematic for an
independent supply scenario.
The recommended ferrite bead value is 330 , 100 MHz (Murata
BLM21PG331SN1D).
Figure 7. Recommended Host Schematic Options for a Single Supply Option
Figure 8. Recommended Host Schematic for an Independent Supply Option
Single Ferrite Bead Option (Seen from Bottom) Two Ferrite Bead Option (Seen from Bottom)
Independent Power Supply Option (Seen from Bottom)

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The CYBLE-022001-00 schematic is shown in Figure 9.
Figure 9. CYBLE-022001-00 Schematic Diagram

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Critical Components List
Table 5 details the critical components used in the CYBLE-022001-00 module.
Table 5. Critical Component List
Antenna Design
Table 6 details the chip antenna used in the CYBLE-022001-00 module. The specifications listed are according to the vendor’s
datasheet. The Cypress module performance improves many of these characteristics. For more information, see Table 8.
Table 6. Chip Antenna Specifications
Component Reference Designator Description
Silicon U1 68-pin WLCSP PSoC 4 Bluetooth LE
Crystal Y1 24.000 MHz, 10PF
Crystal Y2 32.768 kHz, 12.5PF
Antenna E1 2.4–2.5 GHz chip antenna
Item Description
Chip Antenna Manufacturer Johanson Technology Inc.
Chip Antenna Part Number 2450AT18B100
Frequency Range 2400–2500 MHz
Peak Gain 0.5-dBi typical
Average Gain –0.5-dBi typical
Return Loss 9.5-dB minimum

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Electrical Specification
Table 7 details the absolute maximum electrical characteristics for the Cypress Bluetooth LE module.
Table 7. CYBLE-022001-00 Absolute Maximum Ratings
Table 8 details the RF characteristics for the Cypress Bluetooth LE module.
Table 8. CYBLE-022001-00 RF Performance Characteristics
Table 9 through Ta ble 48 list the module-level electrical characteristics for the CYBLE-022001-00. All specifications are valid for –
40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Parameter Description Min Typ Max Units Details/Conditions
VDDD_ABS Analog, digital, or radio supply relative to VSS
(VSSD = VSSA)–0.5 – 6 VAbsolute maximum
VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 Absolute maximum
VDDD_RIPPLE Maximum power supply ripple for VDD and VDDR
input voltage – – 100 mV
3.0-V supply
Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximum
IGPIO_ABS Maximum current per GPIO –25 – 25
mA
Absolute maximum
IGPIO_injection GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS –0.5 – 0.5 Absolute maximum current
injected per pin
LU Pin current for latch up –200 200 –
Parameter Description Min Typ Max Units Details/Conditions
RFO RF output power on ANT –18 0 3
dBm
Configurable via register
settings
RXSRF receive sensitivity on ANT – –87 – Guaranteed by design
simulation
FRModule frequency range 2400 – 2480 MHz –
GPPeak gain – 0.5 – dBi –
GAvg Average gain – –0.5 – –
RL Return loss – –10.5 – dB –
Table 9. CYBLE-022001-00 DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VDD1 Power supply input voltage 1.8 – 5.5
V
With regulator enabled
VDD2 Power supply input voltage unregulated 1.71 1.8 1.89 Internally unregulated
supply
VDDR1 Radio supply voltage (radio on) 1.9 – 5.5 –
VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 –
Active Mode, VDD = 1.71 V to 5.5 V
IDD3 Execute from flash; CPU at 3 MHz – 1.7 –
mA
T = 25 °C,
VDD = 3.3 V
IDD4 Execute from flash; CPU at 3 MHz – – – T = –40 °C to 85 °C
IDD5 Execute from flash; CPU at 6 MHz – 2.5 – T = 25 °C,
VDD = 3.3 V
IDD6 Execute from flash; CPU at 6 MHz – – – T = –40 °C to 85 °C
IDD7 Execute from flash; CPU at 12 MHz – 4 – T = 25 °C,
VDD = 3.3 V

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IDD8 Execute from flash; CPU at 12 MHz – – –
mA
T = –40 °C to 85 °C
IDD9 Execute from flash; CPU at 24 MHz – 7.1 – T = 25 °C,
VDD = 3.3 V
IDD10 Execute from flash; CPU at 24 MHz – – – T = –40 °C to 85 °C
IDD11 Execute from flash; CPU at 48 MHz – 13.4 – T = 25 °C,
VDD = 3.3 V
IDD12 Execute from flash; CPU at 48 MHz – – – T = –40 °C to 85 °C
Sleep Mode, VDD = 1.8 V to 5.5 V
IDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V
IDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
Deep-Sleep Mode, VDD = 1.8 V to 3.6 V
IDD15 WDT with WCO on – 1.5 –
µA
T = 25 °C,
VDD = 3.3 V
IDD16 WDT with WCO on – – – T = –40 °C to 85 °C
IDD17 WDT with WCO on – – – T = 25 °C,
VDD = 5 V
IDD18 WDT with WCO on – – – T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed)
IDD19 WDT with WCO on – – – µA T = 25 °C
IDD20 WDT with WCO on – – – T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 V to 3.6 V
IDD27 GPIO and reset active – 150 – nA
T = 25 °C,
VDD = 3.3 V
IDD28 GPIO and reset active – – – T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 V to 5.5 V
IDD29 GPIO and reset active – – – nA
T = 25 °C,
VDD = 5 V
IDD30 GPIO and reset active – – – T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 V to 3.6 V
IDD33 Stop-mode current (VDD)–20–
nA
T = 25 °C,
VDD = 3.3 V
IDD34 Stop-mode current (VDDR)–40–-
T = 25 °C,
VDDR = 3.3 V
IDD35 Stop-mode current (VDD) – – – T = –40 °C to 85 °C
IDD36 Stop-mode current (VDDR)–––
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 V to 5.5 V
IDD37 Stop-mode current (VDD)–––
nA
T = 25 °C,
VDD = 5 V
IDD38 Stop-mode current (VDDR)–––
T = 25 °C,
VDDR = 5 V
IDD39 Stop-mode current (VDD) – – – T = –40 °C to 85 °C
IDD40 Stop-mode current (VDDR) – – – T = –40 °C to 85 °C
Table 9. CYBLE-022001-00 DC Specifications (continued)
Parameter Description Min Typ Max Units Details/Conditions

CYBLE-022001-00
Document Number: 001-95662 Rev. *N Page 16 of 41
GPIO
Table 10. AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
FCPU CPU frequency DC –48 MHz 1.71 V VDD 5.5 V
TSLEEP Wakeup from Sleep mode – 0 –
µs
Guaranteed by characterization
TDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 24-MHz IMO. Guaranteed by
characterization
THIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization
TSTOP Wakeup from Stop mode – – 2 XRES wakeup
Table 11. GPIO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VIH[8]
Input voltage HIGH threshold 0.7 × VDD – –
V
CMOS input
LVTTL input, VDD < 2.7 V 0.7 × VDD – – –
LVTTL input, VDD ≥ 2.7 V 2.0 – – –
VIL
Input voltage LOW threshold – – 0.3 × VDD CMOS input
LVTTL input, VDD < 2.7 V – – 0.3× VDD –
LVTTL input, VDD ≥ 2.7 V – – 0.8 –
VOH
Output voltage HIGH level VDD –0.6 – – IOH = 4 mA at 3.3-V VDD
Output voltage HIGH level VDD –0.5 – – IOH = 1 mA at 1.8-V VDD
VOL
Output voltage LOW level – – 0.6 IOL = 8 mA at 3.3-V VDD
Output voltage LOW level – – 0.6 IOL = 4 mA at 1.8-V VDD
Output voltage LOW level – – 0.4 IOL = 3 mA at 3.3-V VDD
RPULLUP Pull-up resistor 3.5 5.6 8.5 k–
RPULLDOWN Pull-down resistor 3.5 5.6 8.5 –
IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V
IIL_CTBM Input leakage on CTBm input pins – – 4 –
CIN Input capacitance – – 7 pF –
VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V
VHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –
IDIODE Current through protection diode to
VDD/VSS – – 100 µA –
ITOT_GPIO Maximum total source or sink chip
current – – 200 mA –
Note
8. VIH must not exceed VDD + 0.2 V.

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Table 12. GPIO AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TRISEF Rise time in Fast-Strong mode 2 – 12
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLF Fall time in Fast-Strong mode 2 – 12 3.3-V VDDD, CLOAD = 25 pF
TRISES Rise time in Slow-Strong mode 10 –60 3.3-V VDDD, CLOAD = 25 pF
TFALLS Fall time in Slow-Strong mode 10 –60 3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1 GPIO Fout; 3.3 V  VDD 5.5 V
Fast-Strong mode – – 33
MHz
90/10%, 25-pF load, 60/40 duty
cycle
FGPIOUT2 GPIO Fout; 1.7 VVDD 3.3 V
Fast-Strong mode – – 16.7 90/10%, 25-pF load, 60/40 duty cycle
FGPIOUT3 GPIO Fout; 3.3 V VDD 5.5 V
Slow-Strong mode – – 7 90/10%, 25-pF load, 60/40 duty cycle
FGPIOUT4 GPIO Fout; 1.7 V VDD 3.3 V
Slow-Strong mode – – 3.5 90/10%, 25-pF load, 60/40 duty cycle
FGPIOIN GPIO input operating frequency
1.71 V VDD 5.5 V – – 48 90/10% VIO
Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Parameter Description Min Typ Max Units Details/Conditions
IIL Input leakage (absolute value).
VIH > VDD – – 10 µA 25°C, VDD = 0 V, VIH = 3.0 V
VOL Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V
Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Parameter Description Min Typ Max Units Details/Conditions
TRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12
ns
25-pF load, 10%–90%, VDD=3.3 V
TFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 25-pF load, 10%–90%, VDD=3.3 V
TRISESS Output rise time in Slow-Strong mode 10 – 60 25-pF load, 10%-90%,
VDD = 3.3 V
TFALLSS Output fall time in Slow-Strong mode 10 – 60 25-pF load, 10%-90%,
VDD = 3.3 V
FGPIOUT1 GPIO FOUT; 3.3 V VDD 5.5 V
Fast-Strong mode ––24
MHz
90/10%, 25-pF load, 60/40 duty
cycle
FGPIOUT2 GPIO FOUT; 1.71 V VDD 3.3 V
Fast-Strong mode ––16 90/10%, 25-pF load, 60/40 duty
cycle

CYBLE-022001-00
Document Number: 001-95662 Rev. *N Page 18 of 41
XRES
Temperature Sensor
SAR ADC
Table 15. XRES DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VIH Input voltage HIGH threshold 0.7 × VDDD ––V CMOS input
VIL Input voltage LOW threshold – – 0.3 × VDDD
RPULLUP Pull-up resistor 3.5 5.6 8.5 k–
CIN Input capacitance – 3 – pF –
VHYSXRES Input voltage hysteresis – 100 – mV –
IDIODE Current through protection diode to
VDD/VSS – – 100 µA –
Table 16. XRES AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TRESETWIDTH Reset pulse width 1 – – µs –
Table 17. Temperature Sensor Specifications
Parameter Description Min Typ Max Units Details/Conditions
TSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °C
Table 18. SAR ADC DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
A_RES Resolution – – 12 bits –
A_CHNIS_S Number of channels - single-ended – – 6 6 full-speed[9]
A-CHNKS_D Number of channels - differential – – 3 Diff inputs use neighboring I/O[9]
A-MONO Monotonicity – – – Yes
A_GAINERR Gain error – – ±0.1 % With external reference
A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREF
A_ISAR Current consumption – – 1 mA –
A_VINS Input voltage range - single-ended VSS –V
DDA V–
A_VIND Input voltage range - differential VSS – VDDA –
A_INRES Input resistance – – 2.2 k–
A_INCAP Input capacitance – – 10 pF –
VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg (1.024 V)
Note
9. A maximum of six single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If the
AMUX Buses are being used for other functionality, then the maximum number of single-ended ADC channels is four. Similarly, if the AMUX Buses are being
used for other functionality, then the maximum number of differential ADC channels is two.

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Document Number: 001-95662 Rev. *N Page 19 of 41
CSD
Table 19. SAR ADC AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
A_PSRR Power-supply rejection ratio 70 – – dB
Measured at 1-V
reference
A_CMRR Common-mode rejection ratio 66 – – –
A_SAMP Sample rate – – 1 Msps 806 Ksps for More Part
Numbers devices
Fsarintref SAR operating speed without external ref.
bypass – – 100 Ksps 12-bit resolution
A_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHz
A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz –
A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps –1.7 – 2
LSB
VREF = 1 V to VDD
A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps –1.5 – 1.7 VREF = 1.71 V to VDD
A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 Ksps –1.5 – 1.7 VREF = 1 V to VDD
A_dnl Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps –1 – 2.2 VREF = 1 V to VDD
A_DNL Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps –1 – 2 VREF = 1.71 V to VDD
A_DNL Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 Ksps –1 – 2.2 VREF = 1 V to VDD
A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz
CSD Block Specifications
Parameter Description Min Typ Max Units Details/Conditions
VCSD Voltage range of operation 1.71 – 5.5 V –
IDAC1 DNL for 8-bit resolution –1 – 1
LSB
–
IDAC1 INL for 8-bit resolution –3 – 3 –
IDAC2 DNL for 7-bit resolution –1 – 1 –
IDAC2 INL for 7-bit resolution –3 – 3 –
SNR Ratio of counts of finger to noise 5 – – Ratio
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
IDAC1_CRT1 Output current of IDAC1 (8 bits) in High
range –612 –
µA
–
IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low
range –306 – –
IDAC2_CRT1 Output current of IDAC2 (7 bits) in High
range –305 – –
IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low
range –153 – –