Infineon REF MA5332BTLSPS User manual

User Manual V 1.0
www.infineon.com page 1 of 24 2020-07-07
UM_2102_PL88_2013_192558
REF_MA5332BTLSPS
MA5332M reference board
About this document
Scope and purpose
The REF_MA5332BTLSPS reference board is a one BTL channel, 200 W/ch (4 Ω at 40 V) class D audio power
amplifier for home audio systems. This reference board demonstrates how to use MA5332MS IC with a single
power supply and design an optimum PCB layout using Infineon integrated Class D IC. This reference design
does not require additional heatsink or fan cooling for normal operation (one-eighth of continuous rated
power). The reference design provides all the required housekeeping power supplies for ease of use.
Applications
 Smart speakers
 Sound bars
 Sub-woofers
 Powered speakers
 Musical instrument amplifiers
 Car audio amplifiers
Features
 Output power:
− 200 W x 1 channels (10 percent THD+N, 4 Ω at 40 V)
 Multiple protection features:
− Over-Current Protection (OCP), high-side and low-side
− Over-Temperature Protection (OTP)
 PWM modulator:
− Self-oscillating half-bridge topology with optional clock synchronization

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Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 2
1 Specifications ........................................................................................................................ 3
2 REF_MA5332BTLSPS overview ................................................................................................. 4
3 Set-up guide .......................................................................................................................... 5
4 Audio analyzer set-up ............................................................................................................. 6
5 Operating the evaluation board ............................................................................................... 7
5.1 Test set-up ............................................................................................................................................... 7
5.2 Power-up sequence................................................................................................................................. 7
5.3 Audio functionality tests ......................................................................................................................... 7
5.4 Power-down sequence ........................................................................................................................... 7
6 Audio performance ................................................................................................................. 8
6.1 Power vs. THD+N ..................................................................................................................................... 8
6.2 Frequency response ................................................................................................................................ 8
6.3 Noise floor................................................................................................................................................ 9
6.4 Noise floor with 1 VRMS output ................................................................................................................. 9
7 Efficiency ............................................................................................................................. 10
8 Thermal information ............................................................................................................. 11
8.1 Thermal performance ........................................................................................................................... 11
8.2 Heatsink ................................................................................................................................................. 12
9 Gain setting .......................................................................................................................... 13
9.1 Gain design flow .................................................................................................................................... 13
9.2 Vbus Calculation .................................................................................................................................... 14
9.3 AC gain setting: ...................................................................................................................................... 14
9.4 DC gain setting: ...................................................................................................................................... 15
10 Schematic ............................................................................................................................ 16
11 PCB ...................................................................................................................................... 17
11.1 PCB specification ................................................................................................................................... 17
11.2 PCB layout ............................................................................................................................................. 18
12 Bill of Materials (BOM) ........................................................................................................... 20
Revision history............................................................................................................................. 23

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1 Specifications
Table 1 General test conditions
Condition Notes/conditions
Supply voltages +40 V Unipolar power supply
Rated load impedance 4 Ω Resistive load
Self-oscillating frequency 400 kHz No input signal, adjustable
Voltage gain 23 dB 1Vrms input yields rated power
Table 2 Electrical data
Data Typical Notes/conditions
Infineon devices
MA5332
MS
i
ntegrated c
lass D IC
Modulator Self-oscillating, second-order sigma-delta modulation, analog input
Output power: (1 percent THD+N) 150 W 1 kHz, RL = 4 Ω
Output power: (10 percent THD+N) 200 W 1 kHz, RL = 4 Ω
Rated load impedance 4 Ω Resistive load
Idling supply current +75 mA No input signal, +40 V
Signal-to-noise Ratio(SNR) 96dB
Filter: A
-
weighting(12017), 20 kHz
SPCL
Gain setting:23dB
Residual noise 140 uV
Filter: A
-
weighting(12017), 20 kHz
SPCL
Gain setting:23dB
Channel efficiency 90 percent
Single
-
channel driven,
200 W, class D stage

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2 REF_MA5332BTLSPS overview
The REF_MA5332BTLSPS features a one BTL channel self-oscillating type PWM modulator for the lowest
component count, convenient single power supply and highest performance and robust design. This topology
represents an analog version of a second-order sigma-delta modulation, with the class D switching stage inside
the loop. The benefit of the sigma-delta modulation, in comparison to the carrier-signal based modulation, is
that all the error in the audible frequency range is shifted to the inaudible upper-frequency range by nature of
its operation. Also, sigma-delta modulation enables the designer to apply sufficient error correction.
The REF_MA5332BTLSPS self-oscillating topology consists of the following essential functional blocks:
 Front-end integrator
 PWM comparator
 Level shifters
 Integrated gate drivers and MOSFETs
 Output LPF
Figure 1 Simplified block diagram of class D amplifier

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3 Set-up guide
Typical connections
Figure 2 Typical connection connector description
Table 3 Connector description
ANALOG INPUT J3 Analog balanced input
OUTPUT J1 Analog output
POWER J8 Single power supply
J1
Power
Input
Output
Input
4 Ohm
40V, 7
A DC supply
250W, Non-inductive Resistors
J8
MA5332MS
J3
G
S1
Audio Signal Generator

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4 Audio analyzer set-up
Figure 3 Audio analyzer connection

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5 Operating the evaluation board
5.1 Test set-up
1. Connect 4 Ω 250 W dummy loads to output connector (J1 as shown in Figure 2) and parallel it with the input
of the Audio Precision (AP) analyzer.
2. Connect the Audio Signal Generator (ASG) to J3 for analog signal respectively (AP).
3. Set up the power supply with voltages of 40 V; set the current limit to 7 A.
4. Turn off the power supply before connecting to “on” of the Unit Under Test (UUT).
5. Connect the power supply to J8, as shown in Figure 2
5.2 Power-up sequence
6. Turn on the power supply.
7. Quiescent current for the supply should be 75 mA 10 mA at 40 V.
8. Turn on the switch S1(middle position)
5.3 Audio functionality tests
8. Set the AP’s analog analyzer to 20 kHz AES17 filter.
9. Connect the audio signal from the AP to J3.
10. Sweep the audio signal voltage from 15 mVRMS to 1.5 VRMS.
11. Run the AP test as shown in Figures 4 to 11, below.
5.4 Power-down sequence
13. Turn off the switch S1(side position)
14. Turn off power supply
15. All LEDs turn off when housekeeping power supplies are off.

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6 Audio performance
6.1 Power vs. THD+N
Test conditions:
Vbus = 40 V
Input signal = 1 kHz
Load impedance = 4 Ω
FPWM = 400 kHz
Figure 4 Power vs. THD+N 4 Ω load
6.2 Frequency response
Test conditions:
Vbus = 40 V
Output power = 1 W
Load impedance = 4 Ω
FPWM = 400 kHz
Figure 5 Frequency response 4 Ω load
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 500200m 500m 1 2 5 10 20 50 100 200
W
-10
+4
-9
-8
-7
-6
-5
-4
-3
-2
-1
-0
+1
+2
+3
d
B
r
A
20 200k50 100 200 500 1k 2k 5k 10k 20k 50k 100k
Hz

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6.3 Noise floor
Test conditions:
Vbus = 40 V
No input signal
Load impedance = 4 Ω
FPWM = 400 kHz
Figure 6 Noise floor 4 Ω load
6.4 Noise floor with 1 VRMS output
Test conditions:
Vbus = 40 V
Output = 1 VRMS at 1 kHz
Load impedance = 4 Ω
FPWM = 400 kHz
Figure 7 Noise floor with 1 VRMS output 4 Ω load
-150
+20
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
+10
d
B
V
10 20k20 50 100 200 500 1k 2k 5k 10k
Hz
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
V
20 20k50 100 200 500 1k 2k 5k 10k
Hz

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7 Efficiency
Test conditions:
Vbus = 40 V
Output = 1 VRMS at 1 kHz
Load impedance = 4 Ω
FPWM = 400 kHz
Figure 8 REF_MA5332BTLSPS 4 Ω load stereo, Vbus= 40 V
0.0%
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
90.0%
100.0%
0 50 100 150 200 250
Efficiency
Power (W)
MA5332BTLSPS 4ohm
MA5332BTLSPS 4ohm

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8 Thermal information
Test conditions:
Vbus = 40V
Input signal = 1 kHz
Both channels driven
FPWM = 400 kHz
Load = 4 Ω
8.1 Thermal performance
Table 4 Thermal performance (with heatsink)
Output Power(W) Tc(°C) Record time
18.75 71.4 30(minutes)
200 109 1(minute)
200 144 5(minutes)
Figure 9 1/8Po power Pout = 18.75 W with 4 Ω load 40 V with heatsink
Note: Temperature saturated at 71.4°C after 30 minutes,

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Figure 10 Peak power Pout = 200 W with 4 Ω load 40 V with heatsink
Note: Maximum temperature 109.2°C at 1 minute and 144°C at 5 minutes.
8.2 Heatsink
Figure 11 Heatsink dimension

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9 Gain setting
REF_MA5332BTLSPS reference board has two gain settings for the single power supply application, which is
different from split power supplies application. The AC gain setting (red path in Figure 12) is the same as the
normal gain setting, the ratio of RFB and Rin is the AC gain. The DC gain setting (blue path in Figure 12) depends
on the desired bus voltage & rated output power.
Speaker
EXT CLK
(OPTIONAL)
10V
VAA
IN-2
COMP2
CSD
FAULT
COM
VN2
VS2
VCC
VS1
VN1
CSH1 VB1 VS1 VP1
CSH2
VB2
VS2
VP2
COM
CLIP
IN+2
COMP1
IN-1
IN+1
VSS
GND
+B
CH2 INPUT
CH1 INPUT 10V
AC
DC
AC
DC
0V
R
ACin
R
ACin
R
DCin
R
DCin
R
FB(Class D Stage)
R
FB(Clas s D Stage)
Figure 12 AC and DC path
9.1 Gain design flow
The gain design can follow Figure 13’s gain design flow.
Figure 13 Gain design flow
1, Set target rated power and load impedance
2, Calculate Vbus based on rated power and load impedance.
3, Calculate required AC gain & RACin.
4, Calculate RDCin.
V
ref

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9.2 Vbus Calculation
Vbus is calculated by the load impedance and clipping power(normally 75% of RMS power)
Vbus=(2*Pclipping *Rload)^(1/2)/M
M is maximum modulation index, normally M=90%
Vbus=(2*200*75%*4)^(1/2)*90%
=38.5V
Use 40V as Vbus in this design.
9.3 AC gain setting:
AC gain is the mean ratio of the signal amplitude at the output to the amplitude at the input.
In REF_MA5332BTLSPS design, assume the maximum input signal is up to 5Vp-p balanced input.
Set the gain when input is 5Vp-p and the clipping voltage is 74Vp-p(93% of Vbus*2=40*2V for BTL).
Desire total voltage gain=74/5=14.8.
Total Voltage Gain=Gain(OPAMP stage)*Gain(Class D stage)
Set OPAMP gain to be maximum to have the get minimum noise floor. Set the OPAMP gain based on the supply
of the OPAMP, which is 10V in this design. The maximum output of the OPAMP is 9.9V, which is decided by the
parameter of the OPAMP.
So the maximum OPAMP’s voltage gain is 9.9/(1.414*2)=3.5.
Gain(Class D stage)= Total Voltage Gain/ Gain(OPAMP stage)
=14.8/3.5
=4.3
In the current design preset below values:
RFB(OPAMP stage) =R30=34.8kohm
Rin(OPAMP stage) =R15=10kohm
RFB(Class D stage) =R135=47.5kohm(recommend fix the value as 47.5kohm)
Rin(Class D stage) =R31+R3=(3.3+8.2)kohm
Total Voltage Gain=Gain(OPAMP stage)*Gain(Class D stage)
=[RFB(OPAMP stage) /Rin(OPAMP stage)]* [RFB(Class D stage) /Rin(Class D stage)]
= (R30 /R15)*(R13/(R31+R3))
= (34.8 /10)*(47.5/(3.3+8.2))
=3.48*4.13
=14.37(close to 14.8)
Gain(dB)=20*log(14.37)=23.15dB

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9.4 DC gain setting:
DC gain is to set the output DC operation point at half of the Vbus.
Output DC operation point= ½ *Vbus=Vref*DC gain
Vref=½* of VAA
DC gain= ½* Vbus/Vref
= (RFB(Class D stage) + RDCin )/ RDCin
With RFB(Class D stage)=47.5kohm
RFB(Class D stage) / RDCin=(½* Vbus /2- Vref)/ Vref
 RDCin= RFB(Class D stage) * Vref /(½* Vbus - Vref)
R7==R8= R30*5/(Vbus/2-5)=47.5*5/(40/2-5)=15.8kohm

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10 Schematic
Figure 14 Schematic

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11 PCB
11.1 PCB specification
1. Two-layer SMT PCB with through-holes
2. 1/16 thickness
3. 2/0 oz. Cu
4. FR4 material
5. 10 mil lines and spaces
6. Solder mask to be green enamel EMP110 DBG (CARAPACE) or Enthone endplate DSR-3241 or equivalent
7. Silkscreen to be white epoxy non-conductive per IPC–RB 276 standard
8. All exposed copper must be finished with tin-lead Sn 60 or 63 for 100 µ inches thick
9. Tolerance of PCB size shall be 0.010 to 0.000 inches
10. Tolerance of all holes is +/- 0.003 inches
11. PCB acceptance criteria as defined for class II PCB standards

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11.2 PCB layout
Figure 15 Board top view

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Figure 16 Board bottom view

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12 Bill of Materials (BOM)
Table 5 Board BOM
No. Part number Designator Description Quantity Vendor
1 565-1106-ND C1, C2,C11, C13
CAP ALUM 10UF 20% 50V
RADIAL 4 Digikey
2 490-1500-1-ND C3, C4, C6, C7
CAP CER 2200PF 50V 10%
X7R 0603 4 Digikey
3 587-2668-1-ND C5, C8
CAP CER 10UF 10V X7R
10% 0805 2 Digikey
4 399-1082-1-ND C9, C10
CAP 1000PF 50V
CERAMICX7R 0603 2 Digikey
5 490-5519-1-ND C12, C14
CAP CER 10UF 16V X6S
0805 2 Digikey
6 445-1418-1-ND C15, C16, C17
CAP CER .10UF 100V X7R
10% 0805 3 Digikey
7 445-1377-1-ND C18, C19, C20, C21
CAP CER .1UF 100V X7R
10% 1206 4 Digikey
8 495-4721-ND C24, C43
CAP FILM 1UF 10%
450VDC RADIAL 2 Digikey
9 1928-1956-1-ND C25
CAP FILM 0.1UF 20%
250VDC 2824 1 Digikey
10 URS2A331MHD C27, C34, C35, C36
CAP ALUM 330UF 20%
100V RADIAL 4 Digikey
11 490-1483-1-ND C28, C29
CAP CER 220PF 50V X7R
0603 2 Digikey
12 478-1429-1-ND C30
CAP CER 4.7UF 10V Y5V
0805 1 Digikey
13 445-1601-1-ND C31
CAP CER 10UF 16V X7R
1206 1 Digikey
14 565-1056-ND C37, C38
CAP ALUM 22UF 20% 25V
RADIAL, CAP 22UF 25V
ELECT VR RADIAL 2 Digikey
15 160-1183-1-ND CLIP1
LED GREEN CLEAR 0603
SMD 1 Digikey
16 RF071MM2SCT-ND D1, D2, D3, D4
DIODE SWITCH 100V
400MW SOD123 4 Digikey
17 MURA120T3GOSCT-ND D5, D6, D7, D8
DIODE GEN PURP 200V 2A
SMA 4 Digikey
18 MA5332MS IC1
2 CH Integrated Digital
Audio Amplifier 1 Infineon
19 296-2421-1-ND IC2
IC OPAMP GP 2 CIRCUIT
8SOIC 1 Digikey