Intel 815EG Guide

Intel®815EG Chipset Platform
For Use with Universal Socket 370
Design Guide
August 2002
Document Number: 298301-002
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
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and other countries.
*Other names and brands may be claimed as the property of others.
Copyright©2001-2002, Intel Corporation

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Contents
1Introduction ........................................................................................................................13
1.1 Design Guide and Chipset Basic Information .......................................................13
1.2 Terminology ..........................................................................................................14
1.3 Reference Documents ..........................................................................................16
1.4 System Overview ..................................................................................................17
1.4.1 System Features ...................................................................................18
1.4.2 Component Features.............................................................................19
1.4.2.1 Intel®82815EG GMCH Features .........................................19
1.4.2.2 Intel®815 to 815G/EG Signal Name Changes ....................20
1.4.2.3 Intel®82801BA I/O Controller Hub 2 (ICH2) ........................21
1.4.2.4 Firmware Hub (FWH)...........................................................21
1.4.3 Platform Initiatives .................................................................................21
1.4.3.1 Universal Motherboard Design ............................................21
1.4.3.2 Intel®PC 133........................................................................22
1.4.3.3 Accelerated Hub Architecture Interface ...............................22
1.4.3.4 Internet Streaming SIMD Extensions...................................22
1.4.3.5 Integrated LAN Controller ....................................................22
1.4.3.6 Ultra ATA/100 Support.........................................................22
1.4.3.7 Expanded USB Support .......................................................22
1.4.3.8 Manageability and Other Enhancements .............................23
1.4.3.9 AC ’97 6-Channel Support ...................................................23
1.4.3.10 Low-Pin-Count (LPC) Interface............................................26
2General Design Considerations.........................................................................................27
2.1 Nominal Board Stack-Up ......................................................................................27
2.2 Future Designs Require Pull-Ups and Pull-Downs on Any Unused Input and
I/O Pins .................................................................................................................28
2.3 Support For P-MOS Kicker “ON”: SMAA[9] Is Strapped High by an Internal
50 kΩPull-Up Resistor .........................................................................................28
2.4 Electrostatic Discharge Platform Recommendations ...........................................28
3Component Layouts...........................................................................................................31
4Universal Socket 370 Design ............................................................................................35
4.1 Universal Socket 370 Definitions ..........................................................................35
4.2 Processor Design Requirements ..........................................................................37
4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH............37
4.2.2 Identifying the Processor at the Socket.................................................38
4.2.3 Setting the Appropriate Processor VTT Level .......................................39
4.2.4 VTT Processor Pin AG1........................................................................40
4.2.5 Identifying the Processor at the GMCH.................................................41
4.2.6 Configuring Non-VTT Processor Pins ...................................................42
4.2.7 VCMOS Reference................................................................................43
4.2.8 Processor Signal PWRGOOD...............................................................44
4.2.9 APIC Clock Voltage Switching Requirements .......................................45
4.2.10 GTLREF Topology and Layout..............................................................46

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4.3 Power Sequencing on Wake Events ....................................................................47
4.3.1 Gating of Intel®CK-815 to VTTPWRGD ...............................................47
4.3.2 Gating of PWROK to Intel®ICH2 ..........................................................48
5System Bus Design Guidelines .........................................................................................49
5.1 System Bus Routing Guidelines ...........................................................................49
5.1.1 Initial Timing Analysis ............................................................................49
5.2 General Topology and Layout Guidelines.............................................................52
5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................53
5.2.1.1 Ground Reference ...............................................................53
5.2.1.2 Reference Plane Splits ........................................................53
5.2.1.3 Processor Connector Breakout............................................53
5.2.1.4 Minimizing Crosstalk ............................................................54
5.2.2 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals .....55
5.2.3 THRMDP and THRMDN .......................................................................56
5.2.4 Additional Routing and Placement Considerations ...............................56
5.3 Electrical Differences for Universal PGA370 Designs ..........................................57
5.3.1 THERMTRIP Circuit ..............................................................................57
5.3.1.1 THERMTRIP Timing ............................................................58
5.3.1.2 THERMTRIP Support for 0.13 Micron Technology
Processors, A-1 Stepping ....................................................58
5.4 PGA370 Socket Definition Details ........................................................................59
5.5 BSEL[1:0] Implementation Differences.................................................................62
5.6 CLKREF Circuit Implementation ...........................................................................63
5.7 Undershoot/Overshoot Requirements ..................................................................64
5.8 Processor Reset Requirements............................................................................65
5.9 Processor PLL Filter Recommendations ..............................................................66
5.9.1 Topology................................................................................................66
5.9.2 Filter Specification .................................................................................66
5.9.3 Recommendation for Intel®Platforms ...................................................68
5.9.4 Custom Solutions ..................................................................................70
5.10 Voltage Regulation Guidelines..............................................................................70
5.11 Decoupling Guidelines for Universal PGA370 Designs ........................................70
5.11.1 VCCCORE Decoupling Design .................................................................70
5.11.2 VTT Decoupling Design ........................................................................71
5.11.3 VREF Decoupling Design......................................................................71
5.12 Thermal Considerations........................................................................................72
5.12.1 Heatsink Volumetric Keep-Out Regions................................................72
5.12.2 Fan Heatsink Keep-Out Adherence for Future Boxed Intel®Celeron®
Processors ............................................................................................74
5.13 Debug Port Changes ............................................................................................75
6System Memory Design Guidelines...................................................................................77
6.1 System Memory Routing Guidelines.....................................................................77
6.2 System Memory 2-DIMM Design Guidelines ........................................................78
6.2.1 System Memory 2-DIMM Connectivity ..................................................78
6.2.2 System Memory 2-DIMM Layout Guidelines .........................................79
6.3 System Memory 3-DIMM Design Guidelines ........................................................81
6.3.1 System Memory 3-DIMM Connectivity ..................................................81
6.3.2 System Memory 3-DIMM Layout Guidelines .........................................82
6.4 System Memory Decoupling Guidelines ...............................................................83

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6.5 Compensation.......................................................................................................85
7Display Cache Design Guidelines .....................................................................................87
7.1 Display Cache Interface........................................................................................87
7.2 GPA Card Considerations.....................................................................................87
7.3 GPA Mechanical Considerations ..........................................................................87
7.4 Display Cache Clocking ........................................................................................88
7.5 VDDQ Generation.................................................................................................88
8Integrated Graphics Display Output...................................................................................89
8.1 Analog RGB/CRT..................................................................................................89
8.1.1 RAMDAC/Display Interface ...................................................................89
8.1.2 Reference Resistor (Rset) Calculation..................................................91
8.1.3 RAMDAC Board Design Guidelines ......................................................91
8.1.4 RAMDAC Layout Recommendations ....................................................93
8.1.5 HSYNC/VSYNC Output Guidelines.......................................................93
8.2 Intel®Digital Video Out..........................................................................................94
8.2.1 Intel®DVO Interface Routing Guidelines...............................................94
8.2.2 Intel®DVO I2C Interface Considerations ...............................................94
8.2.3 Leaving the Intel®DVO Port Unconnected............................................94
9Hub Interface .....................................................................................................................97
9.1.1 Data Signals ..........................................................................................98
9.1.2 Strobe Signals .......................................................................................98
9.1.3 HREF Generation/Distribution...............................................................98
9.1.4 Compensation .......................................................................................99
10 I/O Controller Hub 2 (Intel®ICH2)....................................................................................101
10.1 Decoupling ..........................................................................................................101
10.2 Power Sequencing on Wake Events ..................................................................102
10.3 Power Supply PS_ON Considerations................................................................103
11 I/O Subsystem .................................................................................................................105
11.1 IDE Interface .......................................................................................................105
11.1.1 Cabling ................................................................................................105
11.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 .........................................105
11.2.1 Combination Host-Side/Device-Side Cable Detection ........................106
11.2.2 Device-Side Cable Detection...............................................................107
11.2.3 Primary IDE Connector Requirements ................................................108
11.2.4 Secondary IDE Connector Requirements ...........................................109
11.3 AC ’97 .................................................................................................................110
11.3.1 Communications Network Riser (CNR)...............................................111
11.3.2 AC ’97 Audio Codec Detect Circuit and Configuration Options...........112
11.3.2.1 Valid Codec Configurations ...............................................115
11.3.3 SPKR Pin Considerations....................................................................115
11.3.4 AC ’97 Routing ....................................................................................116
11.3.5 Motherboard Implementation ..............................................................117
11.4 USB.....................................................................................................................118
11.4.1 Using Native USB Interface.................................................................118
11.4.2 Disabling the Native USB Interface of ICH2........................................119
11.5 I/O APIC Design Recommendation ....................................................................119
11.5.1 PIRQ Routing Example .......................................................................120

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11.6 SMBus/SMLink Interface ....................................................................................121
11.6.1 SMBus Architecture and Design Considerations ................................122
11.6.1.1 General Design Issues and Notes .....................................122
11.7 PCI ......................................................................................................................125
11.8 RTC.....................................................................................................................126
11.8.1 RTC Crystal.........................................................................................126
11.8.2 External Capacitors .............................................................................127
11.8.3 RTC Layout Considerations ................................................................127
11.8.4 RTC External Battery Connection .......................................................127
11.8.5 RTC External RTCRST Circuit............................................................129
11.8.6 Power-Well Isolation Control Requirements .......................................129
11.8.7 RTC Routing Guidelines......................................................................130
11.8.8 VBIAS DC Voltage and Noise Measurements ....................................131
11.9 LAN Layout Guidelines .......................................................................................131
11.9.1 Intel®ICH2 – LAN Interconnect Guidelines .........................................132
11.9.1.1 Bus Topologies ..................................................................133
11.9.1.2 Point-to-Point Interconnect ................................................133
11.9.1.3 LOM/CNR Interconnect......................................................134
11.9.1.4 Signal Routing and Layout .................................................135
11.9.1.5 Crosstalk Consideration.....................................................135
11.9.1.6 Impedances .......................................................................135
11.9.1.7 Line Termination ................................................................136
11.9.2 General LAN Routing Guidelines and Considerations ........................136
11.9.2.1 General Trace Routing Considerations..............................136
11.9.2.2 Power and Ground Connections........................................138
11.9.2.3 A 4-Layer Board Design.....................................................139
11.9.2.4 Common Physical Layout Issues .......................................139
11.9.3 Intel®82562EH Home/PNA* Guidelines..............................................141
11.9.3.1 Power and Ground Connections........................................141
11.9.3.2 Guidelines for Intel®82562EH Component Placement......141
11.9.3.3 Crystals and Oscillators .....................................................142
11.9.3.4 Phoneline HPNA Termination ............................................142
11.9.3.5 Critical Dimensions ............................................................143
11.9.4 Intel®82562ET / Intel®82562EM Guidelines ......................................144
11.9.4.1 Guidelines for Intel®82562ET / Intel®82562EM Component
Placement ..........................................................................144
11.9.4.2 Crystals and Oscillators .....................................................145
11.9.4.3 Intel®82562ET / Intel®82562EM Termination Resistors...145
11.9.4.4 Critical Dimensions ............................................................145
11.9.4.5 Reducing Circuit Inductance ..............................................147
11.9.5 Intel®82562ET/82562EM Disable Guidelines .....................................148
11.9.6 Intel®82562ET / Intel®82562EH Dual Footprint Guidelines ...............149
11.10 LPC/FWH............................................................................................................151
11.10.1 In-Circuit FWH Programming..............................................................151
11.10.2 FWH VPP Design Guidelines ...............................................................151
11.10.3 FWH Decoupling .................................................................................152
12 Clocking...........................................................................................................................153
12.1 2-DIMM Clocking ................................................................................................153
12.2 3-DIMM Clocking ................................................................................................155
12.3 Clock Routing Guidelines....................................................................................157
12.4 Clock Driver Frequency Strapping ......................................................................159

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12.5 Clock Skew Assumptions ...................................................................................160
12.6 Intel®CK-815 Power Gating On Wake Events ...................................................161
13 Power Delivery.................................................................................................................163
13.1 Power Delivery Guidelines ..................................................................................163
13.1.1 5V Dual Switch ....................................................................................165
13.1.2 VTT......................................................................................................165
13.1.3 1.85 V ..................................................................................................165
13.1.4 VDDQ ..................................................................................................165
13.1.5 3.3VSB ................................................................................................166
13.1.6 1.85VSB ..............................................................................................166
13.1.7 VCMOS ...............................................................................................166
13.2 Thermal Design Power .......................................................................................167
13.2.1 Pull-Up and Pull-Down Resistor Values ..............................................167
13.3 ATX Power Supply PWRGOOD Requirements..................................................168
13.4 Power Management Signals ...............................................................................168
13.4.1 Power Button Implementation .............................................................169
13.4.2 1.85 V/3.3 V Power Sequencing..........................................................170
13.4.3 V5REF/3.3 V Sequencing....................................................................171
13.5 Power Plane Splits ..............................................................................................172
13.6 Glue Chip 3 (ICH2 Glue Chip) ............................................................................173
14 System Design Checklist.................................................................................................175
14.1 Design Review Checklist ....................................................................................175
14.2 Processor Checklist ............................................................................................175
14.2.1 GTL Checklist......................................................................................175
14.2.2 CMOS Checklist ..................................................................................176
14.2.3 TAP Checklist for 370-Pin Socket Processors ....................................176
14.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ....................177
14.3 GMCH Checklist .................................................................................................178
14.3.1 System Memory Interface Checklist....................................................178
14.3.2 Hub Interface Checklist .......................................................................178
14.3.3 Digital Video Output Port Checklist .....................................................179
14.4 Intel®ICH2 Checklist...........................................................................................179
14.4.1 PCI Interface .......................................................................................179
14.4.2 Hub Interface.......................................................................................179
14.4.3 LAN Interface ......................................................................................180
14.4.4 EEPROM Interface..............................................................................180
14.4.5 FWH/LPC Interface .............................................................................180
14.4.6 Interrupt Interface ................................................................................180
14.4.7 GPIO Checklist....................................................................................182
14.4.8 USB .....................................................................................................182
14.4.9 Power Management ............................................................................183
14.4.10 Processor Signals ...............................................................................184
14.4.11 System Management ..........................................................................184
14.4.12 RTC ...........................................................................................184
14.4.13 AC ’97 ...........................................................................................185
14.4.14 Miscellaneous Signals .........................................................................186
14.4.15 Power ...........................................................................................187
14.4.16 IDE Checklist.......................................................................................188
14.5 LPC Checklist .....................................................................................................190
14.6 System Checklist ................................................................................................191

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14.7 FWH Checklist ....................................................................................................191
14.8 Clock Synthesizer Checklist................................................................................192
14.9 System Memory Checklist ..................................................................................193
14.10 Power Delivery Checklist ....................................................................................193
15 Third-Party Vendor Information .......................................................................................195

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Figures
Figure 1. System Block Diagram .......................................................................................18
Figure 2. Component Block Diagram ................................................................................19
Figure 3. AC ’97 Audio and Modem Connections .............................................................25
Figure 4. Board Construction Example for 60 ΩNominal Stack-up ..................................27
Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer ..............................29
Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer .................................29
Figure 7. Bottom Signal Layer before the Ground Fill Near the I/O Area ..........................30
Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O......................................30
Figure 9. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)................................31
Figure 10. ICH2 360-Ball EBGA Quadrant Layout (Top View) ..........................................32
Figure 11. Firmware Hub (FWH) Packages ......................................................................33
Figure 12. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370
Designs Using A-2 GMCH..........................................................................................37
Figure 13. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit ................38
Figure 14. VTT Selection Switch ........................................................................................39
Figure 15. Switching Pin AG1............................................................................................40
Figure 16. Processor Identification Strap on GMCH .........................................................41
Figure 17. VTTPWRGD Configuration Circuit ...................................................................42
Figure 18. GTL_REF/VCMOS_REF Voltage Divider Network ..........................................43
Figure 19. Resistor Divider Network for Processor PWRGOOD.......................................44
Figure 20 Voltage Switch for Processor APIC Clock.........................................................45
Figure 21. GTLREF Circuit Topology ................................................................................46
Figure 22. Gating Power to Intel®CK-815 .........................................................................47
Figure 23 PWROK Gating Circuit for Intel®ICH2..............................................................48
Figure 24. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..52
Figure 25. AGTL/AGTL+ Trace Routing............................................................................53
Figure 26. Routing for THRMDP and THRMDN................................................................56
Figure 27. Example Implementation of THERMTRIP Circuit ............................................57
Figure 28 Thermtrip Support for A-1 Stepping 0.13 Micron Technology Processors........59
Figure 29. BSEL[1:0] Circuit Implementation for PGA370 Designs...................................63
Figure 30. Examples for CLKREF Divider Circuit..............................................................64
Figure 31. RESET#/RESET2# Routing Guidelines ...........................................................65
Figure 32. Filter Specification ............................................................................................67
Figure 33. Example PLL Filter Using a Discrete Resistor .................................................69
Figure 34. Example PLL Filter Using a Buried Resistor ....................................................69
Figure 35. Core Reference Model .....................................................................................70
Figure 36. Capacitor Placement on the Motherboard........................................................71
Figure 37. Heatsink Volumetric Keep-Out Regions...........................................................73
Figure 38 Motherboard Component Keep-Out Regions....................................................73
Figure 39. Keep-Out Requirements for the 370-pin (Top View)........................................74
Figure 40. TAP Connector Comparison ............................................................................75
Figure 41. System Memory Routing Guidelines ................................................................77
Figure 42. System Memory Connectivity (2 DIMM) ...........................................................78
Figure 43. System Memory 2-DIMM Routing Topologies..................................................79
Figure 44. System Memory Routing Example ...................................................................80
Figure 45. System Memory Connectivity (3 DIMM) ...........................................................81
Figure 46. System Memory 3-DIMM Routing Topologies..................................................82
Figure 47. Intel815 Chipset Platform Decoupling Example ............................................83
Figure 48. Intel®815 Chipset Decoupling Example...........................................................84
Figure 49. Display Cache Input Clocking...........................................................................88

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Figure 50. Schematic of RAMDAC Video Interface...........................................................90
Figure 51. Cross-Sectional View of a Four-Layer Board ...................................................91
Figure 52. Recommended RAMDAC Component Placement and Routing ......................92
Figure 53. Recommended RAMDAC Reference Resistor Placement and Connections ..93
Figure 54. Hub Interface Signal Routing Example ............................................................97
Figure 55. Single Hub Interface Reference Divider Circuit................................................99
Figure 56. Locally Generated Hub Interface Reference Dividers ......................................99
Figure 57. Intel®ICH2 Decoupling Capacitor Layout.......................................................102
Figure 58. Combination Host-Side / Device-Side IDE Cable Detection ..........................106
Figure 59. Device-Side IDE Cable Detection...................................................................107
Figure 60. Connection Requirements for Primary IDE Connector...................................108
Figure 61. Connection Requirements for Secondary IDE Connector..............................109
Figure 62. Intel®ICH2 AC ’97– Codec Connection .........................................................110
Figure 63. CNR Interface.................................................................................................111
Figure 64. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard......112
Figure 65. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade..........113
Figure 66. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR .................................................................................................114
Figure 67. CDC_DN_ENAB# Support for Two-Codecs on Motherboard /
Two-Codecs on CNR ...............................................................................................114
Figure 68. Example Speaker Circuit................................................................................116
Figure 69. USB Data Signals...........................................................................................119
Figure 70. Example PIRQ Routing ..................................................................................120
Figure 71. SMBus/SMLink Interface................................................................................121
Figure 72. Unified VCC_Suspend Architecture ...............................................................123
Figure 73. Unified VCCCORE Architecture.........................................................................123
Figure 74. Mixed VCC_Suspend/VCCCORE Architecture .................................................124
Figure 75. PCI Bus Layout Example................................................................................125
Figure 76. External Circuitry for the ICH2 RTC ...............................................................126
Figure 77. Diode Circuit to Connect RTC External Battery..............................................128
Figure 78. RTCRST External Circuit for ICH2 RTC ........................................................129
Figure 79. RTC Power Well Isolation Control..................................................................130
Figure 80. Intel®ICH2 / LAN Connect Section ................................................................132
Figure 81. Single-Solution Interconnect...........................................................................133
Figure 82. LOM/CNR Interconnect ..................................................................................134
Figure 83. LAN_CLK Routing Example ...........................................................................135
Figure 84. Trace Routing.................................................................................................137
Figure 85. Ground Plane Separation ...............................................................................138
Figure 86. Intel®82562EH Termination ...........................................................................142
Figure 87. Critical Dimensions for Component Placement..............................................143
Figure 88. Intel®82562ET/Intel®82562EM Termination .................................................145
Figure 89. Critical Dimensions for Component Placement..............................................146
Figure 90. Termination Plane ..........................................................................................148
Figure 91. Intel®82562ET/82562EM Disable Circuit.......................................................148
Figure 92. Dual-Footprint LAN Connect Interface ...........................................................149
Figure 93. Dual-Footprint Analog Interface .....................................................................149
Figure 94. FWH VPP Isolation Circuitry ..........................................................................151
Figure 95. Platform Clock Architecture for a 2-DIMM Solution........................................154
Figure 96. Platform Clock Architecture for a 3-DIMM Solution........................................156
Figure 97. Clock Routing Topologies ..............................................................................157
Figure 98. Power Delivery Map........................................................................................164
Figure 99. Pull-Up Resistor Example ..............................................................................167
Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit ........................................170
Figure 101. V5REF/3.3 V Sequencing Circuitry ..............................................................171