Intel 82563EB Guide

82563EB/82564EB LAN on
Motherboard Design Guide
Application Note
May 2007
317104-001
Revision 2.6

ii
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82563EB/82564EB Gigabit Platform LAN Connect devices referenced in this document may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-
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Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation

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82563EB/82564EB LAN on Motherboard Design Guide
Revision History
Revision Revision Date Description
2.6 May 2007 • Updated Exposed Pad* landing pattern options.
2.5 May 2006 • Initial public release.
2.0 Nov 2005 • Intel confidential release.
1.75 July 2005 • Added a third magnetics module to Table 3.
• Changed power supply references from 1.8V to 1.9V.
• Changed crystal load capacitance parameter from 20 pF to 27 pF.
1.5 April 2005 • Updated crystal specifications.
• Added Bill of Materials (BOM) information.
1.0 Dec 2004 Major edits (including but not limited to), added landing pattern; added pointer
to BSDL file; added pointer to design checklists; adding pointer to reference
schematics.
0.70 Aug 2004 Added power supply guidelines, crystal guidelines.
0.50 May 2004 Initial publication of preliminary design guide information.

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82563EB/82564EB LAN on Motherboard Design Guide
Contents
1.0 Introduction ......................................................................................................................1
1.1 Scope....................................................................................................................1
1.2 Reference Documents...........................................................................................2
1.3 Product Codes.......................................................................................................2
2.0 Kumeran Connection to 82563EB/82564EB Gigabit Platform LAN Connect..............3
2.1 Kumeran Reference Clock....................................................................................4
2.2 631xESB/632xESB to 82563EB/82564EB Signals...............................................5
3.0 Ethernet Component Design Guidelines .......................................................................7
3.1 General Design Considerations for Ethernet Platform LAN Connect Devices......7
3.1.1 Clock Source............................................................................................7
3.1.2 Integrated Magnetics Module for 1000 BASE-T.......................................7
3.2 Designing with the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect..9
3.2.1 Powering Down the 82563EB/
82564EB Gigabit Ethernet Platform LAN Connect...................................9
3.2.2 Serial EEPROM for 82563EB/
82564EB Gigabit Ethernet Platform LAN Connect Implementations .......9
3.2.3 Power Supplies for the 82563EB/82564EB Device..................................9
3.2.4 82563EB/82564EB Device Power Supply Filtering................................12
3.2.5 82563EB/82564EB Device Test Capability............................................12
3.2.5.1 XOR Testing..............................................................................13
4.0 Frequency Control Device Design Considerations.....................................................15
4.1 Frequency Control Component Types ................................................................15
4.2 Quartz Crystal .....................................................................................................15
4.3 Fixed Crystal Oscillator .......................................................................................15
4.4 Programmable Crystal Oscillators.......................................................................16
4.5 Ceramic Resonator .............................................................................................16
5.0 Crystal Selection Parameters........................................................................................17
5.1 Vibrational Mode .................................................................................................17
5.2 Nominal Frequency.............................................................................................18
5.3 Frequency Tolerance ..........................................................................................18
5.4 Temperature Stability and Environmental Requirements....................................18
5.5 Calibration Mode.................................................................................................18
5.6 Load Capacitance ...............................................................................................19
5.7 Shunt Capacitance..............................................................................................20
5.8 Equivalent Series Resistance..............................................................................20
5.9 Drive Level ..........................................................................................................20
5.10 Aging...................................................................................................................20
5.11 Reference Crystal................................................................................................20
5.11.1 Reference Crystal Selection...................................................................21
5.11.2 Circuit Board...........................................................................................21
5.11.3 Temperature Changes ...........................................................................21

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82563EB/82564EB LAN on Motherboard Design Guide
6.0 Oscillator Support..........................................................................................................23
6.1 Oscillator Solution...............................................................................................24
6.1.1 High Voltage Solution (VDD = 3.3V)......................................................24
7.0 Ethernet Component Layout Guidelines .....................................................................25
7.1 Layout Considerations for the 82563EB/
82564EB Ethernet Platform LAN Connect Devices............................................25
7.1.1 Guidelines for Component Placement....................................................25
7.1.2 Crystals and Oscillators..........................................................................26
7.1.3 Board Stack Up Recommendations.......................................................27
7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs.......................27
7.1.4.1 Signal Termination and Coupling..............................................27
7.1.5 Signal Trace Geometry for 1000 BASE-T Designs................................27
7.1.6 Trace Length and Symmetry for 1000 BASE-T Designs........................28
7.1.7 Trace Routing, Geometry and Length for the Kumeran interface ..........28
7.1.7.1 Signal Termination and Coupling..............................................29
7.1.8 Impedance Discontinuities .....................................................................30
7.1.9 Reducing Circuit Inductance ..................................................................30
7.1.10 Signal Isolation.......................................................................................30
7.1.11 Power and Ground Planes.....................................................................30
7.1.12 Traces for Decoupling Capacitors..........................................................31
7.1.13 Ground Planes Under a
Magnetics Module (Copper-Based Gigabit designs)..............................32
7.1.14 Light Emitting Diodes for
Designs Based on 82563EB/82564EB Device ......................................34
7.1.15 Thermal Design Considerations.............................................................34
7.2 Physical Layer Conformance Testing .................................................................34
7.2.1 Conformance Tests for 10/100/1000 Mbps Designs..............................35
7.3 Troubleshooting Common Physical Layout Issues .............................................35
8.0 82563EB/82564EB Exposed Pad*.................................................................................37
8.1 Introduction .........................................................................................................37
8.2 Component Pad, Solder Mask and Solder Paste................................................38
8.3 Landing Pattern A (No Via In Pad)......................................................................40
8.4 Landing Pattern B (Thermal Relief; No Via In Pad) ............................................41
8.5 Landing Pattern C (Via in Pad) ...........................................................................42
9.0 Bill of Materials (BOM)...................................................................................................43
10.0 Design, Layout, and Test Checklists............................................................................45
10.1 Schematic Checklist............................................................................................45
10.2 Board Layout and Placement Checklist ..............................................................50
10.3 Validation Checklist.............................................................................................54
11.0 Reference Schematic.....................................................................................................55
12.0 System Manageability....................................................................................................57
A Measuring LAN Reference Frequency Using a Frequency Counter .........................59
A.1 Background.........................................................................................................59
A.2 Required Test Equipment ...................................................................................59
A.3 Indirect Probing Method......................................................................................59

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82563EB/82564EB LAN on Motherboard Design Guide
A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps..60
A.5 Direct Probing Test Method, Applicable
for Most 10/100 Devices (Devices that do NOT support 1000Base-T)...............61
A.6 Direct Frequency Measurement and Frequency Accuracy Calculation Steps....62
Figures
1 82563EB/82564EB Connection to the 631xESB/632xESB...................................3
2 631xESB/632xESB Clock Source Diagrams.........................................................4
3 AC Capacitor Placement.......................................................................................5
4 LVR Circuit for the 82563EB (Dual Port).............................................................10
5 LVR Circuit for the 82564EB (Single Port)..........................................................10
6 82563EB Power Sequencing ..............................................................................11
7 Maximum Difference between Voltage Rails.......................................................11
8 XOR Tree Concept..............................................................................................13
9 Internal Oscillator Circuit.....................................................................................19
10 General Placement Distances for 1000 BASE-T Designs...................................26
11 Trace Routing......................................................................................................29
12 Ground Plane Separation....................................................................................32
13 Ideal Ground Split Implementation......................................................................33
14 82563EB/82564EB Silkscreen and Components Pad (Top View)......................38
15 82563EB/82564EB Solder Mask.........................................................................39
16 82563EB/82564EB Solder Paste........................................................................39
17 82563EB/82564EB Landing Pattern A
(Top View - Vias on the Outside of the Exposed Pad*).......................................40
18 Landing Pattern B (Top View - Vias on the Outside of the Exposed Pad*).........41
19 82563EB/82564EB Landing Pattern C
(Top View - Vias on the Inside of the Exposed Pad*) .........................................42
20 Indirect Probing Setup.........................................................................................60
21 Direct Probing Method.........................................................................................62
Tables
1 Product Ordering Codes........................................................................................2
2 Reference Clocks Required ..................................................................................4
3 Third-party Magnetics Modules.............................................................................8
4 PNP Transistors Vendors/Part Numbers.............................................................10
5 Minimum Number of Bypass Capacitors per Voltage Rail ..................................12
6 Tested pins included in XOR Tree (33 pins) .......................................................14
7 Pins not included in the XOR tree (10 pins) ........................................................14
8 Crystal Manufacturers and Part Numbers...........................................................17
9 Crystal Parameters..............................................................................................17
10 82563EB/82564EB Clock Oscillator Specifications.............................................23
11 Oscillator Manufacturers and Part Numbers.......................................................23
12 Capacitor Stuffing Option Recommended Values...............................................33
13 BOM for the 631xESB/632xESB and the
82563EB/82564EB Gigabit Platform LAN Connect.............................................43

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82563EB/82564EB LAN on Motherboard Design Guide
1
1.0 Introduction
The Intel 82563EB/82564EB Gigabit Platform LAN Connect device is a dual/single, compact
component designed for 10/100/1000 Mbps operation. The Intel 82563EB/82564EB Gigabit
Platform LAN Connect device enables dual/single port Gigabit Ethernet implementation in a very
small area — easing routing constraints from the chipset to the PHY. Note that the 82564EB
Gigabit Platform LAN Connect device is the single port implementation.
The Intel 82563EB/82564EB Gigabit Platform LAN Connect device provides a standard IEEE
802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3,
802.3u, and 802.3ab).
The 82563EB/82564EB Gigabit Platform LAN Connect device is designed for high performance.
The device connects directly to the Intel® 631xESB/632xESB I/O Controller Hub using the serial
Kumeran interface.
The 82563EB/82564EB Gigabit Platform LAN Connect device is packaged in a 14 mm x 14 mm x
1.2 mm with 0.5 mm pitch leads, 100-pin TQFL with Exposed-Pad*. An Exposed-Pad* is a central
pad on the bottom of the package that serves as a ground and thermal connection.
1.1 Scope
This application note contains Ethernet design guidelines applicable to 82563EB/82564EB LOM
designs based on 631xESB/632xESB designs. All guidelines are applicable to both the 82563EB
and 82564EB unless specifically specified.
Section 1 – introduction and reference documents
Section 2 – describes the bus interfaces specific to the 82563EB/82564EB device
Section 3 – discusses Ethernet design considerations
Section 4 – discusses attributes of various frequency control devices
Section 5 – describes methods for crystal validation
Section 6 – discusses frequency control alternatives to crystal
Section 7 – discusses Ethernet layout considerations
Section 8 – shows the landing pattern options
Section 9 – lists the Bill of Materials (BOM).
Section 10 – provides schematic, board layout and placement, and validation checklists.
Section 11 – provides link to reference schematics
Appendix A – discusses use of a frequency counter to measure LAN reference signal
Note: This document contains information on products in the design phase of development. Product
features and specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.

82563EB/82564EB LAN on Motherboard Design Guide
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1.2 Reference Documents
This application note assumes that the designer is acquainted with high-speed design and board
layout techniques. The following documents provide additional information:
•82563EB/82564EB Gigabit Ethernet Platform LAN Connect Network Silicon Datasheet, Intel
Corporation.
•631xESB/632xESB I/O Controller Hub EEPROM Information Guide Application Note (AP-
477), Intel Corporation.
•82571/82572/631xESB/632xESB System Manageability Application Note (AP-497), Intel
Corporation.
•82563EB/82564EB Gigabit Platform LAN Connect Specification Update and Sighting
Information, Intel Corporation.
•IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers (IEEE).
— Incorporates various IEEE standards previously published separately.
•IEEE Standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers
(IEEE).
•PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Specification, September 4, 2002,
Version 0.90. PCI Industrial Computer Manufacturers Group (PICMG).
•Intel® 631xESB/632xESB I/O Controller Hub External Design Specification (EDS) - Volume
1-3, Intel Corporation.
•Bensley/Bensley-VS Platform Design Guide, Intel Corporation.
•Oscillation Circuit Design Guide Application Note, Epson Electronics America, Inc.
•Quartz Crystal Theory of Operation and Design Notes. Fox Electronics.
•Crystal Technical Glossary. Fox Electronics.
•Crystal Frequently Asked Questions. Fox Electronics.
•Resonator Terminology and Formulas. Piezo Technology, Inc.
Note: Intel documentation is subject to frequent revision. Verify with your local Intel sales office that you
have the latest information before finalizing a design
1.3 Product Codes
The following Table 1 lists the product ordering codes for the 82563EB dual port device and the
82564EB single port device.
Table 1. Product Ordering Codes
Device Product Code
Dual Port (Leaded) HU82563EB
Single Port (Leaded) HU82564EB
Dual Port (Lead Free) HY82563EB
Single Port (Lead Free) HY82564EB

82563EB/82564EB LAN on Motherboard Design Guide
3
2.0 Kumeran Connection to 82563EB/82564EB Gigabit
Platform LAN Connect
The Kumeran interface is a 4-pin (RXx_PLUS, RXx_MINUS, TXx_PLUS, TXx_MINUS, where
the lower case ‘x’ represents port ‘A’ or port ‘B’, if using the dual device) differential interface for
each Ethernet port based on PICMG 3.1 standard. The clock is embedded within the differential
signals and runs at 1.25 Gbps. There is no need for the additional MDIO/MDC signals as the PHY
management information is passed through in-band. Special encoded packets will carry the MDIO
information.
The Kumeran interface architecture in the PHY and in the MAC sides is symmetric.
In the TX side, the data is translated by the MAC to PCS order sets codes as described in 802.3
standard clause 36. The control data is inserted in the data flow and the data stream is serialized
using 8b/10b encoding.
In the RX side, the clock is recovered from data stream and data is de-serialized. The 10 bits are
translated to 8 bits by the PCS logic and the control data is removed from data flow.
The TX lane of the MAC side is responsible to insert Control & Status packets during data idle
time. Theses packets include MDIO registers RD/WR access commands, power-saving commands
or LED control. The RX lane of PHY side will remove these packets and transfer them to the PHY
registers and LEDs.
The TX lane of the PHY side will insert the Control & Status packets with the response of registers
RD/WR accesses or the twisted-pairs link status. The link status is sent automatically after link is
changed, or after a constant time-out. The RX lane of MAC side will remove link status and
registers access responses and update the MAC logic accordingly.
Figure 1. 82563EB/82564EB Connection to the 631xESB/632xESB
NOTE: 82564EB will only have Port 0 to Port A connections.
631xESB/
632xESB 82563EB
SERP0 TXA_PLUS
SERN0 TXA_MINUS
SETP0 RXA_PLUS
SETN0 RXA_MINUS
SER_CLK_IN PHY_CLK_OUT
LINK_0 LINK_A
SETP1 RXB_PLUS
SETN1 RXB_MINUS
SERP1 TXB_PLUS
SERN1 TXB_MINUS
Port 0
Port 1 Port B
Port A
LINK_1 LINK_B

82563EB/82564EB LAN on Motherboard Design Guide
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2.1 Kumeran Reference Clock
The 82563EB/82564EB Gigabit Ethernet Platform LAN Connect uses an embedded clock within
the Kumeran differential signals to recover the data. This reference clock may be generated in one
of two ways dependant on the length of the Kumeran interface board traces as shown in Figure 2.
Figure 2. 631xESB/632xESB Clock Source Diagrams
NOTE: Figure also reflects the same behavior in the single port 82564EB device.
If the length of the Kumeran board traces are 15 inches or less, then the 82563EB/82564EB uses its
25 MHz crystal and internal PLL to provide a 62.5 MHz clock to the 631xESB/632xESB. If the
length of the Kumeran board traces are greater than 15 inches, an oscillator needs to be connected
directly to the 631xESB/632xESB in addition to the 25 MHz crystal that is on the 82563EB/
82564EB. In this case, the 82563EB/82564EB does not provide a direct reference clock to the
631xESB/632xESB. The oscillator at the 631xESB/632xESB is necessary due to the signal quality
degradation as the routed distance is increased.
A 25 MHz crystal is required for the 82563EB/82564EB for both cases as seen in Table 2.
Table 2. Reference Clocks Required
Kumeran Length 25 MHz Crystal on the 82563EB/
82564EB
62.5 MHz Oscillator on
the 631xESB/632xESB
Less than or equal to 15 inches Yes No
More than 15 inches Yes Yes
RX
TX
RX
TX
TX
RX
TX
RX
PHY_CLK_OUTSER_CLK_I N
X1 X2
25.000 MHz
Length > 15
inches
62.5 MHz oscill ator
RX
TX
RX
TX
TX
RX
TX
RX
PHY_CL K_OUTSER_CL K_I N
X1 X2
25.000 MHz
Length < 15
inches
82563EB 82563EB
631xESB/
632xESB
631xESB/
632xESB

82563EB/82564EB LAN on Motherboard Design Guide
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2.2 631xESB/632xESB to 82563EB/82564EB Signals
The 82563EB/82564EB device implements signals such as the receive signals RXx_PLUS and
RXx_MINUS, as well as the transmit signals TXx_PLUS and TXx_MINUS. Please note that
documentation for 82563EB designates the two ports as A and B and the 631xESB/632xESB
designates them as ports 0 and 1, respectively. Furthermore, unlike PCI-Express, there is no
polarity correction; failure to match polarity correctly may result in a non-functional LAN solution.
These four signals per port are AC-coupled and their respective capacitors (10 nF, type X7R, size
0402 or 0603) should be placed near the receiver side.
NOTE: Figure also reflects the same behavior in the single port 82564EB device.
Figure 3. AC Capacitor Placement
The Gigabit Ethernet Platform LAN Connect has the option to signal power management events to
the system using:
•PHY_SLEEP signal, which will power down the PHY and the Kumeran interface
•PHY_RESET_N signal, which resets the PHY and Kumeran interface
Note: The above connection is not recommended for system designs — power management events will
be passed in band via the Kumeran interface.
The PHY_PWR_GOOD signal indicates that stable power is available for all voltage rails that
power the 82563EB/82564EB and that the device is ready to come out of an otherwise held reset.
Typically, this connects to the system’s RSM_RST# signal.
The PHY_CLK_OUT signal is the output clock available for use by the 631xESB/632xESB for
Kumeran trace length less than or equal to 15 inches. For distances greater than 15 inches, a
discrete oscillator needs to supply the reference clock to the 631xESB/632xESB directly via the
SER_CLK_IN. To ensure signal integrity and feasibility of trace lengths a designer may want to do
some simulations. If the Gigabit Ethernet Platform LAN Connect is supplying the clock to the
631xESB/632xESB via PHY_CLK_OUT, the designer should place a 40 Ωseries termination
resistor near the PHY_CLK_OUT pin. This is needed in order to reduce ringing due to the strong
driver and is required regardless of the length of the clock trace to the 631xESB/632xESB.
631xESB/
632xESB
631xESB/
632xESB
631xESB/
632xESB
TX
631xESB/
632xESB
RX
82563EB
RX
82563EB
TX
82563EB
82563EB
250 mil
bracket
250 mil
bracket
250 mil
bracket
250 mil
bracket

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82563EB/82564EB LAN on Motherboard Design Guide
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3.0 Ethernet Component Design Guidelines
These sections provide recommendations for selecting components and connecting special pins.
For 1000 BASE-T designs, the main design elements are the 631xESB/632xESB, 82563EB/
82564EB Gigabit Ethernet Platform LAN Connect, an integrated magnetics module with RJ-45
connector, an EEPROM, and a clock source.
3.1 General Design Considerations for Ethernet Platform LAN
Connect Devices
Follow good engineering practices with respect to unused inputs by terminating them with pull-up
or pull-down resistors, unless the datasheet, design guide or reference schematic indicates
otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect.
These devices may have special test modes that could be entered unintentionally.
3.1.1 Clock Source
All designs require a 25 MHz clock source. The 82563EB/82564EB Gigabit Ethernet Platform
LAN Connect uses the 25 MHz source to generate clocks up to 125 MHz and 1.25 GHz for the
PHY circuits, and 1.25 GHz for the Kumeran interface. For optimum results with lowest cost,
connect a 25 MHz parallel resonant crystal and appropriate load capacitors at the XTAL1 and
XTAL2 leads. The frequency tolerance of the timing device should be 30 ppm or better. Refer to
the sections, “Frequency Control Device Design Considerations” and “Crystal Selection
Parameters”, for more information on choosing crystals.
There are three steps to crystal qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet the required
conditions for frequency, frequency tolerance, temperature, oscillation mode and load
capacitance as specified in the 82563EB/82564EB datasheet.
2. Independently measure the component’s electrical parameters in real systems. Measure
frequency at a test output to avoid test probe loading effects at LEDA_RX_ACTIVITY_N for
port A and LEDB_RX_ACTIVITY_N for port B. Check that the measured behavior is
consistent from sample to sample and that measurements meet the published specifications.
For crystals, it is also important to examine startup behavior while varying system voltage and
temperature. Refer to Appendix A, “Measuring LAN Reference Frequency Using a Frequency
Counter”.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems.
3.1.2 Integrated Magnetics Module for 1000 BASE-T
The magnetics module has a critical effect on overall IEEE and emissions conformance. The
device should meet the performance required for a design with reasonable margin to allow for
manufacturing variation. Occasionally, components that meet basic specifications may cause the
system to fail IEEE testing because of interactions with other components or the printed circuit
board itself. Carefully qualifying new magnetics modules prevents this problem.

82563EB/82564EB LAN on Motherboard Design Guide
8
The steps involved in magnetics module qualification are similar to those for crystal qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet or exceed
the required IEEE specifications.
2. Independently measure the component’s electrical parameters on the test bench, checking
samples from multiple lots. Check that the measured behavior is consistent from sample to
sample and that measurements meet the published specifications.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems.
Vary temperature and voltage while performing system level tests.
Magnetics modules for 1000 BASE-T Ethernet are similar to those designed solely for 10/100
Mbps, except that there are four differential signal pairs instead of two. Use the following
guidelines to verify specific electrical parameters:
1. Verify that the rated return loss is 19 dB or greater from 2 MHz through 30 MHz for 100
BASE-TX.
2. Verify that the rated return loss is 12 dB or greater at 80 MHz for 100 BASE-TX (the
specification requires greater than or equal to 10 dB).
3. Verify that the rated return loss is 10 dB or greater at 100 MHz for 1000 BASE-TX (the
specification requires greater than or equal to 8 dB).
4. Verify that the insertion loss is less than 1.0 dB at 100 kHz through 80 MHz for 100 BASE-
TX.
5. Verify that the insertion loss is less than 1.4 dB at 100 kHz through 100 MHz for 1000 BASE-
T.
6. Verify at least 30 dB of crosstalk isolation between adjacent channels (through 150 MHz).
7. Verify high voltage isolation to 15000 Vrms
8. Transmitter OCL should be greater than or equal to 350 µH with 8 mA DC bias.
Table 3. Third-party Magnetics Modules1
1. These modules have been used successfully in past designs, however no
particular product is recommended.
Manufacturer Part Number
Pulse JW0A2P019D
Discrete H5007
Bel 0344FLA

82563EB/82564EB LAN on Motherboard Design Guide
9
3.2 Designing with the 82563EB/82564EB Gigabit Ethernet
Platform LAN Connect
This section provides design guidelines specific to the 82563EB/82564EB Gigabit Ethernet
Platform LAN Connect.
3.2.1 Powering Down the 82563EB/82564EB Gigabit Ethernet Platform LAN
Connect
The 82563EB/82564EB device has a signal named PHY_SLEEP that can be used as an alternative
to an in-band event for powering down the Ethernet PHY functions driven only by the 631xESB/
632xESB. When using the in-band event, PHY_SLEEP should be connected to a pulldown resistor
for normal operation.
3.2.2 Serial EEPROM for 82563EB/82564EB Gigabit Ethernet Platform LAN
Connect Implementations
Please note that the EEPROM is connected to the 631xESB/632xESB and not directly to the
82563EB/82564EB. Several words of the EEPROM are accessed automatically by the device after
reset to provide pre-boot configuration data before it is accessed by host software. The remainder
of the EEPROM space is available to software for storing the MAC address, serial numbers, and
additional information. More details may be obtained from the Bensley/Bensley-VS Platform
Design Guide.
Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program
EEPROM images in development or production line environments. To obtain a copy of this
program, contact your Intel representative.
3.2.3 Power Supplies for the 82563EB/82564EB Device
The 82563EB/82564EB device requires three power supplies (3.3V, 1.9V, and 1.2V). For
1000BASE-T designs, the 1.2V supply must provide approximately 580 mA current. The 1.9V
supply must provide approximately 850 mA current. The 3.3V supply must provide approximately
25 mA current.
A central power supply can provide all the required voltage sources, or the power can be derived
from the 3.3V supply and regulated locally near the Ethernet control circuitry. Keep in mind that all
voltage sources must remain present during powerdown in order to use the 82563EB/82564EB
Gigabit Ethernet Platform LAN Connect device's LAN wake up capability. This consideration
makes it more likely that at least some of the voltage sources will be local.
Instead of using external regulators to supply 1.2V and 1.9V, the designer may use power
transistors in conjunction with on-chip regulation circuitry. When using the internal voltage
regulation control logic, the sequencing of the voltages are controlled internally by the 82563EB/
82564EB. Refer to the 82563EB/82564EB Gigabit Platform LAN Connect Datasheet for specific
internal power sequencing requirements.

82563EB/82564EB LAN on Motherboard Design Guide
10
The design may require two external PNP transistors, one for 1.9V and the other for 1.2V
generation, if both voltages are going to be regulated by the 82563EB/82564EB. The beta for the
PNP transistors must be 100 or better. For the 82563EB only (not applicable to 82564EB single
port) resistors are required to dissipate heat with the dual-port platform LAN connect as shown in
Figure 4. Ensure that there is a 0.5 inch by 0.5 inch thermal relief for both transistors. If standby
3.3V is being used for power management, then ensure that the same 3.3V VccAux is sourcing the
transistor(s). To minimize inductance, CTRL_12 and CTRL_18 line must be less than two inches
routed length, and use 12 mil traces.
Figure 4. LVR Circuit for the 82563EB (Dual Port)
The single port 82564EB Platform LAN Connect requires less power than the dual port 82563EB
which eliminates the need for dissipation resistors as seen in Figure 5. The PNP transistor for the
82564EB still maintains the minimum beta of 100, with a separate transistor needed per voltage rail
similar to the 82563EB.
Figure 5. LVR Circuit for the 82564EB (Single Port)
Table 4 shows several vendors and their respective part numbers that are recommended for the
PNP transistors.
CTRL_x
Vcc3_3
Vou
t
1.0 ohm, 5%, 1/4W
1.0 ohm, 5%, 1/4W
Note: PNP needs 0.5 inch by
0.5 inch thermal relief pad
CTRL_x
Vcc3_3
Note: PNP needs 0.5 inch by
0.5 inch thermal relief pad
Vou
t
Table 4. PNP Transistors Vendors/Part Numbers
Vendor Part Number
Infineon BCP69-16
Philips BCP69-16
On Semi BCP69-16

82563EB/82564EB LAN on Motherboard Design Guide
11
If the designer chooses to do their own external voltage regulation and not use the PNP transistors,
then they must adhere to the sequencing shown in Figure 6 to avoid latch-up and forward-biased
internal diodes. The general guideline is that for power up, the higher voltage is up and stable prior
to the next lower voltage. In other words, 3.3V is greater than1.9V > 1.2V.
Figure 6. 82563EB Power Sequencing
In addition, as shown on Figure 7, the voltages must not exceed by more than 0.5V in each of the
following cases:
•The 82563EB/82564EB core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5V
at any time during the power up. The 82563EB core voltage (1.2V) can not exceed the 1.9V
supply by more than 0.5V at any time during the power up. The core voltage is not required to
begin ramping before the 3.3V or the 1.9V supply.
•The 82563EB/82564EB analog voltage (1.9V) cannot exceed the 3.3V supply by more than
0.5V at any time during the power up. The analog voltage is not required to begin ramping
before the 3.3V supply.
Figure 7. Maximum Difference between Voltage Rails
For power down, there is no specific requirement, only charge that is stored in the decoupling caps
remains.
1.2 V
3.3 V
1.9 V
T delay
V
t
3.3 V
1.2 V
Max
Difference ≤
0.5 V
1.9 V
Max
Difference ≤
0.5 V
V
t

82563EB/82564EB LAN on Motherboard Design Guide
12
The 82563EB/82564EB device has a PHY_PWR_GOOD input. Treat this signal as an external
device reset which works in conjunction with the internal power-on reset circuitry. In the situation
where a central power supply furnishes all the voltage sources, PHY_PWR_GOOD can possibly be
tied to the platform’s RSM_RST#. Designs that generate some of the voltages locally can connect
PHY_PWR_GOOD to a power monitor chip that monitors all three required voltages. Ensure that
the system holds PHY_PWR_GOOD inactive for at least 100 µsec after power-up of all three
voltages rails.
The power sources are all expected to ramp up during a brief power-up interval with
PHY_PWR_GOOD de-asserted. Do not leave the 82563EB/82564EB device in a prolonged state
where some, but not all, voltages are applied.
Warning: Do not tie PHY_PWR_GOOD directly to a voltage supply.
3.2.4 82563EB/82564EB Device Power Supply Filtering
Provide several high-frequency bypass capacitors for each power rail, selecting values in the range
of 0.001 µF to 0.01 µF. If possible, orient the capacitors close to the device and adjacent to power
pads. Place one 470 pF capacitor near AVDDF (pin 92) and another one 470 pF capacitor near
AVDDF (pin 86); these two power pins are used for the high speed Kumeran interface. Decoupling
capacitors should connect to the power planes with short, thick (15 mils - 0.4 mm or more) traces
and 14 mil (0.35 mm) vias.
Table 5. Minimum Number of Bypass Capacitors per Voltage Rail
Furnish approximately 4.7 µF of bulk capacitance for each of the main 1.2V and 1.9V levels,
placing them as close to the device power connections as possible. The minimum recommended
bypass capacitors for each voltage rail is shown in Figure 5. For internal voltage regulators, place
the bulk capacitor as close to the collector of the transistor. A low reactance path is mandatory to
maintain internal voltage regulator stability and reduce voltage oscillations.
3.2.5 82563EB/82564EB Device Test Capability
The 82563EB/82564EB Gigabit Ethernet Platform LAN Connect contains a test access port (3.3V
only) conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test
access port, connect these balls to pads accessible by your test equipment.
The device also contains an XOR test tree mechanism for simple board tests.
Voltage Rail 4.7 uF 0.1 uF 470 pF
3.3V 1 1 -
1.9V 1 2 2
1.2V 1 2 1