General Information
operation, the controlling bus master is allowed
to
access
RAM and complete its operation. Where both the CPU
and the controlling bus master have the need to write or
read several bytes
or
words to
or
from on-board RAM,
their operations ary interleaved. For CPU access, the
on-boardRAM addresses are assigned from the bottomup
of
the I-megabyte address space;
i.e.,
0OOOO-07FFFH·
The slave RAM address decode logic includes jumpers
and switchers to allow partitioning the on-based RAM
into any 128K segment
of
the
1-
megabyte system address
space.
Theslave RAM canbeconfigured toalloweither8K, 16K
24K,
or
32K access by another bus master. Thus, the
RAM can be configured to allow other bus masters to
access a segment
of
the on-board RAM and still reserve
another segment strictly for on-board use. The addressing
scheme accommodates both 16-bitand 20-bitaddressing.
Four IC sockets are included
to
accommodate up to 16K
bytes
of
user-installed read only memory. Configuration
jumpers allow read only memory to be installed in 2K,
4K,
or
8K increments.
The iSBC 86/12 includes 24 programmable parallel I/O
lines implemented by means
of
an Intel 8255A Pro-
grammable Peripheral Interface (PPI). The system
software
is
used to configure the I/O lines in any combina-
tion
of
unidirectional input/output and bidirectional ports.
The I/O interface may be customized to meet specific
peripheral requirements and, in order to take full advan-
tage
of
the large number
of
possible I/O configurations, IC
sockets are provided for interchangeable I/O line drivers
and terminators. Hence, the flexibility
of
the parallel I/O
interface
is
furtherenhanced by the capability
of
selecting
the appropriate combination
of
optional line drivers and
terminators'to provide the required sinkcurrent, polarity,
and drive/termination characteristics for each application.
The 24-programmable I/O ,lines and signal ground lines
are brought outto a 50-pin edge connector
(11)
that mates
with flat, woven,
or
round cable.
..
The RS232C compatible serial I/O port is controlled arid
interfaced by an Intel 8251A
US
ART (Universal
Syncronous/Asynchrortous ReceiverlTransmitter) chip.
The USART
is
individually programmable for operation
in most synchronous
or
asynchronous serial data trans-
mission formats (including·iBM Bi-Sync).
In the synchronous mode the following are programma- .
ble:
a. Character length,
b. Sync character (or chlU1lcters), and
c. Parity.
1-2
iSBC 86/12
In the asynchronous mode the following are program-
mable:
a.
Character length,
b.
Baud rate factor (clockdivide ratios
of
1, 16,
or
64),
c. Stop bits, and
d. Parity.
In both the synchronous and asychronous modes, the
serial I/O port features half-
or
full-duplex, double buf-
fered transmitand receive capability. In addition, USART
errordetection circuits can check for parity, overrun, and
framing errors. The USART transmit and receive clock
rates are supplied by a programmable baud rate/time
generator. These clocks may optionally be supplied from
an external source. The RS232C command lines, serial
data lines, and signal ground lines are brought out to a
50-pin edge connector
(12)
that mates with flat
or
round
cable.
Three independent, fully programmable 16-bit interval
timer/event counters are provided by an Intel 8253 Pro-
grammable Interval Timer (PIT). Each counteris capable
of
operating in either BCD
or
binary modes; two
of
these
counters are available
to
the systems designer to generate
accurate time intervals under software control. Routing
for the outputs and gate /trigger inputs
of
two
of
these
counters may
be
independently routed to the 8259A Prog-
rammable Interrupt Controller (PIC). The gate/trigger in-
puts
of
the two counters may
be
routed to I/O terminators
associated with the 8255A PPI
or
as input connections
from the 8255A PPI. The third counter is used as a
programmable baud rate generator for the serial
I/O
port.
In utilizing the iSBC 86/12, the systems designer simply
configures, via software, each counter independently to
meet system requirements. Whenever a given time delay
or count
is
needed, software commands to the 8253 PIT
select the desired function. The contents
of
each counter
may
be
read at any time during system operation with
simple operations for event counting applications, and
special commands are included
~
that the contents
of
each counter·can
be
read
"on
the
fly".
TheiSBC 86/
12
provides vectoring forbus vectored (BV)
~ruid
non-bus vectored (NBY) interrupts. An on-board
In.tel 8259A Programmable Interrupt Controller (PIC)
handles up to eight NBV interrupts. By using external
PIC's slaved. to the on-board PIC (master), the interrupt
structure can
be
expanded to handle and resolve the prior-
ityof
upto
64 BV sources.
The PIC, which can
be
programmed to respond to edge-
sensitive
or
level-sensitive inputs, treats each true input
signal condition as an interrupt request. After resolving
the interrupt priority, the PIC issues a single interrupt
request to the·CPU. Interrupt priorities are independently
programmable under software control. The program-
mable interrupt priority modes are:
