Intel iSBC 86/12 Quick user guide

rr
iSBC 86/12
SINGLE BOARD COMPUTER
HARDWARE
REFERENCE MANUAL
Manual Order Number: 9800645A
.
Copyright © 197E: Intel Corporation
I Intel Corporation, 3065 Bowers
Av.~nue, Santa Clara, California 95051 L

ii
The infonnation in this manual is subject to change without notice. Intel Corporation makes no warranty of any
kind with regard to this manual, including, but not limited to, the implied warranties
of merchantability and
fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this
manual. Intel Corporation makes no commitment to update nor to keep current the infonnation contained
in this manual.
No part of this manual may be copied orreproduced in any fonn or by any means without the priorwritten consent
of Intel Corporation. The following are trademarks of Intel Corporation and may be used only to describe
Intel products:
ICE· 30
ICE·gO
INSITE
INTEL
INTEU.EC
iSBC
LIBRARY MANAGER
MCS
MEGACHASSIS
MICROMAP
MULTIBUS
PROMPT
UPI
RMX
Printed in U.S,A./B66/0778(TL 7.SK

PREFACE
This manual provides general information, installation, programming information,
principles of operation, and service information for the Intel iSBC 86/12 Single Board
Computer. Additional information
is available in the following documents:
• 8086 Assembly Language Reference Ma~ual, Order No. 9800640
• Intel MCS-85 User's Manual, Order No. 98-366
• Intel 8255A Programmable Peripheral 1nterface, Application Note AP-15
• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter, Application
Note AP-16
• Intel MULTIBUS Interfacing, Application Note AP-28
• Intel 8259 Programmable Interrupt Cm~troller, Application Note AP-31
iii

CHAPTER 1
GENERAL INFORMATION
PAGE
Introduction .................................... , 1-1
Description ..................................... I-I
System Software Development ..................... 1-3
Equipment Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-3
Equipment Required
.............................. 1-3
Specifications ................................... 1-3
CHAPTER 2
PREPARATION FOR USE
Introduction ..................................... 2-1
Unpacking and Inspection ......................... 2-1
Installation Considerations . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
User-Furnished Components
..................... 2-1
Power Requirement ............................ 2-1
Cooling Requirement ........................... 2-1
Physical Dimensions ............................ 2-1
Component Installation. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
ROM/EPROM Chips ........................... 2-1
Line Drivers and I/O Terminators
................. 2-4
Jumper/Switch Configuration ....................... 2-4
RAM Addresses (Multibus Access)
................ 2-4
Priority Interrupts ... . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
Serial I/O Port Configuration. . . . . . . . . . . . . . . . . . . .. 2-9
Parallel I/O Port Configuration ................... 2-9
Multibus Configuration
........................... 2-9
Signal Characteristics .......................... 2-13
Serial Priority Resolution ....................... 2-13
Parallel Priority Resolution ..................... 2-13
Power Fail/Memory Protect Configuration ........... 2-13
Parallel I/O Cabling ............................. 2-23
Serial I/O Cabling ............................... 2-23
Board Installation
............................... 2-23
CHAPTER 3
PROGRAMMING INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Failsafe Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 3-1
Memory Addressing
.............................. 3-1
CPU Access .................................. 3-1
Multibus Access
................................ 3-2
I/O Addressing .................................. 3-3
System Initialization .............................. 3-3
8251A USART Programming
...................... 3-4
Mode Instruction Fonnat
........................ 3-4
Sync CharaCters ............................... 3-5
Command Instruction Fonnat
.................... 3-5 .
Reset
........................................ 3-5
Addressing
.................................... 3-5
Initialization
.................................. 3-6
Operation ..................................... 3-7
Data Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 3-7
Status Read ................................. 3-7
iv
CONTENTS]
PAGE
8253 PIT Programming ........................... 3-8
Mode Control Word and Count
................... 3-8
Addressing
.................................. 3-12
Initialization
................................. 3-12
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1"3
Counter Read .............................. 3-13
Clock Frequency/Divide Ratio Selection
......... 3-13
Rate Generator/Interval
Timer. . . . . . . . . . . . . . . .. 3-14
Interrupt Timer
............................. 3-14
8255;\ ppl Programming . . . . . .. . . . . . . . . . . . . . . . . .. 3-14
Control Word Fonnat
.......................... 3-15
Addressing
.................................. 3-15
Iniitialization
................................. 3-16
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-16
Read Operation
............................. 3-16
Write Operation
............................ 3-16
8259A PIC-Programming ......................... 3-17
Interrupt Priority Modes. . . . . . . . . . . . . . . . . . . . . .
.. 3-17
Nested Mode
............................... 3-17
Fully Nested Mode
.......................... 3-17
Automatic Rotating Mode
.................... 3-17
Specific Rotating Mode ...................... 3-17
Special Mask Mode ......................... 3-18
Poll Mode ................................. 3-18
Status Read .................................. 3-18
Initialization Command Words
.................. 3-18
Operation Command Words. . . . . . . . . . . . . . . . . . . .. 3-19
Addressing
.................................. 3-19
Initialization
................................. 3-19
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-19
Hardware Interrupts
............................. 3-25
Non-Maskable Interrupt (NMI)
.................. 3-25
Maskable Interrupt (lNTR)
..................... 3-25
Master PIC Byte Identifier
.................... 3-25
Slave PIC Byte Identifier ....................• 3-25
CHAPTER 4
PRINCIPLES OF OPERATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Functional Description ............................ 4-1
Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-1
Interval Timer
................................. 4-1
Serial I/O ..................................... 4-1
Parallel I/O ................. . . . . . . . . . . . . . . . . .. 4-1
Interrupt Controller
.............•............... 4-2
ROM/EPROM Configuration ..................... 4-2
RAM Configuration
............................ 4-2
Bus Structure ................................. 4-2
Multibus Interface
............................. , 4-3
I,

PAGE
Circuit Analysis ................................. 4-3
Initialization
................................. 4-4
Clock Circuits ................................. 4-4
Central Processor Unit .......................... 4-4
Basic Timing ................................ 4-4
Bus Timing ................................. 4-4
Address Bus .................................. 4-6
Data Bus ..................................... 4-6
Bus Time Out ............................... " 4-6
Internal Control Signals ......................... 4-8
Dual Port Control Logic ........................... 4-8
Multibus Access Timing ........................ 4-8
CPU Access Timing ............................ 4-8
Multibus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11
I/O Operation .................................. 4-11
On-Board I/O Operation ....................... 4-11
System I/O Operation. . . . . . . . . . . . . . . . . . . . . . . . .. 4-12
ROM/EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . .. 4-12
CONTENTS (Continued)
PAGE
RA\1 Operation ................................ 4-12
RA\1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
RA\1 Chips .................................. 4-13
On-Board Read/Write Operation ................. 4-13
Bus Read/Write Operation
...................... 4-13
Byte Operation
............................. " 4-13
Interrupt
Operation. . . . . . . . . . . . . . . . . . . . . . . . . .. " 4-14
NBVlnterrupt ................................ 4-14
BV Interrupt ............................... " 4-14
CHAPTER 5
SERVICE INFORMATION
Introduction ..................................... 5-1
Replaceable Parts
............................. 5-1
Service Diagrams ............................ 5-1
Service and Repair Assistance. . . . . . . . . . . . . . . . . . 5-1
APPENDIX A
TELETYPEWRITER MODIFICATIONS
v

TABLE
1·1
2·1
2~2
2·3
2·4
2·5
2·6
2·7
2·8
2·9
2·10
2·11
2·12
2·13
2·14
2·15
2·16
2·17
3·}
3·2
3·3
3·4
3·5
vi
I
TITLE
PAGE
Specifications ........................... 1-4
User-Furnished- and Installed Components .... 2-2
User·
Furnished Connector Details ........... 2-3
Line Driver and I/O Terminator Locations . .
.. 2-4
Jumper and Switch Selectable Options
....... 2-5
Priority Interrupt Jumper Matrix
............ 2-8
Serial I/O Connector J2 Pin Assignments
Vs
Configuration Jumpers ....... : .......... 2-9
Parallel I/O Port ConfigurationJumpers
..... 2-10
Multibus Connector
PJ. Pin Assignments .... 2-14
Multibus Signal Functions
................ 2-15
iSBC 86/12 DC Characteristics
............ 2-16
iSBC 86/12 AC Characteristics
(Master Mode)
....................... 2-18
iSBC 86/12 AC Characteristics
(Slave Mode)
........ : ............... 2-18
Auxiliary Connector P2 Pin Assignments
.... 2-22
Auxiliary Signal (Connector P2)
DC Characteristics
............. ' ....... 2-22
Parallel I/O Connector
11
Pin Assignments ...................... 2-23
Parallel I/O Signal (Connector 11)
DC Characteristics .................... 2-24
Connector J2 Vs RS232C Pin
Correspondence
....................... 2-24
On-Board Memory Addresses
(CPU Access) ......................... 3-2
I/O Address Assignments .................. 3-3
Typical USART Mode
or Command
Instruction Subroutine
.................. 3-7
Typical USART Data,Character Read
Subroutine
............................ 3-8
Typical USART Data Character Write
Subroutine
............................ 3-8
TABLE
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3·24
3-25
5-1
5-2
TABLES
TITLE PAGE
Typical US ART Status Read Subroutine ..... 3-9
PIT Counter Operation
Vs Gate Inputs ...... 3·12
Typical PIT Control Word Subroutine ...... 3-12
Typical PIT Count Value Load
Subroutine
........................... 3·12
Typical PIT Counter Read Subroutine ...... 3-13
PIT Count Value
Vs Rate Multiplier for
Each Baud Rate
...................... 3-14
PIT Rate Generator Frequencies and
Timer Intervals . . . . . . . . . . . . . .
.. . . . . . .. 3-15
PIT Time Intervals
Vs Timer Counts ....... 3-15
Typical PPI Initialization Subroutine. . . . . .
.. 3-16
Typical PPI Port Read Subroutine
.......... 3-16
Typical PPI Port Write Subroutine
......... 3-16
Typical PIC Initialization Subroutine
(NBV Mode)
......................... 3-21
Typical Master PIC Initialization Subroutine
(BV Mode)
.......................... 3-21
Typical Slave PIC Initialization Subroutine
(BV Mode)
.......................... 3-22
PIC Operation Procedures
................ 3-22
Typical PIC Interrupt Request
Register Read Subroutine
............... 3-24
Typical PIC In-Service Register
Read Subroutine
...................... 3-24
Typical PIC Set Mask Register Subroutine
... 3-24
Typical PIC Mask Register Read
Subroutine
........................... 3-24
Typical PIC End-of-Interrupt Command
Subroutine
........................... 3-25
Replaceable Parts
........................ 5-1
List
of Manufacturers' Codes .............. 5·3
Ij'

FIGURE
TITLE
PAGE
I-I
iSBC 86/12 Single Board Computer .........
I-I
2-1 Dual Port RAM Address Configuration
(Multibus Access)
...................... 2-7
2-2 Simplified Master/Slave PIC
Interconnect Example
................... 2-8
2-3 Bus Exchange Timing (Master Mode)
......
2-19
2-4 Bus Exchange Timing (Slave Mode)
........ 2-20
2-5 Serial Priority Resolution Scheme
.......... 2-21
2-6 Parallel Priority Resolution Scheme
........
2-21
3-1 Dual Port RAM Addressing
(Multibus Access)
...................... 3-2
3-2 USART Synchronous Mode Instruction
Word Format
..........................
3-4
3-3 USART Synchronous Mode Transmission
Format
............................... 3-4
3-4
US ART Asynchronous Mode Instruction
Word Format
.......................... 3-5
3-5 USART Asynchronous Mode Transmission
Format
............................... 3-5
3-6 USART Command Instruction
Word Format ............................ 3-6
3-7 Typical USART Initialization and
I/O Data Sequence .....................
3-6
3-8 USART Status Read Format
............... 3-9
3-9 PIT Mode Control Word Format
........... 3-10
3-10 PIT Programming Sequence Examples
...... 3-11
FIGURE
3-11
3-12
3-13
3-14
3-15
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
5-4
ILLUSTRATIONS
TITLE PAGE
PIT Counter Register Latch Control
Word Format
..................... .
PPI Control Word Format
............... . 3-13
3-15
PPI Port C Bit Set/Reset Control
Word Format.
................... .
PIC Initialization Command
Word Formats
................... .
PIC Operation Control Word Formats
... .
iSBC 86/12 Input/Output and Interrupt
3-17
3-18
3-20
Simplified Logic
Diagram. . . . . . . . . . 4-15
iSBC 86/12 ROM/EPROM and Dual Port RAM
Simplified Logic Diagram " ............ 4-17
Internal Bus Structure ................... " 4-3
CPU Read Timing
........... , ........... 4-5
CPU Write Timing
....................... 4-6
CPU Interrupt Acknowledge
Cycle Timing
......................... 4-7
Dual Port Control Multibus Access
Timing With CPU Lockout
.. . . . . . . . . . . .. 4-9
Dual Port Control CPU Access Timing
With Multibus Lockout
................ 4-10
iSBC 86/12
PaJ1s Location Diagram ......... 5-6
iSBC 86/12 Schematic Diagram
............ 5-7
iSBC 604 Schematic Diagram
............. 5-29
iSBC 614 Schematic Diagram
............. 5-31
vii/viii

1-1. INTRODUCTION
The iSBC 86/12 Single Board Computer, which is a
member
of Intel's complete line of iSBC 80/86 computer
products,
is a complete computer system on a single
printed-circuit assembly. The iSBC 86/12 includes a
16-bit central processing unit (CPU), 32K bytes
of
dynamic RAM, a serial communications interface, three
programmable parallel I/O ports, programmable timers,
priority interrupt control, Multibus control logic, and bus
expansion drivers for interface with other Multibus-
compatible expansion boards. Also included is dual port
control logic to allow the iSBC 86/12 to act
as a slave
RAM device to other Multibus masters
in the system.
Provision is made for user installation
of up to 16K bytes
of read only memory.
1-2. DESCRIPTION
The iSBC 86/12 Single Board Computer (figure 1-1) is
controlledby an Intel 8086 16- Bit Microprocessor(CPU).
The 8086 CPU includes four 16-bitgeneral purpose regis-
ters that may also be addressed as eight 8-bit registers. In
(MULTIBUS)
CHAPTER 1
GENERAL INFORMATION
addition, the CPU contains two 16-bit pointer registers
and two 16-bit index registers. Four 16-bit segment regis-
ters allow extended addressing to a full megabyte of
memory. The CPU instruction set supports a wide range
of addressing modes and data transfer operations, signed
and unsigned 8-bit and 16-bit arithmetic including
hardware mUltiply and divide, and logical and string oper-
ations. The CPU architecture features dynamic code relo-
cation, reentrant code, and instruction lookahead.
The iSBC 86/12 has an internal bus for all on-board
memory and I/O operations and accesses the system bus
(Multibus) for all external memory and I/O operations.
Hence, local (on-board) operations do not involve the
Multibus, making the Multibus available for true parallel
processing when several bus masters (e.
g., DMA devices
and othersingle board computers) are used in a multimas-
ter scheme.
Dual port control logic
is included to interface the
dynamic RAM with the Multibus so that the iSBC 86/12
can function
as a slave RAM device when notin control of
the Multibus. The CPU has priority when accessing on-
board RAM. After the CPU completes its read or write
(AUXIUARy)
645-1 f4'igure 1-1. iSBC 86/12 Single Board Computer
1-1

General Information
operation, the controlling bus master is allowed to access
RAM and complete its operation. Where both the CPU
and the controlling bus master have the need to write or
read several bytes
or words to or from on-board RAM,
their operations ary interleaved. For CPU access, the
on-boardRAM addresses are assigned from the bottomup
of the I-megabyte address space; i.e., 0OOOO-07FFFH·
The slave RAM address decode logic includes jumpers
and switchers to allow partitioning the on-based RAM
into any 128K segment
of the 1- megabyte system address
space.
Theslave RAM canbeconfigured toalloweither8K, 16K
24K,
or 32K access by another bus master. Thus, the
RAM can be configured to allow other bus masters to
access a segment
of the on-board RAM and still reserve
another segment strictly for on-board use. The addressing
scheme accommodates both 16-bitand 20-bitaddressing.
Four IC sockets are included
to accommodate up to 16K
bytes
of user-installed read only memory. Configuration
jumpers allow read only memory to be installed in 2K,
4K, or 8K increments.
The iSBC 86/12 includes 24 programmable parallel I/O
lines implemented by means of an Intel 8255A Pro-
grammable Peripheral Interface (PPI). The system
software
is used to configure the I/O lines in any combina-
tion
of unidirectional input/output and bidirectional ports.
The I/O interface may be customized to meet specific
peripheral requirements and, in order to take full advan-
tage
of the large number of possible I/O configurations, IC
sockets are provided for interchangeable I/O line drivers
and terminators. Hence, the flexibility
of the parallel I/O
interface is furtherenhanced by the capability of selecting
the appropriate combination
of optional line drivers and
terminators'to provide the required sinkcurrent, polarity,
and drive/termination characteristics for each application.
The 24-programmable I/O ,lines and signal ground lines
are brought outto a 50-pin edge connector
(11) that mates
with flat, woven,
or round cable.
..
The RS232C compatible serial I/O port is controlled arid
interfaced by an Intel 8251A
US ART (Universal
Syncronous/Asynchrortous ReceiverlTransmitter) chip.
The USART
is individually programmable for operation
in most synchronous
or asynchronous serial data trans-
mission formats (including·iBM Bi-Sync).
In the synchronous mode the following are programma- .
ble:
a. Character length,
b. Sync character (or chlU1lcters), and
c. Parity.
1-2
iSBC 86/12
In the asynchronous mode the following are program-
mable:
a. Character length,
b. Baud rate factor (clockdivide ratios of 1, 16, or 64),
c. Stop bits, and
d. Parity.
In both the synchronous and asychronous modes, the
serial I/O port features half-
or full-duplex, double buf-
fered transmitand receive capability. In addition, USART
errordetection circuits can check for parity, overrun, and
framing errors. The USART transmit and receive clock
rates are supplied by a programmable baud rate/time
generator. These clocks may optionally be supplied from
an external source. The RS232C command lines, serial
data lines, and signal ground lines are brought out to a
50-pin edge connector (12) that mates with flat or round
cable.
Three independent, fully programmable 16-bit interval
timer/event counters are provided by an Intel 8253 Pro-
grammable Interval Timer (PIT). Each counteris capable
of operating in either BCD or binary modes; two of these
counters are available
to the systems designer to generate
accurate time intervals under software control. Routing
for the outputs and gate /trigger inputs
of two of these
counters may
be independently routed to the 8259A Prog-
rammable Interrupt Controller (PIC). The gate/trigger in-
puts
of the two counters may be routed to I/O terminators
associated with the 8255A PPI
or as input connections
from the 8255A PPI. The third counter is used as a
programmable baud rate generator for the serial
I/O port.
In utilizing the iSBC 86/12, the systems designer simply
configures, via software, each counter independently to
meet system requirements. Whenever a given time delay
or count
is needed, software commands to the 8253 PIT
select the desired function. The contents of each counter
may
be read at any time during system operation with
simple operations for event counting applications, and
special commands are included
~ that the contents of
each counter·can be read "on the fly".
TheiSBC 86/ 12 provides vectoring forbus vectored (BV)
~ruid non-bus vectored (NBY) interrupts. An on-board
In.tel 8259A Programmable Interrupt Controller (PIC)
handles up to eight NBV interrupts. By using external
PIC's slaved. to the on-board PIC (master), the interrupt
structure can be expanded to handle and resolve the prior-
ityof upto 64 BV sources.
The PIC, which can
be programmed to respond to edge-
sensitive
or level-sensitive inputs, treats each true input
signal condition as an interrupt request. After resolving
the interrupt priority, the PIC issues a single interrupt
request to the·CPU. Interrupt priorities are independently
programmable under software control. The program-
mable interrupt priority modes are:

iSBC 86/12
a. Fully Nested Priority. Each interrupt request has a
fixed priority: input 0
is highest, input 7 is lowest.
b. Auto-Rotating Priority. Each interrupt request has
equal priority. Each level, after receiving service,
becomes the lowest priority level until the next inter-
rupt occurs.
c. Specific priority. Software assigns lowest priority.
Priority of all other levels is in numerical sequence
based on lowest priority.
The CPU includes a non-maskable interrupt (NMI) and a
maskable interrupt (lNTR). The NMI interrupt
is intended
to be used for catastrophic events such as power outages
that require immediate action
of the CPU. The INTR
interrrupt
is driven by the 8259A PIC which, on demand,
provides an 8-bit identifier of the interrupting source. The
C~U multiplies the 8-bit identifier by four to derive a
pomter to the service routine for the interrupting device.
Interrupt requests may originate from
18 sources without
the necessity
of external hardware. Two jumper-
selectable interrupt requests can be automatically gener-
ated
by the Programmable Peripheral Interface (PPI)
when a byte of information is ready to be transferred to the
~086 CPU (i.e., input buffer is full) or a byte of informa-
tIOn has been transferred to a peripheral device (i.e.,
output buffer
is empty). Two jumper-selectable interrupt
requests can be automatically generated
by the US ART
when a character
is ready to be transferred to the 8086
CPU (i.e., receive channel buffer
is full) or when a
character
is ready to be transmitted (i.e., transmit channel
data buffer
is empty.) A jumper-selectable interrupt
request can be generated by two
of the programmable
counters and eight additional interrupt request lines are
ava.ilable to the userfordirect interfaces to user-designated
penpheraldevices via the Multibus. One interrupt request
line may be jumper routed directly from a peripheral via
th~ ~arallel VO driverlterminator section and one power
fall mterrupt may be input via auxiliary connector P2.
Th~ iSBC 86/12 includes the resources for supporting a
~anety of OEM system requirements. For those applica-
tIOns requiring additional processing capacity and the
benefits
of multiprocessing (Le., several CPU's and/or
controllers logically sharing systems tasks with com-
munication over the Multibus), the iSBC 86/12 provides
full bus arbitration control logic. This control logic allows
up to three bus masters (e.g., combination
of iSBC 86/12
DMA controller, diskette controller, etc.)
to share the
Multibus
in serial (daisy-chain) fashion or up to 16 bus
masters to share the Multibus using an external parallel
priority resolving network.
T~e Multibus arbitration logic operates synchronously
WIth the bus clock, which is derived either from the iSBC
86/12 or can be optionally generated by some other bus
master. Data, however,
is transferred via a handshake
between the controlling master and the addressed slave
module. This arrangement allows different speed control-
General Information
lers to share resources on the same bus,. and transfers via
~he bus proceed asynchronously. Thus, the transfer speed
IS dependent on transmitting and receiving devices only.
This design prevents slower master modules from being
handicapped in their attempts
to gain control of the bus,
but does not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious applica-
tions for the master-slave capabilities
of the bus are mul-
tiprocessor configurations, high-speed direct memory
access (DMA) operations, and high-speed peripheral
control, but are
by no means limited to these three.
1-3. SYSTEM SOFTWARE
DEVELOPMENT
The development cycle of iSBC 86/12 based products
may be significantly reduced using an Intel Intellec Mic-
rocomputerDevelopment System. The resident texteditor
and system monitor greatly simplify the design, develop-
~ent, and deb~g of iSBC system software. An optional
dIskette operatmg system provides a relocating loaderand
linkage editor, and a library manager.
Intel's high level programming language,
PUM86, is also
available
as a resident Intellec Microcomputer Develop-
ment System option.
PUM 86 provides the capability to
program
in a natural, algorithmic language andeliminates
the need
to manage register usage or allocate memory.
PUM 86 programs can be written in a much shorter time
than assembly language programs fora given application.
1-4. EQUIPMENT SUPPLIED
The following are supplied with the iSBC 86/12 Single
Board Computer:
a. Schematic diagram, dwg no. 2002259
b. Assembly drawing, dwg no. 1001801
1-5. EQUIPMENT REQUIRED
Because the iSBC 86/12 is designed to satisfy a variety of
applications, the user must purchase and install only those
components required to satisfy his particular needs. A list
of components required to configure all the intended ap-
plications
of the iSBC86/12 is provided in table 2-1.
1-6. SPECIFICATIONS
Specifications of the iSBC 86/12 Single Board Computer
are listed
in table 1-1.
1-3

General Information
WORD SIZE
Instruction:
Data
CYCLE TIME:
MEMORY CAPACITY
On-Board ROM/EPROM:
On-Board Dynamic RAM:
Off-Board Expansion:
MEMORY ADDRESSING
On-Board ROM/EPROM:
On-Board RAM:
(CPU Access)
On-Board RAM:
(Multibus Access)
SERIAL COMMUNICATIONS
Synchronous:
Asynchronous:
Sample Baud Rate:
1-4
Table 1-1. Specifications
8, 16, 24, or 32 bits.
8/16 bits.
iSBC 86/12
800 nanosecond forfastest executable instruction (assumes instruction is in the queue).
1.2 microseconds for fastest executable instruction (assumes instruction is not
in the
queue).
Up to 16K bytes; user installed in 1
K, 2K, or 4K byte increments.
32K bytes. Integrity maintained during power failure with user-furnished batteries.
Up to 1 megabyte of user-specified combination of RAM, ROM, and EPROM.
FFOOO-FFFFFH (using 2758 EPROM's),
FEOOO-FFFFFH (using 2316E ROM's or 2716 EPROM's), and
FCOOO-FFfFFH (using 2332 ROM's).
00000-07FFFH.
Jumpers and switches allow board to act as slave RAM device for access by another
bus master. Addresses may
be set within any 8K boundary of any 128K segment of the
1-megabytesystem addressspace. Accessisselectablefor
8K, 16K, 24K, or32K bytes.
5-, 6-, 7-,
or 8-bit characters.
Intemal; 1 or 2 sync characters.
Automatic sync insertion.
5-, 6-, 7-,
or 8-bit characters.
Break character generation.
1, 1 Y2, or 2 stop bits.
False start bit detection.
Frequency'
(kHz, Software Selectable)
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
Baud Rate (Hz)2
Synchronous Asynchronous
+16 +64
-9600 2400
-4800 1200
38400 2400 600
19200 1200 300
9600 600 150
4800 300 75
2400 150 -
1760 110 -
Notes: 1. Frequency selected by I/Owritesof appropriate 16-bitfrequency factorto
Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software-
programmable rates available. Anyfrequencyfrom 18.75Hzto 613.5kHz
maybe generated utilizingon-board crystal oscillatorand 16-bitProgram-
mable Interval T'imer (used here as frequency divider).

JSBC 86/12
General Information
Table 1-1. Specifications (Continued)
INTERVAl TIMER AND BAUD RATE
GENERATOR
Input Frequency (selectable):
Output Frequencies:
SYSTEM CLOCK (8086 CPU):
I/O ADDRESSING:
INTERFACE COMPATIBILITY
Serial I/O:
Parallel I/O:
INTERRUPTS:
COMPATIBLE CONNECTORS/CABLES:
ENVIRONMENTAL REQUIREMENTS
OperatingTemperature:
Relative Humidity:
PHYSICAl CHARACTERISTICS
Width:
Height:
Thickness:
Weight:
2.46 MHz ±0.1% (0.41
jLsec period nominal),
1.23 MHz ±0.1% (0.82
jLsec period nominal), and
153.6 kHz ±0.1% (6.5
jLsec period nominal).
Function Single Timer
Min. Max.
Real-Time
Interrupt
1.63 jLsec 427.1 msec
Interval
Rate
Generator 2.342
Hz 613.5 kHz
(Frequency)
5.0 MHz ±0.1%.
Dual Timers
(Two Timers Cascaded)
Min. Max.
466.5
3.26 jLsec
minutes
0.000036Hz 306.8 kHz
All communication to Parallel I/O and Serial I/O Ports, Timer, and InterruptControlier
is via read and write commands from on-board 8086 CPU. Refer to table 3-2.
EIA Standard RS232C signals provided and supported:
Clear to Send Receive Data
Data Set Ready SecondaryReceive Data*
Data Terminal Ready Secondary CTS*
Request to Send Transmit Clock*
Receive Clock Transmit Data
*Can support only one.
24 programmable lines (8 lines per port); one port indudes bidirectional bus driver.
IC sockets included for user installation of line drivers and/or I/O terminators as
required for interface ports. Refer to table 2-1.
8086 CPU includes non-maskable interrupt (NMI) and maskable interrupt (INTR).
NMI interrupt is provided for catastrophic event such as power failure; NMI vector
address is 00008. INTR interrupt is driven by on-board 8259A PIC, which provides
8-bitidentifierofinterruptingdevicetoCPU. CPUmultipliesidentifierbyfourtoderive
vector address. Jumpers select interrupts from 18 sources without necessity of
external hardware. PIC may be programmed to accommodate edge-sensitive
or
level-sensitive inputs.
Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-21 and
2-22 for recommended types and lengths of I/O cables.
To 90% without condensation.
30.48 cm (12.00 inches).
17.15 em (6.75 inches).
1.78 cm (0.7 inch).
539 gm (19 ounces).
1-5

General Information
iSBC 86/12
Table 1-1. Specifications (Continued)
POWER REQUIREMENTS:
1-6
CONFIGURATION VCC =
+5V±5%
VOO = +12V±5%
VBB = -5V±5%
VAA = -12V±5%
Without EPROM' 5.2A 350 rnA -40 rnA
RAM Only3 390 rnA 40 rnA 1.0 rnA -
With iSBC 53()4
5.2A 450 rnA -140 rnA
With 4K EPROMs 5.5A 450 rnA 140 rnA
(Using 2758) -
With 8K ROMS
6.1A 450 rnA 140 rnA
(Using 2316E) -
With 8K EPROMs 5.5A 450 rnA 140 rnA
(Using 2716) -
With 16K ROMS
5.4A 450 rnA 140 rnA
(Using 2332) -
Notes: 1. Does not include power for optional ROM/EPROM, 110 drivers, and 110 terminators.
2. Does not include power required for optional ROM/EPROM, 1/0 drivers, and 110 terminators.
3. RAM chips powered via auxiliary power bus.
4. Does not include power for optional ROM/EPROM,
110 drivers, and 110 terminators. Power for iSBC 530 is supplied
via serial port connector.
5. Includes power required for four ROM/EPROM chips, and 110 terminators installed for16 110 lines; all terminator
inputs low.

2-1. INTRODUCTION
This chapter provides instructions for the iSBC 86/12
Single Board Computer in the user-defined environment.
It is advisable that the contents
of Chapters 1 and 3 be
fully understood before beginning the configuration and
installation procedures provided in this chapter.
2-2. UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt for
evidence
of mishandling during transit. If the shipping
carton is severely damaged
or waterstained, request that
the carrier's agent be present when the carton
is opened.
If the carrier's agent is not present when the carton is
opened and the contents of the carton are damaged,
keep the carton and packing material for the agent's
inspection.
For repairs to a product damaged in shipment, contact
the Intel Technical Support Center (see paragraph 5-3)
to obtain a Return Authorization Number and further
instructions. A purchase order will be required to com-
plete the repair. A copy
of the purchase order should be
submitted to the carrier with your claim.
It is suggested that salvageable shipping cartons and pack-
ing material be saved for future use
in the event the pro-
duct must be reshipped.
2-3. INSTALLATION CONSIDERATIONS
The iSBC 86/12 is designed for use in one ofthe follow-
ing configurations:
a. Standalone
(single~board) system.
b. Bus master in a single bus master system.
c. Bus master in a multiple bus master system.
Important criteria for installing and interfacing the
iSBC 86/12 in these configurations are presented in
following paragraphs.
2-4. USER-FURNISHED COMPONENTS
The user-furnished components required to configure the
iSBC86/12 for a particular application are listed in table
2-1. Various types and vendors
of the connectors speci-
fied in table 2-1 are listed in table 2-2.
CHAPTER 2
PREPARATION FOR USE
2-5. POWER REQUIREMENT
The iSBC 86/12 requires +5V, -5V, + 12V, and -12V
power. The -5V power, which is required only for the
dual port RAM, can be supplied by the system
-5V
supply, an auxiliary battery, or by the on-board -5V
regulator. (The -5V regulator operates from the system
-12V supply.)
2-6. COOLING REQUIREMENT
The iSBC 86/12 dissipates 451 gram-calories/minute
(1.83 Btu/minute) and adequate circulation
of air must be
provided to prevent a temperature rise above 55°C
(131°F). The System 80 enclosures and the Intellec Sys-
tem includefans to provide adequate intake and exhaust of
ventilating air.
2-7. PHYSICAL DIMENSIONS
Physical dimensions of the iSBC 86/12 are as follows:
a. Width: 30.48 cm (12.00 inches).
b. Height:
c. Thickness:
17.15 cm (6.75 inches).
1.78
cm (0.70 inch).
2-8. COMPONENT INSTALLATION
Instructions for installing optional ROM/EPROM and
parallel I/O port line drivers and/or line terminators are
given in following paragraphs. When installing these chip
components, be sure to orient pin 1
of the chip adjacent
to the white dot located near pin 1
of the associated
IC socket. The grid zone location on figure 5-1 (pltrts
location diagram) is specified for each componentchip to
be installed.
2-9. ROM/EPROM CHIPS
IC sockets A28, A29, A46, and A47 (figure 5-1 zone C3)
accommodate 24-pin ROM/EPROM chips. Because the
CPUjumps to location FFFFO on a power up or reset, the
ROM/EPROM address space resides in the topmost por-
tion
of the I-megabyte address space and must be loaded
from the top down. IC sockets A29 and A47 accom-
modate the top
of the ROM/EPROM address space and
must always be loaded; IC sockets A28 and A46 accom-
modate the ROM/EPROM space directly below that in-
stalled in A29 and A47.
2-1

Preparation for Use
iSBC 86112
Table 2-1. User-Furnished and Installed Components
Item Item Description Use
No.
1
iSBC 604
Modular Backplane and Cardcage. In-
Provides power input pins and Multibus
cludes four
slots with bus terminators.
signal interface between iSBC 86/12 and
(See figure 5-3.) -
three additionalboards in amultiple board
system.
2
iSBC 614
Modular Backplane and Cardcage. In-
Provides four-slot extensionof iSBC 604.
cludes four slotswithout bus terminators.
(See figure 5-4.)
3 Connector
See Multibus Connector details in
Power inputs and Multibus signal inter-
(mates with P1)
table 2-2.
face. Not required if iSBC 86/12 is in-
stalled in an iSBC 6041614.
4
Connector
See Auxiliary Connector details in
Auxiliary backup
battery and asso-
(mates with P2)
table 2-2.
ciated memory protect functions.
5
Connector
See Parallel I/O Connector details in
Interfaces parallel I/O port with Intel8255A
(mates with J1)
table 2-2.
PPI.
6
Connector
See Serial I/O connector details in
Interfaces serial I/O port with Intel 8251A
(mates with J2)
table 2-2.
USART.
7
ROM/EPROM Chips
Two
or four each of the
following Ultraviolet Erasable PROM (EPROM) for
types:
development. Masked ROM for dedi-
cated program.
ROM
or EPROM
- 2758
2316E
2716
2332
-
8
Une Drivers
Type Current
Interface parallel I/O ports CA and CC with
Intel 8255A PPI. Requres two line driver
SN7403I,OC
16mA
IC's for each 8-bit parallel output port.
SN7400 I 16mA
SN7408 NI 16mA
SN7409 NI, OC
16mA
Types selected as typical; I = invert-
ing, NI = noninverting, and OC = open
collector.
9
Une Terminators
Intel iSBC 901 Divider or iSBC 902
Interface parallel"VO ports CA and CC with
Pull-Up:
Intel8255A PPI. Requires two901'sortwo
902'sfor
each 8-bit parallel input port.
+5V
iSBC 901
220
A
.& 330
iSBC 902
r:v
0 0
2-2

iSBC 86/12
Preparation for Use
Table 2-2. User-Furnished Connector Details
No. Of
Centers Connector
Intel
Function
Pairs/
(inches)
Type
Vendor
Vendor Part No.
Part No.
Pins
3M 3415-0000 WITH EARS
Parallel 3M 3415-0001 W/O EARS iSBC 956
I/O 25/50
0.1 Flat Crimp AMP 88083-1 Cable
Connector ANSLEY 609-5015 Set
SAE S06750 SERIES
Parallel AMP 2-583485-6
I/O 25/50
0.1 Soldered VIKING 3VH25/1JV5 N/A
Connector TI H312125
Parallel TI H311125
I/O . 24/50
0.1
Wirewrap' VIKING 3VH25/1JN05 N/A
COO
VPB01 B25000A1
Connector
ITICANNON EC4A050A1A
Serial 3M 3462-0001 iSBC 955
110 13/26
0.1 Flat Crimp AMP 88106-1 Cable
ANSLEY 609-2615
Connector SAE S06726 SERIES Set
Serial TI H312113
110
13/26
0.1
Soldered AMP 1-583485-5 N/A
Connector
Serial
110
13/26
0.1
Wi rew rap' TI H311113 N/A
Connector
COC3
VPB01 E43000A1
Multibus 43/86 0.156 Soldered' MICRO PLASTICS MP-0156-43-BW-4 N/A
Connector ARCO AE443WP1 LESS EARS
VIKING 2VH43/1AV5
Multibus
COO VFB01 E43000A1 or
:,
Connector 43/86 0.156
Wirewrap1.2
COC3
VPB01E43AooA1 MOS 985
VIKING 2VH43/1AV5
Auxiliary 30/60
0.1 Soldered' TI H312130 N/A
Connector VIKING 3VH30/1JN5
Auxiliary 30/60
0.1
Wirewrap1.2
COO VPB01 B30AOOA2
N/A
Connector TI H311130
NOTES:
1.
Connector heights are not guaranteed to conform to OEM packaging equipment.
2. Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment.
3.
COC VPB01 .... VPB02 .... VPB04 .... etc. are identical connectors with different electroplating thicknesses or
metal surfaces.
2-3

Preparation for Use
The low-order byte (bits 0-7) of ROM/EPROM must be
installed in sockets A29 and A28; the high-order byte
(bits 8-15) must
be installed in sockets A47 and A46.
Assuming that 2K bytes
of EPROM are to be installed
using two Intel 2758 chips, the chip containing the
low-order byte must
be installed in IC socket A29 and
the chip containing the high-order byte must
be installed
in IC socket A47. In this configuration, the usable
ROM/EPROM address space is FF800-FFFFF. Two ad-
ditional Intel 2758 chips may be installed later in IC
sockets A28 and A46 and occupy the address space
FFOOO-FF7FF. (Even addresses read the low-order bytes
and odd addresses read the high-order bytes.)
The default (factory connected) jumpers and switch S1
are configured for
2K by 8-bit ROM/EPROM chips
(e.g., two or four Intel 2716's). If different type chips
are installed, reconfigure the jumpers and switch S1
as
listed in table 2-4.
2-10. LINE DRIVERS AND I/O
TERMINATORS
Table 2-3 lists the I/O ports and the location of associated
14-pin
IC sockets for instaHing either line drivers or I/O
tenninators. (Refer to table 2-1 items 8 and 9.)
Port
C8 is factory equipped with Intel 8226 Bidirectional
Bus Drivers and requires
no additional components.
2-11. JUMPER/SWITCH CONFIGURATION
The iSBC :86/12 includes a variety of jumper- and switch-
selectable options to allow the user to configure the board
for his particular application. Table 2-4 summarizes these
options and lists the grid reference locations
of the
jumpers and switches
as shown in figure 5-1 (parts
location diagram) and figure 5-2 (schematic diagram).
Because the schematic dIagram consists
of 11 sheets, gria
iSBC 86/12
references to figure 5-2 may be either four or five alpha-
numeric characters. For exampfe, grid reference 3ZB7
signifies sheet 3 Zone B7.
Study table 2-4 carefully while making reference to fig-
ures 5-1 and 5-2. If the default (factory configured)
jumpers and switch settings are appropriate for a partic-
ular function,
no further action is required for that
function. If, however, a different configuration
is re-
quired, reconfigure the switch settings and/or remove the
default jumper(s) and install an optional jumper(s)
as
specified. For most options, the infonnation in table
2-4
is sufficient for proper configuration. Additional
information, where necessary for clarity,
is described
in subsequent paragraphs.
2-12. RAM ADDRESSES (MULTIBUS
ACCESS)
The dual port RAM can be shared with other bus masters
via the Multibus. One jumper wire connected between a
selected pair
of jumperposts (113 through 128) places the
dual port RAM
in one of eight 128K byte segments of the
I-megabyte address space. Switch S1
is a dual-inline
package (DIP) composed
of eight individual single-pole,
single-throw switches. (Two
of these individual switches
are used for ROM/EPROM configuration.) Two switches
(6-11 and 5-12) are configured
to allow 8K, 16K, 24K,
or 32K bytes
of dual port RAM to be accessed. Four
switches (1-16, 2-15, 3-14, and 4-13) are configured
to displace the addresses from the top of the selected
128K byte segment
of memory.
Figure
2-1 provides an example of 8K bytes of dual port
RAM being made accessible from the Multibus and how
the addresses are established. Note in figure 2-1 that the
Multibus accesses the dual port RAM from the top down.
Thus, as shown for
8K byte access via the Multibus,
the bottom
24Kbytes of the iSBC 86/12 on-board
RAM
is reserved strictly for on-board CPU access.
Table 2-3. Line Driver and I/O Terminator Locations
1/0 Port Bits DriverlTermlnator Fig.
5-1 Grid Ref. Fig. 5-2*Grid Ref.
C8 0-7 None Required --
8255A
CA
0-3 A12 lO4 9ZA3
PPI 4-7 A13 lO4 9ZA3
Interface
CC 0-3
A11 lO5 9lC3
4-7 A10 lO5
9lB3
*Figure 5-2 is the schematic diagram. Grid reference 9ZA3, for example, denotes sheet 9 lone A3.
2-4

i8BC 86/12
Preparation for Use
Table 2-4. Jumper and Switch Selectable Options
Function
Fig. 5-1 Fig. 5-2
Description
Grid Ref. Grid Ref.
ROM/EPROM ZC3, ZB6,
6ZB3,6ZC7,
Jumpers94through 99 and switch S1 maybe configured to accommodate
Configuration
ZD7 2ZB6 four types of ROM/EPROM chips:
ROM/EPROM
Switch S1
Jumpers
-- --
Type
8-9 7-10
2758 94-95, 97-98 C C
2316E/2716 *94-96, *97-98
*C *0
2332 94-96, 97-99 0 C
Reserved -0 0
C = closed switch position.
o = open switch position.
Default jumpers and switch settings accommodate Intel 2316E/2716
chips. Disconnect existing configuration jumpers (if necessary) and
reset switch
S1 if reconfiguration is required.
Dual Port RAM ZB7, ZB6
3ZB6,3ZB7
The dual port RAM permits access by the local (on-board) CPU and any
(Multibus Access) system bus mastervia the Multibus. Forlocal CPU access, the dual port
RAM address space is fixed beginning at location 00000. Foraccess via
the Multibus, one jumper and one switch can configure the dual port
RAM on any 8K boundary within the 1-megabyte address space. Refer
to paragraph 2-12 for configuration details.
Bus Clock
ZB7 10ZA2 Default jumper *105-106 routes Bus Clock signal BCLKI to the Multibus.
(Refer to table 2-9.) Remove this jumper only if another bus master
supplies this signal.
Constant Clock ZB7 10ZA2 Default jumper *103-104 routes Constant Clock signal CCLKI to the
Multibus. (Refer to table 2-9.) Remove this jumperonly if another bus
master supplies this signal.
Bus Priority Out
ZB7
3ZD2 Default jumper *151-152 routes Bus Priority
Out signal BPRO/ to the
Multibus. (Refer to table 2-9.) Remove this jumper only in those
systems employing a parallel priority bus resolution scheme. (Refer
to paragraph 2-19.)
Bus Arbitration ZBB, Zf)7
3ZD2,3ZC3
The Common.Bus Request signal (CBRO) trom the Multibus and the
ANYROST input to the Bus Arbiter chip are not presently used.
Auxiliary Backup ZD3, ZBB, 1ZC7,1ZCB Ifauxiliarybackupbatteriesare usedto sustainthedual port RAM
conter1'ts
Batteries ZB5
du~ng ac poweroutages, remove default jumpers *W4(A-B), *W5(A-B),
and *W6(A-B).
..
On-Board -5V
ZB6
1ZCB The dual port RAM requires a -5V AUX input, which can be supplied by
Regulator the system
-5V supply, an auxiliary backup battery, or bythe,on-board
-5V regulator. (The -5V regulator operates from the system -12V
supply.) If a system -5V supply is available and auxiliary backup bat-
teries are not used, disconnect default jumper *W5(A-B) and connect
jumper W5(B-C). If auxiliary backup batteries are used, disconnect de-
fault jumper *W5(A-B); do not connect W5(B-C).
Failsafe Timer ZD7 2ZB6 If the on-board CPU addresses either a system
or an on-board memory
or I/O device and that device does not return an acknowledge Signal,
the CPU will hang up in a wait state. A failsafe timer is triggered during
T1 ofevery machinecycle and, ifnot retriggeredwithin 6.2milliseconds,
the resultant time-out pulse can be used to allow the CPU to exit the
wait state. If this feature is desired, connect jumper 5-6.
*Default jumper connected at the factory.
2-5

Preparation for Use
iSBC 86/12
Table 2-4. Jumper and Switch Selectable Options (Continued)
Function
Fig. 5-1 Fig. 5-2
Description
Grid Ref. Grid Ref.
Timer Input Input frequencies to the 8253 Programmable Interval Timer are jumper
Frequency selectable as follows:
Counter 0 (TMRO INTR)
57-58: 153.6 kHz.
ZD3 7ZB5 *57-56: 1.23 MHz.
57-53: 2.46 MHz.
57-62: Extemal Clock to/from Port CC terminator/driver.
Counter 1
(TMR1 INTR)
*59-60: 153.6 kHz.
59-56: 1.23 MHz.
ZD3 7ZA5 *59-53: 2.46 MHz.
59-62: External Clock to/from Port CC terminator/driver.
59-61: Counter 0 output.
Jumper59-61 effectively connects Counter0 and Counter 1in series
in
which.the output of Counter 0 serves as the input clock to Counter 1.
This permits programming the clock rates to Counter 1and thus provide
longer TMR1 INTR intervals.
Counter 2 (8251 Baud Rate Clock)
55-58: 153.6 kHz.
ZD3 7ZB5 *55-54: 1.23 MHz.
55-53: 2.46 MHz.
55-62: External Clock to/from Port CC terminator/driver.
Priority Interrupts -Sheet 8 A jumper matrix provides a wide selection of interrupts to be interfaced
to the 8086 CPU and the Multibus. Refer to paragraph 2-13 for
configuration.
Serial I/O Port -Sheet 7 Jumpers posts 38 through 52 are used to configure the 8251A USARTas
Configuration described
in paragraph 2-14.
Parallel I/O Port -Sheet 9 Jumper posts 7 through 37 are used to configure the 8255A PPI as de-
Configuration scribed
in paragraph 2-15.
*Default jumper connected at the factory.
The configuration for 16K, 24K, or 32K access is done
in a similar manner. Always observe the IMPORTANT
note in figure 2-1 in that the address space intended
for Multibus access
of the dual port RAM must not
cross a 128K boundary.
which himdles up to eight vectored priority interrupts,
provides the capability to expand the number
of priority
interrupts by cascading each interrupt line with another
8259A PIC. Figure 2-2 shows
as an example the on~board
PIC (master) with two slave PIC'sinterfacedby the Multi-
bus. This .arrangement leaves the master PIC with six
inputs (IR2 through IR7) that can be used to handle the
various on-board interrupt functions.
If it is desired to reserve all the dual port RAM strictly
for local CPU access, connect jumper 112-114.
2-13. PRIORITY INTERRUPTS
Table 2-5 lists the source (from)iand destination (to) of the
priority interruptjumpermatrix shown in figure 5-2 sheet
8. The INTR
output'of the on-board Intel 8259A Pro-
grammable Interrupt Controller (PIC) is applied directly
to the INTR input
of the 8086 CPU. The on-board PIC,
2-6
The master/slave PIC arrangement illustrated in figure
2-2
is implemented by programming the master PIC to
handle IRO and IRI as bus vectored interrupt inputs. For
example,
if the Multibus INT3/line is driven low by slave
PIC
1, the master PIC will let slave PIC 1send the restart
address to the 8086 CPU.
Each interrupt input (IRO through IR7) to the master PIC
can be individually programmed to be a non-bus vectored
i I