Intel 80C186EB User manual

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
October 1995
COPYRIGHT ©INTEL CORPORATION, 1995
Order Number: 272433-004
80C186EB/80C188EB AND 80L186EB/80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
XFull Static Operation
XTrue CMOS Inputs and Outputs
YIntegrated Feature Set
Ð Low-Power Static CPU Core
Ð Two Independent UARTs each with
an Integral Baud Rate Generator
Ð Two 8-Bit Multiplexed I/O Ports
Ð Programmable Interrupt Controller
Ð Three Programmable 16-Bit
Timer/Counters
Ð Clock Generator
Ð Ten Programmable Chip Selects with
Integral Wait-State Generator
Ð Memory Refresh Control Unit
Ð System Level Testing Support (ONCE
Mode)
YDirect Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I/O
YSpeed Versions Available (5V):
Ð 25 MHz (80C186EB25/80C188EB25)
Ð 20 MHz (80C186EB20/80C188EB20)
Ð 13 MHz (80C186EB13/80C188EB13)
YAvailable in Extended Temperature
Range (b40§Ctoa
85§C)
YSpeed Versions Available (3V):
Ð 16 MHz (80L186EB16/80L188EB16)
Ð 13 MHz (80L186EB13/80L188EB13)
Ð 8 MHz (80L186EB8/80L188EB8)
YLow-Power Operating Modes:
Ð Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Ð Powerdown Mode Freezes All
Internal Clocks
YSupports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
YAvailable In:
Ð 80-Pin Quad Flat Pack (QFP)
Ð 84-Pin Plastic Leaded Chip Carrier
(PLCC)
Ð 80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.
272433–1

80C186EB/80C188EB and 80L186EB/80L188EB
16-Bit High-Integration Embedded Processors
CONTENTS PAGE
INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
CORE ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
80C186EC PERIPHERAL
ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
80C187 Interface (80C186EB Only) ÀÀÀÀÀÀÀÀÀ 7
ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
80C186EB PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
PACKAGE THERMAL
SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 23
Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
CONTENTS PAGE
Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 27
PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
AC CharacteristicsÐ80C186EB25 ÀÀÀÀÀÀÀÀÀ 28
AC CharacteristicsÐ80C186EB20/13 ÀÀÀÀÀ 30
AC CharacteristicsÐ80L186EB16 ÀÀÀÀÀÀÀÀÀ 32
Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 53
ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
2

80C186EB/80C188EB, 80L186EB/80L188EB
272433–2
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB
Figure 1. 80C186EB/80C188EB Block Diagram
3

80C186EB/80C188EB, 80L186EB/80L188EB
INTRODUCTION
Unless specifically noted, all references to the
80C186EB apply to the 80C188EB, 80L186EB, and
80L188EB. References to pins that differ between
the 80C186EB/80L186EB and the 80C188EB/
80L188EB are given in parentheses. The ‘‘L’’ in the
part number denotes low voltage operation. Physi-
cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are
identical.
The 80C186EB is the first product in a new genera-
tion of low-power, high-integration microprocessors.
It enhances the existing 186 family by offering new
features and new operating modes. The 80C186EB
is object code compatible with the 80C186XL/
80C188XL microprocessors.
The 80L186EB is the 3V version of the 80C186EB.
The 80L186EB is functionally identical to the
80C186EB embedded processor. Current
80C186EB users can easily upgrade their designs to
use the 80L186EB and benefit from the reduced
power consumption inherent in 3V operation.
The feature set of the 80C186EB meets the needs
of low power, space critical applications. Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals as well as
low voltage operation. Minimum current consump-
tion is achieved by providing a Powerdown mode
that halts operation of the device, and freezes the
clock circuits. Peripheral design enhancements en-
sure that non-initialized peripherals consume little
current.
Space critical applications benefit from the inte-
gration of commonly used system peripherals. Two
serial channels are provided for services such as
diagnostics, inter-processor communication, modem
interface, terminal display interface, and many oth-
ers. A flexible chip select unit simplifies memory and
peripheral interfacing. The interrupt unit provides
sources for up to 129 external interrupts and will pri-
oritize these interrupts with those generated from
the on-chip peripherals. Three general purpose tim-
er/counters and sixteen multiplexed I/O port pins
round out the feature set of the 80C186EB.
Figure 1 shows a block diagram of the 80C186EB/
80C188EB. The Execution Unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions,
string move instructions that operate at full bus
bandwidth, ten new instruction, and fully static oper-
ation. The Bus Interface Unit (BIU) is the same as
that found on the original 186 family products, ex-
cept the queue status mode has been deleted and
buffer interface control has been changed to ease
system design timings. An independent internal bus
is used to allow communication between the BIU
and internal peripherals.
CORE ARCHITECTURE
Bus Interface Unit
The 80C186EB core incorporates a bus controller
that generates local bus control signals. In addition,
it employs a HOLD/HLDA protocol to share the local
bus with other bus masters.
The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information, and data (for write operations) in-
formation. It is also responsible for reading data off
the local bus during a read operation. A READY in-
put pin is provided to extend a bus cycle beyond the
minimum four states (clocks).
The local bus controller also generates two control
signals (DEN and DT/R) when interfacing to exter-
nal transceiver chips. (Both DEN and DT/R are
available on the PLCC devices, only DEN is avail-
able on the QFP and SQFP devices.) This capability
allows the addition of transceivers for simple buffer-
ing of the multiplexed address/data bus.
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide-
by-two counter, and two low-power operating
modes.
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network. Alternatively, the oscilla-
tor circuit may be driven from an external clock
source. Figure 2 shows the various operating modes
of the oscillator circuit.
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter. This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components. All AC timings are referenced to
CLKOUT.
4

80C186EB/80C188EB, 80L186EB/80L188EB
272433–3
(A) Crystal Connection
NOTE:
The L1C1network is only required when using a third-
overtone crystal.
272433–4
(B) Clock Connection
Figure 2. Clock Configurations
The following parameters are recommended when
choosing a crystal:
Temperature Range: Application Specific
ESR (Equivalent Series Resistance): 40Xmax
C0 (Shunt Capacitance of Crystal): 7.0 pF max
CL(Load Capacitance): 20 pF g2pF
Drive Level: 1 mW max
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact, yet powerful system. The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e.g., the
interrupt control unit supports interrupt requests
from the timer/counters or serial channels).
The list of integrated peripherals includes:
#7-Input Interrupt Control Unit
#3-Channel Timer/Counter Unit
#2-Channel Serial Communications Unit
#10-Output Chip-Select Unit
#I/O Port Unit
#Refresh Control Unit
#Power Management Unit
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB). The PCB
can be located in either memory or I/O space on
any 256 Byte address boundary.
Figure 3 provides a list of the registers associated
with the PCB. The Register Bit Summary at the end
of this specification individually lists all of the regis-
ters and identifies each of their programming attri-
butes.
Interrupt Control Unit
The 80C186EB can receive interrupts from a num-
ber of sources, both internal and external. The inter-
rupt control unit serves to merge these requests on
a priority basis, for individual service by the CPU.
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU.
Internal interrupt sources include the Timers and Se-
rial channel 0. External interrupt sources come from
the five input pins INT4:0. The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU. Although the Timer and Serial channel
each have only one request input to the ICU, sepa-
rate vector types are generated to service individual
interrupts within the Timer and Serial channel units.
Timer/Counter Unit
The 80C186EB Timer/Counter Unit (TCU) provides
three 16-bit programmable timers. Two of these are
highly flexible and are connected to external pins for
control or clocking. A third timer is not connected to
any external pins and can only be clocked internally.
However, it can be used to clock the other two timer
channels. The TCU can be used to count external
events, time external events, generate non-repeti-
tive waveforms, generate timed interrupts. etc.
5

80C186EB/80C188EB, 80L186EB/80L188EB
PCB Function
Offset
00H Reserved
02H End Of Interrupt
04H Poll
06H Poll Status
08H Interrupt Mask
0AH Priority Mask
0CH In-Service
0EH Interrupt Request
10H Interrupt Status
12H Timer Control
14H Serial Control
16H INT4 Control
18H INT0 Control
1AH INT1 Control
1CH INT2 Control
1EH INT3 Control
20H Reserved
22H Reserved
24H Reserved
26H Reserved
28H Reserved
2AH Reserved
2CH Reserved
2EH Reserved
30H Timer0 Count
32H Timer0 Compare A
34H Timer0 Compare B
36H Timer0 Control
38H Timer1 Count
3AH Timer1 Compare A
3CH Timer1 Compare B
3EH Timer1 Control
PCB Function
Offset
40H Timer2 Count
42H Timer2 Compare
44H Reserved
46H Timer2 Control
48H Reserved
4AH Reserved
4CH Reserved
4EH Reserved
50H Port 1 Direction
52H Port 1 Pin
54H Port 1 Control
56H Port 1 Latch
58H Port 2 Direction
5AH Port 2 Pin
5CH Port 2 Control
5EH Port 2 Latch
60H Serial0 Baud
62H Serial0 Count
64H Serial0 Control
66H Serial0 Status
68H Serial0 RBUF
6AH Serial0 TBUF
6CH Reserved
6EH Reserved
70H Serial1 Baud
72H Serial1 Count
74H Serial1 Control
76H Serial1 Status
78H Serial1 RBUF
7AH Serial1 TBUF
7CH Reserved
7EH Reserved
PCB Function
Offset
80H GCS0 Start
82H GCS0 Stop
84H GCS1 Start
86H GCS1 Stop
88H GCS2 Start
8AH GCS2 Stop
8CH GCS3 Start
8EH GCS3 Stop
90H GCS4 Start
92H GCS4 Stop
94H GCS5 Start
96H GCS5 Stop
98H GCS6 Start
9AH GCS6 Stop
9CH GCS7 Start
9EH GCS7 Stop
A0H LCS Start
A2H LCS Stop
A4H UCS Start
A6H UCS Stop
A8H Relocation
AAH Reserved
ACH Reserved
AEH Reserved
B0H Refresh Base
B2H Refresh Time
B4H Refresh Control
B6H Reserved
B8H Power Control
BAH Reserved
BCH Step ID
BEH Reserved
PCB Function
Offset
C0H Reserved
C2H Reserved
C4H Reserved
C6H Reserved
C8H Reserved
CAH Reserved
CCH Reserved
CEH Reserved
D0H Reserved
D2H Reserved
D4H Reserved
D6H Reserved
D8H Reserved
DAH Reserved
DCH Reserved
DEH Reserved
E0H Reserved
E2H Reserved
E4H Reserved
E6H Reserved
E8H Reserved
EAH Reserved
ECH Reserved
EEH Reserved
F0H Reserved
F2H Reserved
F4H Reserved
F6H Reserved
F8H Reserved
FAH Reserved
FCH Reserved
FEH Reserved
Figure 3. Peripheral Control Block Registers
6

80C186EB/80C188EB, 80L186EB/80L188EB
Serial Communications Unit
The Serial Control Unit (SCU) of the 80C186EB con-
tains two independent channels. Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin). Each
channel has its own baud rate generator that is in-
dependent of the Timer/Counter Unit, and can be
internally or externally clocked at up to one half the
80C186EB operating frequency.
Independent baud rate generators are provided for
each of the serial channels. For the asynchronous
modes, the generator supplies an 8x baud clock to
both the receive and transmit register logic. A 1x
baud clock is provided in the synchronous mode.
Chip-Select Unit
The 80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip-
selects to access both memories and peripherals. In
addition, each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically termi-
nate a bus cycle independent of the condition of the
READY input pin.
I/O Port Unit
The I/O Port Unit (IPU) on the 80C186EB supports
two 8-bit channels of input, output, or input/output
operation. Port 1 is multiplexed with the chip select
pins and is output only. Most of Port 2 is multiplexed
with the serial channel pins. Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with.
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed. A 9-bit
counter controls the number of clocks between re-
fresh requests.
A 12-bit address generator is maintained by the RCU
and is presented on the A12:1 address lines during
the refresh bus cycle. Address bits A19:13 are pro-
grammable to allow the refresh address block to be
located on any 8 Kbyte boundary.
Power Management Unit
The 80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides three power modes: Ac-
tive, Idle, and Powerdown.
Active Mode indicates that all units on the
80C186EB are functional and the device consumes
maximum power (depending on the level of periph-
eral operation). Idle Mode freezes the clocks of the
Execution and Bus units at a logic zero state (all
peripherals continue to operate normally).
The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
All internal registers hold their values provided VCC
is maintained. Current consumption is reduced to
just transistor junction leakage.
80C187 Interface (80C186EB Only)
The 80C186EB (PLCC package only) supports the
direct connection of the 80C187 Numerics Coproc-
essor.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EB has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’. The
ONCE mode is selected by forcing the A19/ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN is ac-
tive.
7

80C186EB/80C188EB, 80L186EB/80L188EB
PACKAGE INFORMATION
This section describes the pins, pinouts, and thermal
characteristics for the 80C186EB in the Plastic
Leaded Chip Carrier (PLCC) package, Shrink Quad
Flat Pack (SQFP), and Quad Flat Pack (QFP) pack-
age. For complete package specifications and infor-
mation, see the Intel Packaging Outlines and Dimen-
sions Guide (Order Number: 231369).
Prefix Identification
With the extended temperature range, operational
characteristics are guaranteed over the temperature
range corresponding to b40§Ctoa
85§C ambient.
Package types are identified by a two-letter prefix to
the part number. The prefixes are listed in Table 1.
Table 1. Prefix Identification
Prefix Note Package Temperature
Type Type
TN PLCC Extended
TS QFP (EIAJ) Extended
SB 1 SQFP Extended/Commercial
N 1 PLCC Commercial
S 1 QFP (EIAJ) Commercial
NOTE:
1. The 5V 25 MHz and 3V 16 MHz versions are only avail-
able in commercial temperature range corresponding to
0§Ctoa
70§C ambient.
Pin Descriptions
Each pin or logical set of pins is described in Table
3. There are three columns for each entry in the Pin
Description Table.
The Pin Name column contains a mnemonic that
describes the pin function. Negation of the signal
name (for example, RESIN) denotes a signal that is
active low.
The Pin Type column contains two kinds of informa-
tion. The first symbol indicates whether a pin is pow-
er (P), ground (G), input only (I), output only (O) or
input/output (I/O). Some pins have multiplexed
functions (for example, A19/S6). Additional symbols
indicate additional characteristics for each pin. Table
2 lists all the possible symbols for this column.
The Input Type column indicates the type of input
(Asynchronous or Synchronous).
Asynchronous pins require that setup and hold times
be met only in order to guarantee
recognition at a
particular clock edge. Synchronous pins require that
setup and hold times be met to guarantee proper
operation. For example, missing the setup or hold
time for the SRDY pin (a synchronous input) will re-
sult in a system failure or lockup. Input pins may also
be edge- or level-sensitive. The possible character-
istics for input pins are S(E), S(L), A(E) and A(L).
The Output States column indicates the output
state as a function of the device operating mode.
Output states are dependent upon the current activi-
ty of the processor. There are four operational
states that are different from regular operation: bus
hold, reset, Idle Mode and Powerdown Mode. Ap-
propriate characteristics for these states are also in-
dicated in this column, with the legend for all possi-
ble characteristics in Table 2.
The Pin Description column contains a text de-
scription of each pin.
As an example, consider AD15:0. I/O signifies the
pins are bidirectional. S(L) signifies that the input
function is synchronous and level-sensitive. H(Z)
signifies that, as outputs, the pins are high-imped-
ance upon acknowledgement of bus hold. R(Z) sig-
nifies that the pins float during reset. P(X) signifies
that the pins retain their states during Powerdown
Mode.
8

80C186EB/80C188EB, 80L186EB/80L188EB
Table 2. Pin Description Nomenclature
Symbol Description
P Power Pin (Apply aVCC Voltage)
G Ground (Connect to VSS)
I Input Only Pin
O Output Only Pin
I/O Input/Output Pin
S(E) Synchronous, Edge Sensitive
S(L) Synchronous, Level Sensitive
A(E) Asynchronous, Edge Sensitive
A(L) Asynchronous, Level Sensitive
H(1) Output Driven to VCC during Bus Hold
H(0) Output Driven to VSS during Bus Hold
H(Z) Output Floats during Bus Hold
H(Q) Output Remains Active during Bus Hold
H(X) Output Retains Current State during Bus Hold
R(WH) Output Weakly Held at VCC during Reset
R(1) Output Driven to VCC during Reset
R(0) Output Driven to VSS during Reset
R(Z) Output Floats during Reset
R(Q) Output Remains Active during Reset
R(X) Output Retains Current State during Reset
I(1) Output Driven to VCC during Idle Mode
I(0) Output Driven to VSS during Idle Mode
I(Z) Output Floats during Idle Mode
I(Q) Output Remains Active during Idle Mode
I(X) Output Retains Current State during Idle Mode
P(1) Output Driven to VCC during Powerdown Mode
P(0) Output Driven to VSS during Powerdown Mode
P(Z) Output Floats during Powerdown Mode
P(Q) Output Remains Active during Powerdown Mode
P(X) Output Retains Current State during Powerdown Mode
9

80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions
Pin Pin Input Output Description
Name Type Type States
VCC PÐ ÐPOWER connections consist of four pins which must be
shorted externally to a VCC board plane.
VSS GÐ ÐGROUND connections consist of six pins which must be
shorted externally to a VSS board plane.
CLKIN I A(E) Ð CLocK INput is an input for an external clock. An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN. For crystal
operation, CLKIN (along with OSCOUT) are the crystal
connections to an internal Pierce oscillator.
OSCOUT O Ð H(Q) OSCillator OUTput is only used when using a crystal to
generate the external clock. OSCOUT (along with CLKIN)
R(Q)
are the crystal connections to an internal Pierce oscillator.
P(Q) This pin is not to be used as 2X clock output for non-crystal
applications (i.e., this pin is N.C. for non-crystal applications).
OSCOUT does not float in ONCE mode.
CLKOUT O Ð H(Q) CLocK OUTput provides a timing reference for inputs and
outputs of the processor, and is one-half the input clock
R(Q)
(CLKIN) frequency. CLKOUT has a 50% duty cycle and
P(Q) transistions every falling edge of CLKIN.
RESIN I A(L) Ð RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state. All
pins will be driven to a known state, and RESOUT will also
be driven active. The rising edge (low-to-high) transition
synchronizes CLKOUT with CLKIN before the processor
begins fetching opcodes at memory location 0FFFF0H.
RESOUT O Ð H(0) RESet OUTput that indicates the processor is currently in
the reset state. RESOUT will remain active as long as RESIN
R(1)
remains active.
P(0)
PDTMR I/O A(L) H(WH) Power-Down TiMeR pin (normally connected to an external
capacitor) that determines the amount of time the processor
R(Z)
waits after an exit from power down before resuming normal
P(1) operation. The duration of time required will depend on the
startup characteristics of the crystal oscillator.
NMI I A(E) Ð Non-Maskable Interrupt input causes a TYPE-2 interrupt to
be serviced by the CPU. NMI is latched internally.
TEST/BUSY I A(E) Ð TEST is used during the execution of the WAIT instruction to
suspend CPU operation until the pin is sampled active
(TEST)
(LOW). TEST is alternately known as BUSY when interfacing
with an 80C187 numerics coprocessor (80C186EB only).
AD15:0 I/O S(L) H(Z) These pins provide a multiplexed Address and Data bus.
During the address phase of the bus cycle, address bits 0
(AD7:0) R(Z)
through 15 (0 through 7 on the 80C188EB) are presented on
P(X) the bus and can be latched using ALE. 8- or 16-bit data
information is transferred during the data phase of the bus
cycle.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
10

80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin Pin Input Output Description
Name Type Type States
A18:16 I/O A(L) H(Z) These pins provide multiplexed Address during the address
phase of the bus cycle. Address bits 16 through 19 are presented
A19/ONCE R(WH)
on these pins and can be latched using ALE. These pins are
(A15:A8) P(X) driven to a logic 0 during the data phase of the bus cycle. On the
(A18:16) 80C188EB, A15– A8 provide valid address information for the
(A19/ONCE) entire bus cycle. During a processor reset (RESIN active), A19/
ONCE is used to enable ONCE mode. A18:16 must not be driven
low during reset or improper operation may result.
S2:0 O Ð H(Z) Bus cycle Status are encoded on these pins to provide bus
transaction information. S2:0 are encoded as follows:
R(Z)
P(1) S2 S1 S0 Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)
ALE O Ð H(0) Address Latch Enable output is used to strobe address
information into a transparent type latch during the address phase
R(0)
of the bus cycle.
P(0)
BHE O Ð H(Z) Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus. BHE and
(RFSH) R(Z)
A0 have the following logical encoding
P(X)
A0 BHE Encoding (for the 80C186EB/80L186EB only)
0 0 Word Transfer
0 1 Even Byte Transfer
1 0 Odd Byte Transfer
1 1 Refresh Operation
On the 80C188EB/80L188EB, RFSH is asserted low to indicate a
refresh bus cycle.
RD O Ð H(Z) ReaD output signals that the accessed memory or I/O device
must drive data information onto the data bus.
R(Z)
P(1)
WR O Ð H(Z) WRite output signals that data available on the data bus are to be
written into the accessed memory or I/O device.
R(Z)
P(1)
READY I A(L) Ð READY input to signal the completion of a bus cycle. READY
must be active to terminate any bus cycle, unless it is ignored by
S(L)
correctly programming the Chip-Select Unit.
DEN O Ð H(Z) Data ENable output to control the enable of bi-directional
transceivers in a buffered system. DEN is active only when data is
R(Z)
to be transferred on the bus.
P(1)
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
11

80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin Pin Input Output Description
Name Type Type States
DT/R O Ð H(Z) Data Transmit/Receive output controls the direction of a
bi-directional buffer in a buffered system. DT/R is only
R(Z)
available for the PLCC package.
P(X)
LOCK O Ð H(Z) LOCK output indicates that the bus cycle in progress is not
to be interrupted. The processor will not service other bus
R(WH)
requests (such as HOLD) while LOCK is active. This pin is
P(1) configured as a weakly held high input while RESIN is
active and must not be driven low.
HOLD I A(L) Ð HOLD request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix.
HLDA O Ð H(1) HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus. When HLDA is
R(0)
asserted, the processor will (or has) floated its data bus
P(0) and control signals allowing another bus master to drive the
signals directly.
NCS O Ð H(1) Numerics Coprocessor Select output is generated when
accessing a numerics coprocessor. NCS is not provided on
(N.C.) R(1)
the QFP or SQFP packages. This signal does not exist on
P(1) the 80C188EB/80L188EB.
ERROR I A(L) Ð ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition. An interrupt
(N.C.)
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation. ERROR is not provided
on the QFP or SQFP packages. This signal does not exist
on the 80C188EB/80L188EB.
PEREQ I A(L) Ð CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
(N.C.)
pending. PEREQ is not provided on the QFP or SQFP
packages. This signal does not exist on the 80C188EB/
80L188EB.
UCS O Ð H(1) Upper Chip Select will go active whenever the address of
a memory or I/O bus cycle is within the address limitations
R(1)
programmed by the user. After reset, UCS is configured to
P(1) be active for memory accesses between 0FFC00H and
0FFFFFH.
LCS O Ð H(1) Lower Chip Select will go active whenever the address of
a memory bus cycle is within the address limitations
R(1)
programmed by the user. LCS is inactive after a reset.
P(1)
P1.0/GCS0 O Ð H(X)/H(1) These pins provide a multiplexed function. If enabled, each
pin can provide a Generic Chip Select output which will go
P1.1/GCS1 R(1)
active whenever the address of a memory or I/O bus cycle
P1.2/GCS2 P(X)/P(1) is within the address limitations programmed by the user.
P1.3/GCS3 When not programmed as a Chip-Select, each pin may be
P1.4/GCS4 used as a general purpose output Port. As an output port
P1.5/GCS5 pin, the value of the pin can be read internally.
P1.6/GCS6
P1.7/GCS7
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
12

80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin Pin Input Output Description
Name Type Type States
T0OUT O Ð H(Q) Timer OUTput pins can be programmed to provide a
single clock or continuous waveform generation,
T1OUT R(1)
depending on the timer mode selected.
P(Q)
T0IN I A(L) Ð Timer INput is used either as clock or control signals,
depending on the timer mode selected.
T1IN A(E)
INT0 I A(E,L) Ð Maskable INTerrupt input will cause a vector to a
specific Type interrupt routine. To allow interrupt
INT1
expansion, INT0 and/or INT1 can be used with
INT4 INTA0 and INTA1 to interface with an external slave
controller.
INT2/INTA0 I/O A(E,L) H(1) These pins provide a multiplexed function. As inputs,
they provide a maskable INTerrupt that will cause
INT3/INTA1 R(Z)
the CPU to vector to a specific Type interrupt routine.
P(1) As outputs, each is programmatically controlled to
provide an INTERRUPT ACKNOWLEDGE
handshake signal to allow interrupt expansion.
P2.7 I/O A(L) H(X) BI-DIRECTIONAL, open-drain Port pins.
P2.6 R(Z)
P(X)
CTSO I A(L) Ð Clear-To-Send input is used to prevent the
transmission of serial data on their respective TXD
P2.4/CTS1
signal pin. CTS1 is multiplexed with an input only port
function.
TXD0 O Ð H(X)/H(Q) Transmit Data output provides serial data
information. TXD1 is multiplexed with an output only
P2.1/TXD1 R(1)
Port function. During synchronous serial
P(X)/P(Q) communications, TXD will function as a clock output.
RXD0 I/O A(L) R(Z) Receive Data input accepts serial data information.
RXD1 is multiplexed with an input only Port function.
P2.0/RXD1 H(Q)
During synchronous serial communications, RXD is
P(X) bi-directional and will become an output for
transmission or data (TXD becomes the clock).
P2.5/BCLK0 I A(L)/A(E) Ð Baud CLocK input can be used as an alternate clock
source for each of the integrated serial channels.
P2.2/BCLK1
BCLKx is multiplexed with an input only Port function,
and cannot exceed a clock rate greater than one-half
the operating frequency of the processor.
P2.3/SINT1 O Ð H(X)/H(Q) Serial INTerrupt output will go active to indicate
serial channel 1 requires service. SINT1 is
R(0)
multiplexed with an output only Port function.
P(X)/P(X)
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
13

80C186EB/80C188EB, 80L186EB/80L188EB
80C186EB PINOUT
Tables 4 and 5 list the 80C186EB/80C188EB pin
names with package location for the 84-pin Plastic
Leaded Chip Carrier (PLCC) component. Figure 5
depicts the complete 80C186EB/80C188EB pinout
(PLCC package) as viewed from the top side of the
component (i.e., contacts facing down).
Tables 6 and 7 list the 80C186EB/80C188EB pin
names with package location for the 80-pin Quad
Flat Pack (QFP) component. Figure 6 depicts the
complete 80C186EB/80C188EB (QFP package) as
viewed from the top side of the component (i.e., con-
tacts facing down).
Tables 8 and 9 list the 80186EB/80188EB pin
names with package location for the 80-pin Shrink
Quad Flat Pack (SQFP) component. Figure 7 depicts
the complete 80C186EB/80C188EB (SQFP pack-
age) as viewed from the top side of the component
(i.e., contacts facing down).
Table 4. PLCC Pin Names with Package Location
Address/Data Bus
Name Location
AD0 61
AD1 66
AD2 68
AD3 70
AD4 72
AD5 74
AD6 76
AD7 78
AD8 (A8) 62
AD9 (A9) 67
AD10 (A10) 69
AD11 (A11) 71
AD12 (A12) 73
AD13 (A13) 75
AD14 (A14) 77
AD15 (A15) 79
A16 80
A17 81
A18 82
A19/ONCE 83
Bus Control
Name Location
ALE 6
BHE (RFSH)7
S0 10
S1 9
S2 8
RD 4
WR 5
READY 18
DEN 11
DT/R 16
LOCK 15
HOLD 13
HLDA 12
Power
Name Location
VSS 2, 22, 43
63, 65, 84
VCC 1, 23
42, 64
Processor Control
Name Location
RESIN 37
RESOUT 38
CLKIN 41
OSCOUT 40
CLKOUT 44
TEST/BUSY 14
NCS (N.C.) 60
PEREQ (N.C.) 39
ERROR (N.C.) 3
PDTMR 36
NMI 17
INT0 31
INT1 32
INT2/INTA0 33
INT3/INTA1 34
INT4 35
I/O
Name Location
UCS 30
LCS 29
P1.0/GCS0 28
P1.1/GCS1 27
P1.2/GCS2 26
P1.3/GCS3 25
P1.4/GCS4 24
P1.5/GCS5 21
P1.6/GCS6 20
P1.7/GCS7 19
T0OUT 45
T0IN 46
T1OUT 47
T1IN 48
RXD0 53
TXD0 52
P2.5/BCLK0 54
CTS0 51
P2.0/RXD1 57
P2.1/TXD1 58
P2.2/BCLK1 59
P2.3/SINT1 55
P2.4/CTS1 56
P2.6 50
P2.7 49
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
14

80C186EB/80C188EB, 80L186EB/80L188EB
Table 5. PLCC Package Locations with Pin Name
Location Name
1V
CC
2V
SS
3 ERROR (N.C.)
4RD
5WR
6 ALE
7 BHE (RFSH)
8S2
9S1
10 S0
11 DEN
12 HLDA
13 HOLD
14 TEST/BUSY
15 LOCK
16 DT/R
17 NMI
18 READY
19 P1.7/GCS7
20 P1.6/GCS6
21 P1.5/GCS5
Location Name
22 VSS
23 VCC
24 P1.4/GCS4
25 P1.3/GCS3
26 P1.2/GCS2
27 P1.1/GCS1
28 P1.0/GCS0
29 LCS
30 UCS
31 INT0
32 INT1
33 INT2/INTA0
34 INT3/INTA1
35 INT4
36 PDTMR
37 RESIN
38 RESOUT
39 PEREQ (N.C.)
40 OSCOUT
41 CLKIN
42 VCC
Location Name
43 VSS
44 CLKOUT
45 T0OUT
46 T0IN
47 T1OUT
48 T1IN
49 P2.7
50 P2.6
51 CTS0
52 TXD0
53 RXD0
54 P2.5/BCLK0
55 P2.3/SINT1
56 P2.4/CTS1
57 P2.0/RXD1
58 P2.1/TXD1
59 P2.2/BCLK1
60 NCS (N.C.)
61 AD0
62 AD8 (A8)
63 VSS
Location Name
64 VCC
65 VSS
66 AD1
67 AD9 (A9)
68 AD2
69 AD10 (A10)
70 AD3
71 AD11 (A11)
72 AD4
73 AD12 (A12)
74 AD5
75 AD13 (A13)
76 AD6
77 AD14 (A14)
78 AD7
79 AD15 (A15)
80 A16
81 A17
82 A18
83 A19/ONCE
84 VSS
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
15

80C186EB/80C188EB, 80L186EB/80L188EB
272433–5
NOTE:
This is the FPO number location (indicated by X’s).
Pin names in parentheses apply to the 80C188EB/80L188EB.
Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram
16

80C186EB/80C188EB, 80L186EB/80L188EB
Table 6. QFP Pin Name with Package Location
Address/Data Bus
Name Location
AD0 10
AD1 15
AD2 17
AD3 19
AD4 21
AD5 23
AD6 25
AD7 27
AD8 (A8) 11
AD9 (A9) 16
AD10 (A10) 18
AD11 (A11) 20
AD12 (A12) 22
AD13 (A13) 24
AD14 (A14) 26
AD15 (A15) 28
A16 29
A17 30
A18 31
A19/ONCE 32
Bus Control
Name Location
ALE 38
BHE (RFSH)39
S0 42
S1 41
S2 40
RD 36
WR 37
READY 49
DEN 43
LOCK 47
HOLD 45
HLDA 44
Power
Name Location
VSS 12, 14, 33
35, 53, 73
VCC 13, 34
54, 72
Processor Control
Name Location
RESIN 68
RESOUT 69
CLKIN 71
OSCOUT 70
CLKOUT 74
TEST 46
PDTMR 67
NMI 48
INT0 62
INT1 63
INT2/INTA0 64
INT3/INTA1 65
INT4 66
I/O
Name Location
UCS 61
LCS 60
P1.0/GCS0 59
P1.1/GCS1 58
P1.2/GCS2 57
P1.3/GCS3 56
P1.4/GCS4 55
P1.5/GCS5 52
P1.6/GCS6 51
P1.7/GCS7 50
T0OUT 75
T0IN 76
T1OUT 77
T1IN 78
RXD0 3
TXD0 2
P2.5/BCLK0 4
CTS0 1
P2.0/RXD1 7
P2.1/TXD1 8
P2.2/BCLK1 9
P2.3/SINT1 5
P2.4/CTS1 6
P2.6 80
P2.7 79
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
17

80C186EB/80C188EB, 80L186EB/80L188EB
Table 7. QFP Package Location with Pin Names
Location Name
1 CTS0
2 TXD0
3 RXD0
4 P2.5/BCLK0
5 P2.3/SINT1
6 P2.4/CTS1
7 P2.0/RXD1
8 P2.1/TXD1
9 P2.2/BCLK1
10 AD0
11 AD8 (A8)
12 VSS
13 VCC
14 VSS
15 AD1
16 AD9 (A9)
17 AD2
18 AD10 (A10)
19 AD3
20 AD11 (A11)
Location Name
21 AD4
22 AD12 (A12)
23 AD5
24 AD13 (A13)
25 AD6
26 AD14 (A14)
27 AD7
28 AD15 (A15)
29 A16
30 A17
31 A18
32 A19/ONCE
33 VSS
34 VCC
35 VSS
36 RD
37 WR
38 ALE
39 BHE (RFSH)
40 S2
Location Name
41 S1
42 S0
43 DEN
44 HLDA
45 HOLD
46 TEST
47 LOCK
48 NMI
49 READY
50 P1.7/GCS7
51 P1.6/GCS6
52 P1.5/GCS5
53 VSS
54 VCC
55 P1.4/GCS4
56 P1.3/GCS3
57 P1.2/GCS2
58 P1.1/GCS1
59 P1.0/GCS0
60 LCS
Location Name
61 UCS
62 INT0
63 INT1
64 INT2/INTA0
65 INT3/INTA1
66 INT4
67 PDTMR
68 RESIN
69 RESOUT
70 OSCOUT
71 CLKIN
72 VCC
73 VSS
74 CLKOUT
75 T0OUT
76 T0IN
77 T1OUT
78 T1IN
79 P2.7
80 P2.6
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
18

80C186EB/80C188EB, 80L186EB/80L188EB
272433–6
NOTE:
This is the FPO number location (indicated by X’s).
Pin names in parentheses apply to the 80C188EB/80L188EB.
Figure 5. Quad Flat Pack Pinout Diagram
19

80C186EB/80C188EB, 80L186EB/80L188EB
Table 8. SQFP Pin Functions with Location
AD Bus
AD0 47
AD1 52
AD2 54
AD3 56
AD4 58
AD5 60
AD6 62
AD7 64
AD8 (A8) 48
AD9 (A9) 53
AD10 (A10) 55
AD11 (A11) 57
AD12 (A12) 59
AD13 (A13) 61
AD14 (A14) 63
AD15 (A15) 65
A16 66
A17 67
A18 68
A19/ONCE 69
Bus Control
ALE 75
BHEÝ(RFSHÝ)76
S0Ý79
S1Ý78
S2Ý77
RDÝ73
WRÝ74
READY 6
DENÝ80
LOCKÝ4
HOLD 2
HLDA 1
Processor Control
RESINÝ25
RESOUT 26
CLKIN 28
OSCOUT 27
CLKOUT 31
TESTÝ/BUSY 3
NMI 5
INT0 19
INT1 20
INT2/INTA0Ý21
INT3/INTA1Ý22
INT4 23
PDTMR 24
Power and Ground
VCC 11
VCC 29
VCC 50
VCC 71
VSS 10
VSS 30
VSS 49
VSS 51
VSS 70
VSS 72
I/O
UCSÝ18
LCSÝ17
P1.0/GCS0Ý16
P1.1/GCS1Ý15
P1.2/GCS2Ý14
P1.3/GCS3Ý13
P1.4/GCS4Ý12
P1.5/GCS5Ý9
P1.6/GCS6Ý8
P1.7/GCS7Ý7
P2.0/RXD1 44
P2.1/TXD1 45
P2.2/BCLK1 46
P2.3/SINT1 42
P2.4/CTS1Ý43
P2.5/BCLK0 41
P2.6 37
P2.7 36
CTS0Ý38
TXD0 39
RXD0 40
T0IN 33
T1IN 35
T0OUT 32
T1OUT 34
Table 9. SQFP Pin Locations with Pin Names
1 HLDA
2 HOLD
3 TESTÝ
4 LOCKÝ
5 NMI
6 READY
7 P1.7/GCS7Ý
8 P1.6/GCS6Ý
9 P1.5/GCS5Ý
10 VSS
11 VCC
12 P1.4/GCS4Ý
13 P1.3/GCS3Ý
14 P1.2/GCS2Ý
15 P1.1/GCS1Ý
16 P1.0/GCS0Ý
17 LCSÝ
18 UCSÝ
19 INT0
20 INT1
21 INT1/INTA0Ý
22 INT3/INTA1Ý
23 INT4
24 PDTMR
25 RESINÝ
26 RESOUT
27 OSCOUT
28 CLKIN
29 VCC
30 VSS
31 CLKOUT
32 T0OUT
33 T0IN
34 T1OUT
35 T1IN
36 P2.7
37 P2.6
38 CTS0Ý
39 TXD0
40 RXD0
41 P2.5/BCLK0
42 P2.3/SINT1
43 P2.4/CTS1Ý
44 P2.0/RXD1
45 P2.1/TXD1
46 P2.2/BCLK1
47 AD0
48 AD8 (A8)
49 VSS
50 VCC
51 VSS
52 AD1
53 AD9 (A9)
54 AD2
55 AD10 (A10)
56 AD3
57 AD11 (A11)
58 AD4
59 AD12 (A12)
60 AD5
61 AD13 (A13)
62 AD6
63 AD14 (A14)
64 AD7
65 AD15 (A15)
66 A16
67 A17
68 A18
69 A19/ONCE
70 VSS
71 VCC
72 VSS
73 RDÝ
74 WRÝ
75 ALE
76 BHEÝ(RFSHÝ)
77 S2Ý
78 S1Ý
79 S0Ý
80 DENÝ
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
20