Intel SE7520AF2 Configuration guide

Intel® Server Board
SE7520AF2
Technical Product Specification
Intel order number C77866-003
Revision 1.2
March, 2005
Enterprise Platforms and Services Marketing

Revision History Intel® Server Board SE7520AF2 TPS
Revision 1.2
Intel order number C77866-003
ii
Revision History
Date Revision
Number Modifications
01/2004 0.5 First release
05/2004 0.97 Second release
05/2004 0.99 Added integrated Intel® RAID Controller SROMBU42E Chapter
08/2004 1.0 First public release
01/2005 1.1
Q1’2005 Update (rolled Spec Update documentation changes and updated
BIOS Setup screen changes)
03/2005 1.2 Updated mBMC and Intel Management Module platform sensors tables

Intel® Server Board SE7520AF2 TPS Disclaimers
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Disclaimers
Information in this document is provided in connection with Intel®products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining
applications. Intel may make changes to specifications and product descriptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Server Board SE7520AF2 may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized
errata are available on request.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2005.

Table of Contents Intel® Server Board SE7520AF2 TPS
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Intel® Server Board SE7520AF2 TPS Table of Contents
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Table of Contents
1. Introduction ........................................................................................................................ 21
1.1 Chapter Outline...................................................................................................... 21
1.2 Server Board Use Disclaimer ................................................................................ 22
2. Server Board Overview......................................................................................................23
2.1 Intel® Server Board SE7520AF2 SKU Options ..................................................... 23
2.2 Intel® Server Board SE7520AF2 Feature Set ....................................................... 23
2.3 Server Board Layout..............................................................................................25
2.3.1 Component Placement .......................................................................................... 25
2.3.2 Mechanical Drawing .............................................................................................. 26
2.3.3 ATX I/O Layout ...................................................................................................... 27
3. Functional Architecture ..................................................................................................... 29
3.1 Intel® E7520 Chipset............................................................................................. 30
3.1.1 Memory Controller Hub (MCH) .............................................................................. 30
3.1.2 PCI-X Hub (PXH)................................................................................................... 34
3.1.3 IOP332 I/O Processor............................................................................................ 35
3.1.4 I/O Controller Hub (ICH5-R) .................................................................................. 35
3.2 Processor Sub-system........................................................................................... 39
3.2.1 Processor VRD ...................................................................................................... 40
3.2.2 Reset Configuration Logic ..................................................................................... 40
3.2.3 Processor Module Presence Detection .................................................................40
3.2.4 GTL2006................................................................................................................ 41
3.2.5 Common Enabling Kit (CEK) Design Support........................................................ 41
3.3 Memory Sub-System ............................................................................................. 41
3.3.1 Supported Memory ................................................................................................ 42
3.3.2 DIMM Population Rules and Supported Configurations ........................................ 42
3.3.3 Single Channel Operation...................................................................................... 44
3.3.4 I2C Bus................................................................................................................... 44
3.3.5 Memory Voltage Margining....................................................................................44
3.3.6 Memory RASUM Features..................................................................................... 44
3.4 I/O Sub-System ..................................................................................................... 51
3.4.1 PCI Subsystem ...................................................................................................... 51
3.4.2 Interrupt Routing .................................................................................................... 55

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3.4.3 SCSI Support......................................................................................................... 60
3.4.4 RAID Functionality ................................................................................................. 62
3.4.5 Parallel ATA (PATA) Support ................................................................................ 63
3.4.6 Serial ATA (SATA) Support ................................................................................... 64
3.4.7 Video Controller ..................................................................................................... 65
3.4.8 Network Interface Controller (NIC) ........................................................................ 67
3.4.9 USB 2.0 Support.................................................................................................... 68
3.4.10 Super I/O ............................................................................................................... 68
3.4.11 BIOS Flash ............................................................................................................ 70
3.5 Configuration and Initialization............................................................................... 70
3.5.1 Memory Space....................................................................................................... 70
3.5.2 I/O Map .................................................................................................................. 76
3.5.3 Accessing Configuration Space............................................................................. 78
3.5.4 Hardware Initialization ........................................................................................... 80
3.6 Clock Generation and Distribution .........................................................................81
4. Integrated Intel® RAID Controller SROMBU42E.............................................................. 83
4.1 Overview................................................................................................................ 83
4.2 Primary Integrated Intel RAID Controller SROMBU42E Features ......................... 83
4.2.1 Configuration on Disk ............................................................................................ 85
4.2.2 Array Performance Features ................................................................................. 85
4.2.3 Fault Tolerance Capabilities ..................................................................................85
4.3 RAID Software Stack ............................................................................................. 86
4.3.1 General RAID Features ......................................................................................... 86
4.3.2 RAID Level Migration............................................................................................. 87
4.3.3 Fault Tolerant Features ......................................................................................... 87
4.3.4 Cache Options and Settings .................................................................................. 87
4.3.5 Background Tasks ................................................................................................. 88
4.3.6 Error Handling........................................................................................................ 88
4.3.7 Decoding an Audible Alarm ................................................................................... 89
4.4 Levels of RAID....................................................................................................... 89
4.4.1 RAID 0 - Data Striping ........................................................................................... 89
4.4.2 RAID 1 - Disk Mirroring/Disk Duplexing................................................................. 90
4.4.3 RAID 5 - Data Striping with Striped Parity ............................................................. 90
4.4.4 RAID 10 - Combination of RAID 1 and RAID 0...................................................... 91
4.4.5 RAID 50 - Combination of RAID 5 and RAID 0...................................................... 91

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4.4.6 Levels of Drive Hierarchy within the Intel® Integrated RAID Firmware ................. 92
4.5 Intel® RAID Controller Drivers............................................................................... 93
4.6 Intel® RAID Web Console .....................................................................................93
4.7 Intel® RAID BIOS Console Configuration Utility.................................................... 94
4.7.1 Quick Configuration Steps ..................................................................................... 94
4.7.2 Starting the BIOS Console Utility on the Host Computer....................................... 94
4.7.3 Screen and Option Descriptions ............................................................................ 95
4.7.4 Configuration Mismatch Screen............................................................................. 98
4.7.5 Detailed Configuration Instructions........................................................................ 98
4.7.6 Finish Configuration............................................................................................. 102
4.7.7 Initialize the Drive ................................................................................................ 102
5. System BIOS..................................................................................................................... 105
5.1 BIOS Identification String..................................................................................... 105
5.2 Supported BIOS Features ...................................................................................105
5.3 Processor Initialization......................................................................................... 106
5.3.1 Multiple Processor Initialization ........................................................................... 106
5.3.2 Mixed Processor Steppings ................................................................................. 107
5.3.3 Mixed Processor Models .....................................................................................107
5.3.4 Mixed Processor Families.................................................................................... 107
5.3.5 Mixed Processor Cache Sizes............................................................................. 107
5.3.6 Jumperless Processor Speed Settings................................................................ 107
5.3.7 Microcode ............................................................................................................ 108
5.3.8 Processor Cache ................................................................................................. 108
5.3.9 Hyper-Threading Technology .............................................................................. 108
5.3.10 Intel SpeedStep® Technology ............................................................................. 108
5.3.11 Intel® Extended Memory 64 Technology (Intel® EM64T) ................................... 108
5.4 Memory Initialization ............................................................................................ 108
5.4.1 Memory Sizing ..................................................................................................... 109
5.4.2 Disabling DIMMs.................................................................................................. 109
5.4.3 Memory On-Line Sparing and Mirroring............................................................... 109
5.4.4 ECC Memory Initialization ................................................................................... 110
5.4.5 Memory Population.............................................................................................. 110
5.4.6 DIMM Module Capacity ....................................................................................... 110
5.4.7 Memory Error Handling........................................................................................ 111
5.4.8 Memory Test........................................................................................................ 111

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5.5 PCI Initialization ................................................................................................... 112
5.5.1 Scan Order .......................................................................................................... 112
5.5.2 Resource Assignment.......................................................................................... 112
5.5.3 Automatic IRQ Assignment.................................................................................. 112
5.5.4 Option ROMs ....................................................................................................... 112
5.5.5 PCI APIs .............................................................................................................. 113
5.5.6 Split Option ROM................................................................................................. 113
5.5.7 Dual Video ........................................................................................................... 113
5.5.8 PCI Hot Plug Initialization .................................................................................... 113
5.5.9 PCI Express* Initialization.................................................................................... 116
5.5.10 PCI Express* Enhanced Configuration Mechannisms......................................... 116
5.5.11 Legacy Universal Serial Bus (USB) Initialization ................................................. 116
5.5.12 IDE Initialization ................................................................................................... 116
5.5.13 Removable Media Initialization ............................................................................ 117
5.6 Flash ROM........................................................................................................... 117
5.7 BIOS User Interface............................................................................................. 117
5.7.1 System State Window.......................................................................................... 118
5.7.2 Logo/Diagnostic Window ..................................................................................... 118
5.7.3 Current Activity Window....................................................................................... 118
5.8 System Diagnostic Screen................................................................................... 118
5.8.1 Static Information Display .................................................................................... 118
5.9 Quiet Boot / OEM Splash Screen ........................................................................ 119
5.10 BIOS Boot Popup Menu ...................................................................................... 119
5.11 BIOS Setup Utility ................................................................................................ 119
5.11.1 Localization.......................................................................................................... 120
5.11.2 Console Redirection ............................................................................................ 120
5.11.3 Configuration Reset ............................................................................................. 120
5.11.4 Keyboard Commands .......................................................................................... 120
5.11.5 Entering BIOS Setup ...........................................................................................121
5.12 Flash Architecture and Flash Update Utility......................................................... 137
5.13 Rolling BIOS and On-line Updates ...................................................................... 138
5.14 Flash Update Utility.............................................................................................. 138
5.14.1 Flash BIOS .......................................................................................................... 139
5.14.2 User Binary Area .................................................................................................140
5.14.3 Recovery Mode.................................................................................................... 140

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5.14.4 Update OEM Logo ............................................................................................... 141
5.15 OEM Binary ......................................................................................................... 142
5.15.1 Scan Point Definitions.......................................................................................... 144
5.15.2 Format of the OEM Binary Structure.................................................................... 145
5.16 Quiet Boot / OEM Splash Screen ........................................................................ 145
5.17 Operating System Boot, Sleep, and Wake .......................................................... 146
5.17.1 Microsoft* Windows* Compatibility ...................................................................... 146
5.17.2 Advanced Configuration and Power Interface (ACPI) ......................................... 146
5.17.3 Sleep and Wake Functionality .............................................................................147
5.17.4 On to Off (operating system-Present) or operating system to Sleep ................... 147
5.17.5 Sleep to On (ACPI) .............................................................................................. 148
5.17.6 System Sleep States ...........................................................................................148
6. Platform Management...................................................................................................... 149
6.1 Management Architecture Overview.................................................................... 149
6.1.1 Tiered Server Management Model ...................................................................... 149
6.1.2 5V Standby .......................................................................................................... 153
6.1.3 IPMI Messaging, Commands, and Abstractions.................................................. 154
6.1.4 IPMI ‘Sensor Model’............................................................................................. 154
6.1.5 Private Management Bus .................................................................................... 155
6.1.6 Management Controllers ..................................................................................... 156
6.2 Onboard Platform Instrumentation Management Features and Functionality ..... 158
6.2.1 mBMC Self-test.................................................................................................... 159
6.2.2 SMBus Interfaces ................................................................................................ 159
6.2.3 External Interface to mBMC................................................................................. 159
6.2.4 Messaging Interfaces........................................................................................... 160
6.2.5 Direct Platform Control (IPMI over LAN).............................................................. 162
6.2.6 Wake On LAN / Power On LAN and Magic Packet Support................................ 164
6.2.7 Watchdog Timer .................................................................................................. 165
6.2.8 System Event Log (SEL) ..................................................................................... 165
6.2.9 Sensor Data Record (SDR) Repository ............................................................... 166
6.2.10 Event Message Reception................................................................................... 166
6.2.11 Event Filtering and Alerting.................................................................................. 166
6.2.12 NMI Generation ................................................................................................... 169
6.3 Platform Management Interconnects................................................................... 170
6.3.1 Power Supply Interface Signals........................................................................... 170

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6.3.2 System Reset Control.......................................................................................... 171
6.3.3 Temperature-based Fan Speed Control .............................................................. 172
6.3.4 Front Panel Control.............................................................................................. 172
6.3.5 FRU Information .................................................................................................. 176
6.4 Sensors................................................................................................................ 176
6.4.1 Sensor Type Codes ............................................................................................. 176
7. Error Reporting and Handling......................................................................................... 189
7.1 Fault Resilient Booting (FRB) .............................................................................. 189
7.1.1 FRB-3 – BSP Reset Failures ............................................................................... 189
7.1.2 FRB-2 – BSP POST Failures............................................................................... 189
7.1.3 FRB-1 – BSP Self-Test Failures .......................................................................... 190
7.1.4 OS Watchdog Timer: Operating System Load Failures....................................... 190
7.1.5 AP Failures .......................................................................................................... 191
7.1.6 Treatment of Failed Processors........................................................................... 191
7.2 Error Logging ....................................................................................................... 192
7.2.1 Error Sources and Types..................................................................................... 192
7.2.2 SMI Handler......................................................................................................... 192
7.2.3 BIOS Generated IPMI Events.............................................................................. 197
7.2.4 Single Bit ECC Error Throttling Prevention.......................................................... 198
7.3 Error Messages and Error Codes ........................................................................ 199
7.3.1 POST Progress Codes and Messages................................................................ 199
7.3.2 BIOS Messages................................................................................................... 206
7.3.3 POST Error Messages and Handling .................................................................. 212
7.3.4 Boot Block Error Beep Codes.............................................................................. 215
7.3.5 POST Error Beep Codes ..................................................................................... 215
7.3.6 "POST Error Pause" option.................................................................................. 216
8. Connectors, Headers and Jumpers................................................................................ 217
8.1 Board Connector Information............................................................................... 217
8.2 Main Power Connector ........................................................................................ 218
8.3 Main Memory Module Connector......................................................................... 219
8.4 RAID Memory Module Connector........................................................................ 221
8.5 Processor Socket................................................................................................. 222
8.6 System Management Headers ............................................................................ 225
8.6.1 Intel Management Module Connector.................................................................. 225
8.6.2 ICMB Header ....................................................................................................... 228