1
®DDR Power Solution Using the ISL6539
Introduction
The ISL6539 is capable of providing a complete solution for
the power requirements of DDRI, DDRII or DDRIII memory
systems. The ISL6539 can be configured to operate as a
dual switching regulator or as a DDR regulator. This
application note will focus on the ISL6539 configured as a
DDR regulator. For information on the ISL6539 configured
as a dual switching regulator, refer to either the datasheet[1]
or to application note AN1278.
As a DDR regulator, the ISL6539 provides control and
protection for both the VDDQ and VTT rails while also
providing VREF for the DDR system. Both VDDQ and VTT
are provided through synchronous buck regulation. VREF is
provided via a low current buffer.
The switching frequency is fixed at 300kHz for both the
VDDQ and VTT regulators. The two channels can be phase
shifted 90° in order to minimize interaction. The ISL6539
incorporates voltage-feed-forward ramp modulation, current
mode control, and internal feedback compensation, which
provides fast response to input voltage and output load
transients.
Protection features include undervoltage and overvoltage
protection as well as a programmable overcurrent protection
feature that utilizes the rDS(ON) of the lower MOSFET. A
more complete description of the ISL6539 can be found in
the datasheet.
Quick Start Evaluation
The ISL6539EVAL1 board is shipped ‘ready to use’ right
from the box. The box includes this application note, the
ISL6539 datasheet, and the evaluation board.
The evaluation board supports testing with laboratory power
supplies. Both regulated outputs can be exercised through
external loads. There are posts available on the two
regulated output rails for drawing a load and/or monitoring
the voltages. An LED indicates the status of the PGOOD
signal. There are also three scope probe points that allow for
in depth analysis and two posts available to monitor the
enable signals for either channel. Four jumpers have also
been provided for control and monitoring purposes.
Recommended Test Equipment
To test the full functionality of the ISL6539, the following
equipment is recommended:
• Two laboratory power supplies
• Two Electronic Loads
• Four-channel Oscilloscope with probes
• Precision Digital Multimeters
CIRCUIT SETUP
Refer to Figure 1 for locations of the jumpers, connectors
and components described in the following sections.
JUMPER SETTINGS
There are four jumpers on the board. Shunting jumper JP3
pulls the EN1 pin to VCC and is used to enable Channel 1,
which is the VDDQ regulator. Shunting jumper JP4 enables
Channel 2, which is the VTT regulator. It should be noted that
the input rail for the VTT regulator is the VDDQ rail. If the
VDDQ rail is to be disabled and the VTT rail enabled, then
the VDDQ rail must be energized from an external power
supply and a 0.01µF capacitor should be installed in location
C21 for the VTT rail to soft-start properly. C21 is the soft-start
capacitor for the VTT rail, as shown in the schematic.
Jumper JP1 can be used to monitor the ISL6539 bias current
by connecting an ammeter to the two jumper pins. If the bias
current is not being monitored, this jumper must be shunted.
Jumper JP5 is used to set the phase angle between the two
switching regulators. Refer to Figure 1 for the jumper
positions relating to the desired phase angle. Table 1 also
provides a detailed description of the jumper descriptions
and positions.
CONNECTING LOADS
Loads should only be connected to the VDDQ and VTT rails.
Loading VDDQ:Connect the positive terminal of an
electronic load to the VDDQ post (J5). Connect the return
terminal of the same load to the adjacent GND post (J7).
Loading VTT - Sourcing Current: To test VTT while the
regulator sources current, connect the positive terminal of an
electronic load to the VTT post (J6). Connect the return
terminal of the same load to the adjacent GND post (J9).
JUMPER POSITION FUNCTION
JP1 Shunted An AmpMeter may be connected across
thesepinstomeasureICandGATEDrive
current
JP3 Shunted CH1 enabled
Removed CH1 disabled
JP4 Shunted CH2 enabled
Removed CH2 disabled
JP5
Toward
VINPRG This will tie VIN pin to the input voltage for
feed forward. It will also program CH2
PWM to phase lag CH1 by 90°
Away from
VINPRG This will tie VIN pin to GND, disabling
input voltage feed forward, and will also
program in phase PWM for CH1 and CH2
TABLE 1. DETAILED DESCRIPTION OF THE JUMPER
SETTINGS
Application Note October 30, 2006 AN1278.0
Author: Douglas Mattingly
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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