JVC KD-LX555R User manual

SERVICE MANUAL
COPYRIGHT © 2003 VICTOR COMPANY OF JAPAN, LTD. No.49793
2003/5
CD RECEIVER
4979320034
KD-LX555R
TABLE OF CONTENTS
1 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Disassembly method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Description of major ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
S
KD-LX555R
10
7 8
9
11
12
STDM
SOURCE
Area Suffix
E ------ Continental Europe

1-32 (No.49793)
SECTION 4
Description of major ICs
4.1 BA6956AN (IC830, IC831) : Reversible motor driver
• Block diagram
• Pin function • Truth table
TSD
CONTROL LOGIC
1 2 3 4 5 6 7 8 9
V
REF
OUT2
RNF
OUT1
VM
Vcc
FIN
GND
RIN
Pin No. Symbol Function
1 VREF Output high voltage level control terminal
2 OUT2 Output terminal for motor
3 RNF GND of driver division
4 OUT1 Output terminal for motor
5 VM Power supply for driver division
6 Vcc Power supply for signal division
7 FIN Input terminal for control logic
8GNDGND
9 RIN Input terminal for control logic
FIN RIN OUT1 OUT2 MODE
H L H L Forward rotation mode
L H L H Reverse rotation mode
H H L L Break Mode
L L OPEN OPEN Stand-by mode

(No.49793)1-33
4.2 BR24C01AFV-W-X (IC1502) : EEPROM
•Pinlayout
• Block diagram
• Pin function
*1 An open drain output requires a pull-up resister.
A0 A1 A2 GND
Vcc WP SCL SDA
A0
A1
A2
GND
1
2
3
4
Vcc
WP
SCL
SD
A
8
7
6
5
1kbit EEPROM ARRAY
7bit
ADDRESS
DECODER SLAVE/WORD
ADDRESS REGISTER
7bit
8bit
DATA
REGISTER
CONTROL LOGIC
HIGH VOLTAGE GEN. Vcc LEVEL DETECT
ACK
START STOP
Pin name I/O Description
Vcc - Power supply
GND - Ground (0v)
A0,A1,A2 IN Slave address set
SCL IN Serial clock input
SDA IN / OUT Slave and word addressserial data input serial data output *1
WP IN Write protect input

1-34 (No.49793)
4.3 BR24C32F (IC703) : EEPROM
• Pin Layout
• Pin layout & Block diagram
• Pin function
4.4 HD74HC126FP (IC771) : Changer Control
SDASCLWP
BR24C32/F
VCC
GNDA2A1A0
PIN NAME I/O Function
VCC - Power Supply
GND - Ground (0V)
A0-A2 I Slave Address Set
SCL I Serial Clock Input
SDA I/O Slave and Word Address.
Serial Data Input$ Serial Data Output *1
WP I Write Protect Input
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SD
A
A0
A1
A2
GND
32 Kbit EEPROM ARRAY
8bit
12bit
12bit
DATA
REGISTER
SLAVE WORD
ADDRESS REGISTER
ADDRESS
DECODER
START STOP
CONTROL LOGIC
VCC LEVEL DETECT
HIGH VOLTAGE GEN.
ACK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OE1
A1
Y1
OE2
A2
Y2
Vss
Vcc
OE4
A4
Y4
OE3
A3
Y3
HD74HC126

(No.49793)1-35
4.5 BU1923F (IC51) : RDS decoder
•Pinlayout
• Block diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QUAL
RDATA
Vref
MUX
VDD1
VSS1
VSS3
CMP
RCLK
N.C.
XO
XI
VDD2
VSS2
T1
T2
-
+
8th Switched
capacitor filter
PLL
57kHz
RDS/ARI
PLL
1187.5Hz Bi-phase
decoder Differential
decoder
Measurement
circuit
Reference
clock
100k
100k
120k
anti-aliasing
filter
comparator
Analog
Power supply
Digital
Power supply
4
3
5
6
12
11
13 14 10 9
78
16
1
2
MUX
Vref
VDD1
VSS1
VDD2
VSS2
Xl X0 T1 T2
RDAT
A
QUAL
RCLK
CMP
VSS3

1-36 (No.49793)
4.6 HA13164A (IC961) : Regulator
• Terminal layout
• Block diagram
• Pin function
123456789101112131415
Pin No. Symbol Function
1 EXTOUT Output voltage is VCC-1 V when M or H level applied to CTRL pin.
2 ANTOUT Output voltage is VCC-1 V when M or H level to CTRL pin and H level to ANT-CTRL.
3 ACCIN Connected to ACC.
4 VDDOUT Regular 5.7V.
5 SW5VOUT Output voltage is 5V when M or H level applied to CTRL pin.
6 COMPOUT Output for ACC detector.
7 ANT CTRL L:ANT output OFF H:ANT output ON
8 VCC Connected to VCC.
9 BATT DET Low battery detect.
10 AUDIO OUT Output voltage is 9V when M or H level applied to CTRL pin.
11 CTRL L:BIAS OFF M:BIAS ON H:CD ON
12 CD OUT Output voltage is 8V when H level applied to CTRL pin.
13 ILM AJ Adjustment pin for ILM output voltage.
14 ILM OUT Output voltage is 10V when M or H level applied to CTRL pin.
15 GND Connected to GND.
2
1
11
12
10
15 13
14
5
4
6
3
8
9
7
ILM AJGND GND
C6
10u
C5
0.1u
C4
0.1u
C3
0.1u
AUDIO OUT
CD OUT
CTRL
ANT CTRL
EXT OUT
ANT OUT
VCC ACC
Surge Protector
BIAS TSD
C1
100u C2 0.1u
+B
ACC
BATT.DET OUT
COMPOUT
VDD OUT
SW5VOUT
ILMOUT
C7
0.1u
C8
0.1u
R1
UNIT R:
C:F
note1) TAB (header of IC)
connected to GND
TAB

(No.49793)1-37
4.7 HD74HCT126T-X : (IC1500,IC1503) Buffer
• Pin arrangement • Pin function
H : High level
L : Low level
X : Irrelevant
Z : Off (Hhigh-impedance)state of a 3-stage output
• Block diagram
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Vcc
4C
4A
4Y
3C
3A
3Y
1C
1A
1Y
2C
2A
2Y
GND
Input Output
CA Y
LX Z
HL L
HH H
1Y
2Y
3Y
4Y
1A
1C
2A
2C
3A
3C
4A
4C

1-38 (No.49793)
4.8 LA47505 (IC941) : Power amp.
• Terminal layout
Muting &
On Time Control
Circuit
protective
circuit
Mute
circuit
Protective
circuit
Ripple
Filter
Stand by
Switch
11
16
14
13
25
15
10
4
1
12
22
17
19
18
21
23
24
2
3
5
8
7
9
206

(No.49793)1-39
• Terminal layout
• Pin function
AC CONT1 GND1 OUTFR- STBY OUTFR+ Vcc1/2 OUTRR- GND2 OUTRR+ VREF INRR INFR SGND INFL INRL ONTIME OUTRL+ GND3 OUTRL- Vcc3/4 OUTFL+ MUTE OUTFL- GND4 NC
Pin No. Symbol Function
1 AC CONT1 Header of IC
2 GND1 Power GND
3 OUTFR- Outpur(-) for front Rch
4 STBY Stand by input
5 OUTFR+ Output (+) for front Rch
6 Vcc1/2 Power input
7 OUTRR- Output (-) for rear Rch
8 GND2 Power GND
9 OUTRR+ Output (+) for rear Rch
10 VREF Ripple filter
11 INRR Rear Rch input
12 INFR Front Rch input
13 SGND Signal GND
14 INFL Front Lch input
15 INRL Rear Lch input
16 ONTIME Power on time control
17 OUTRL+ Output (+) for rear Lch
18 GND3 Power GND
19 OUTRL- Output (-) for rear Lch
20 Vcc3/4 Power input
21 OUTFL+ Output (+) for front
22 MUTE Muting control input
23 OUTFL- Output (-) for front
24 GND4 Power GND
25 NC No connection

1-40 (No.49793)
4.9 LA6579H-X (IC1681) : 4-Channel bridge driver
• Pin layout & Block diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FR FR
VIN1
VIN1-B
VIN1+B
S-GND
VIN1-S
W
MUTE
VREFIN
VCCS
3.3VREG
REGIN
VIN2G
VIN2
VIN3G
VIN3
FR
VIN1-A
VIN1+A
VCCP1
VO+
VO-
VO2+
VO2-
VO3+
VO3-
VO4+
VO4-
VCCP2
VIN4
VIN4G
FR
+
-
+
-
+
-
[H]
[L]
VIN1_SW
[H]: OP-AMP_A
[L]: OP-AMP_B
33k 11k Signal system
power supply
All outputs ON/OFF
H : ON
L : OFF MUTE
Level shift Level shift
Power system GND
Signal system
power supply
3.3VREG
(External:PTP Tr)
+
-
Power system
GND
Level shift Level shift
+
-
33k 11k
+
-
+
-
+
-11k
33k
33k
11k

(No.49793)1-41
• Pin function
Pin No. Symbol Function
1 VIN1-A CH1 input AMP_inverted input
2 VIN1+A CH1 input AMP_non-inverted input
3 VCCP1 CH1 and CH2 power stage power supply
4 VO1+ Output pin(+)for channel 1
5 VO1- CH1 output pin (-) for channel 1
6 VO2+ Output pin(+)for channel 2
7 VO2- Output pin(-)for channel 2
8 VO3+ Output pin(+)for channel 3
9 VO3- Output pin(-)for channel 3
10 VO4+ Output pin(+)for channel 4
11 VO4- Output pin(-)for channel 4
12 VCCP2 CH3 and CH4 power stage powr supply
13 VIN4 Input pin for channel 4
14 VIN4G Input pin for channel 4(for gain adjustment)
15 VIN3 Input pin for channel 3
16 VIN3G Input pin for channel 3(for gain adjustment)
17 VIN2 Input pin for channel 2
18 VIN2G Input pin for channel 2(for gain adjustment)
19 REGIN External PNP transistor base connection
20 3.3VREG 3.3VREG output pin external PNP transistor,collector connection
21 VCCS Signal system GND
22 VREFIN Reference voltage application pin
23 MUTE Output ON/OFF pin
24 VIN1_SW CH1 input OP AMP_changeover pin
25 S_GND Signal system GND
26 VIN1+B CH1 AMP_B non-inverted input pin
27 VIN1-B CH1 AMP_B inverted input pin
28 VIN1 CH1 input pin input OP_AMP output pin

1-42 (No.49793)
4.10 M61508FP (IC400) : E.volume
• Pin layout & Block diagram
18 VDD OUT 1
DATA
GND
NonFadaer OUT 1
FRONT OUT 1
REAR OUT1
FADER IN 1
TONE OUT 1
TIMER
DETECTOR
NON FADER
VOLUME
VOL IN 1
SEL OUT 1
DEFN OUT 1
IND 1
INC 1
INB 1
INA 1
DEFN IN 1
DEFP IN 1
REF
VOL IN 2
SEL OUT 2
DEFN OUT 2
IND 2
INC 2
INB 2
INA 2
DEFN IN 2
DEFP IN 2
AVDD
VDD OUT 2
CLOCK
VDD
NonFadaer OUT 2
FRONT OUT 2
REAR OUT2
FADER IN 2
TONE OUT 2
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NON FADER
VOLUME
VOLUME 2
LOUDNESS
+
3BAND TONE
CONTROL
(BASS/MID/
TREBLE)
LOUDNESS
+
3BAND TONE
CONTROL
(BASS/MID/
TREBLE)
VOLUME 1
ZERO
CROSS
DETECTOR
BA
- +
- +
- +
+ -
+ -
+ -
+ -
-
+- +
AB
ZERO
CROSS
DETECTOR
REF
51K
51K
50K
50K
50K
50K
50K
50K
50K
50K
51K
51K
25.5K25.5K
25.5K
30K 30K
25.5K
VCC
SOFT
SELECT
I/F
GNDVDD
ZERO DETECT SELECT SWITCH

(No.49793)1-43
• Pin function
Pin No. Symbol Function
1 REF IC signal GND
2 DEFP IN 1 Ope amp positive input
3 DEFN IN 1 Ope amp negative input
4 INA 1 Input selector ch1 input terminal
5 INB 1 Input selector ch1 input terminal
6 INC 1 Input selector ch1 input terminal
7 IND 1 Input selector ch1 input terminal
8 DEFN OUT 1 Operation outoutterminal (-)
9 SEL OUT 1 Input selector output terminal
10 VOL IN 1 Volume 1 input terminal
11 TONE OUT 1 Tone output terminal
12 FADER IN 1 Volume 2 input terminal
13 REAR OUT1 Fader volume (rear) output terminal
14 FRONT OUT 1 Fader volume (front) output terminal
15 NonFadaer OUT 1 Non fader volume output terminal
16 GND GND
17 DATA Control data input terminal
18 VDDOUT 1 Connect to GND with capacitor
19 VDDOUT 2 Connect to GND with capacitor
20 CLOCK Serial data clock input terminal
21 VDD VDD for digital
22 NonFadaer OUT 2 Non fader volume output terminal
23 FRONT OUT 2 Fader volume (front) output terminal
24 REAR OUT2 Fader volume (rear) output terminal
25 FADER IN 2 Volume 2 input terminal
26 TONE OUT 2 Tone output terminal
27 VOL IN 2 Volume 1 input terminal
28 SEL OUT 2 Input selector output terminal
29 DEFN OUT 2 Ope amp output terminal (-)
30 IND 2 Input selector switch ch2 input terminal
31 INC 2 Input selector switch ch2 input terminal
32 INB 2 Input selector switch ch2 input terminal
33 INA 2 Input selector switch ch2 input terminal
34 DEFN IN 2 Ope amp negative input terminal
35 IEFP IN 2 Ope amp positive input terminal
36 VCC VCC for analog

1-44 (No.49793)
4.11 LC75878W (IC601) : LCD driver
• Pin layout
• Block diagram
• Pin function
1
~
25
75
~
51
26 ~ 50
100 ~ 76
No. Symbol I/O Function
1~73 SEG1~SEG73 O Segment driver output pin.
74 SEG74 O Segment driver output pin.
75 SEG75 O Segment driver output pin.
76~83 COM8~COM1 O Common driver output pin.
84~87 P1~P4 O General-purpose output pin.
88 VDD - Logic block power supply pin.
89 VLCD - LCD driver power supply pin.
90 VLCD0 O LCD driver bias 4/4 voltage (H-level) power pin.
91 VLCD1 I LCD driver bias 3/4 voltage (intermediate level) power pin.
92 VLCD2 I LCD driver bias 2/4 voltage (intermediate level) power pin.
93 VLCD3 I LCD driver bias 1/4 voltage (intermediate level) power pin.
94 VLCD4 I LCD driver bias 0/4 voltage (L-level) power pin.
95 VSS - Power supply pin to connect to ground.
96 OSC I/O Oscillator pin.
97 LCD RESET I Display off general-purpose output port "L" fixed input pin.
98 CE I Chip enable
99 CL I Synchronization clock
100 DI I Transfer data
OSC
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VSS
P1 P4 COM1 COM8 S75/COM9 S74/COM10 S73 S1
INH
DI
CL
CE
GENERAL
PORT COMMON
DRIVER SEGMENT DRIVER & LATCH
SHIFT REGISTER
CONTROL
REGISTER
CCB
INTERFACE
CLOCK
GENERATOR
CONTRAST
ADJUSTER

(No.49793)1-45
4.12 NJM4565V-X (IC1572) : Dual ope amp
• Terminal layout & Pin function
4.13 NJU7241F25 (IC1651) : Regulator
• Pin Layout • Block Diagram
4.14 NJU7241F33 (IC1504) : Voltage regulator
A
-+
B
-+
8
7
6
5
1
2
3
4
1
2
3
4
5
6
7
8
AOUTPUT
A-INPUT
A+INPUT
V
B+INPUT
B-INPUT
B OUTPUT
V
GND 1
VIN 2
VOUT 3
5 STB
4 NC
Short protect
3 VOUT
1 GND
Vref
VIN 2
STB 5
GND 1
1
2
3
5
4
PIN FUNCTION
1. GND
2. VIN
3. VOUT
4. NC
5. STB

1-46 (No.49793)
4.15 TA2157FN-X (IC1601):RF amp
• Terminal layout
• Block diagram
24 ~ 13
1 ~ 12
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
20k 20k
15k
20k
20k
3k
180k
240k
240k
15pF
15pF
40pF
40pF
10pF
60k
60k
22k
22k
94k
94k
14k
50k
20k
20k
20k 40k
50k
PEAK
15k
40k
2k
1.75k
1.3V
2k
1k
180k
3k
12k
12k
20k
40k30k 10pF
50 A
BOTTOM
PEAK
K
1
x0.5
x2
x0.5
x2
PIN SEL
(APC SW)
TEB
(TE BAL)
RFGC
(AGC Gian)
TEB
(TE BAL)
VCTRLPIN
VCC APC ON -50% +12dB Normal mode
(0dB)
HiZ APC ON 0% +6dB Normal mode
(0dB)
GND APC OFF
(LDO=H) 50% 0dB CD-RW mode
(+12dB)

(No.49793)1-47
• Pin function
Pin No. Symbol I/O Function
1 VCC - 3.3V power supply pin
2 FNI I Main-beam amp input pin
3 FPI I Main-beam amp input pin
4 TPI I Sub-beam amp input pin
5 TNI I Sub-beam amp input pin
6 MDI I Monitor photo diode amp input pin
7 LDO O Laser diode amp output pin
8 SEL I APC circuit ON/OFF control signal, laser diode (LDO) control signal input
or bottom/peak detection frequency change pin.
9 TEB I Tracking error balance adjustment signal input pin
Adjusts TE signal balance by eliminating carrier component from PWM signal (3-state output,
PWM carrier = 88.2kHz) output from TC94A14F/FA
TEBC pin using RC-LPF and inputting DC.
TEBC input voltage:GND~VCC
10 TEN I Tracking error signal generation amp negative-phase input pin
11 TEO O Tracking error signal generation amp output pin.
Combining TEO signal RFRP signal with TC94A14F/FA configures tracking search system.
12 RFDC O RF signal peak detection output pin
13 GVSW I AGC/FE/TE amp gain change pin
14 VRO O Reference voltage (VRO) output pin
*VRO=1/2VCC When VCC=3.3V
15 FEO O Focus error signal generation amp output pin
16 FEN I Focus error signal generation amp negative-phase input pin
17 RFRP O Signal amp output pin for track count
Combining RFRP signal and TEO signal with TC94A14F/FA configures tracking search system.
18
19
20
REIS
RFGO
RFGC
I
O
I
RF signal amplitude adjustment amp output pin
RF amplitude adjustment control signal input pin
Adjusts RF signal amplitude by eliminating carrier component from PWM signal (3-state output,
PWM carrier=88.2kHz)output fromTC94A14F/14FA *RFGC pin using RC-LPF and inputting DC.
*RFGC input voltage:GND~VCC
21 AGCIN I RF signal amplitude adjustment amp input pin
22 RFO O RF signal generation amp output pin
23 RFI I RF signal generation amp input pin
24 GND - GND pin
SEL
GND
Hiz
VCC
APC
circuit LDO
OFF Connected VCC through 1k resistor
ON Control signal output
ON Control signal output
VCC
GVSW Mode
GND
Hiz
CD-RW
Normal

1-48 (No.49793)
4.16 TC94A14FA (IC1621) : DSP & DAC
• Terminal layout & block daiagram
• Pin function
LPF
1-bit
DAC
Clock
generator
Micro-
controller
interface
Audio out
circuit Digital output
Address
circuit
Correction
circuit
16 k
RAM CLV servo
Digital equalizer
automatic
adjustment circuit
Servo
control A/D
D/A
PWM
Synchronous
guarantee
EFM
decoder
Sub code
decoder PLL
TMAX
VCO
Data
slicer
ROM
RAM
49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
161514131211101 2 3 4 5 6 7 8 9
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin
No Symbol I/O Descroption
1 BCK O Bit clock output pin.32fs48fsor 64fs selectable by command.
2 LRCK O L/R channel clock output pin."L" for L channel and "H" for R channel.
Output polarity can be inverted by command.
3 AOUT O Audio data output pin. MSB-first or LSB-first selectable by command.
4 DOUT O Digital data output pin.Outputs up to double-speed playback.
5 IPF O Correction flag output pin. When set to "H" AOUT output cannot be corrected by C2 correction processing.
6V
DD3 - Digital 3.3V power supply voltage pin.
7V
SS3 - Digital GND pin.
8 SBOK O Subcode Q data CRCC result output pin. "H" level when result is OK.
9 CLCK O Subcode P-W data read I/O pin. I/O polarity selectable by command.
10 DATA O Subcode P-W data output pin.
11 SFSY O Playback frame sync signal output pin.
12 SBSY O Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
13 HSO I/O General-purpose input / output pins.Input port at reset.
14 UHSO
15 PVDD3 - PLL-only 3.3V power supply voltage pin.
16 PDO O EFM and PLCK phase difference signal output pin.

(No.49793)1-49
17 TMAX O TMAX detection result output pin.
18 LPFN I Inverted input pin for PLL LPF amp.
19 LPFO O Output pin for PLL LPF amp.
20 PVREF - PLL-only VREF pin.
21 VCOF O VCO filter pin.
22 AVSS3 - Analog GND pin.
23 SLCO O DAC output pin for data slice level generation.
24 RFI I RF signal input pin. Zin selectable by command.
25 AVDD3 - Analog 3.3V power supply voltage pin.
26 RFCT I RFRP signal center level input pin.
27 RFZI I RFRP signal zero-cross input pin.
28 RFRP I RF ripple signal input pin.
29 FEI I Focus error signal input pin.
30 SBAD I Sub-beam adder signal input pin.
31 TEI I Tracking error input pin. Inputs when tracking servo is on.
32 TEZI I Tracking error signal zero-cross input pin.
33 FOO O Focus equalizer output pin.
34 TRO O Tracking equalizer output pin.
35 VREF - Analog reference power supply voltage pin.
36 RFGC O RF amplitude adjustment control signal output pin.
37 TEBC O Tracking balance control signal output pin.
38 SEL O APC circuit ON/OFF signal output pin. At laser on, high impedance with UHS="L",
H output with UHS="H".
39 AVDD3 - Analog 3.3V power supply voltage pin.
40 FMO O Feed equalizer output pin.
41 DMO O Disc equalizer output pin.
42 VSS3 - Digital GND pin.
43 VDD3 - Digital 3.3V power supply voltage pin.
44 TESIN I Test input pin. Normally, fixed to "L".
45 XVSS3 - System clock oscillator GND pin.
46 XI I System clock oscillator input pin.
47 XO O System clock oscillator output pin.
48 XVDD3 - System clock oscillator 3.3V power supply voltage pin.
49 DVSS3R - DA converter GND pin.
50 RO O R-channel data forward output pin.
51 DVDD3 - DA converter 3.3V power supply pin.
52 DVR - Reference voltage pin.
53 LO O L-channel data forward output pin.
54 DVSS3L - DA converter GND pin.
55 ZDET O 1 bit DA converter zero detection flag output pin.
56 VSS5 - Microcontroller interface GND pin.
57 BUS0
58 BUS1
I/O Microcontroller interface data I/O pins.59 BUS2
60 BUS3
61 BUCK I Microcontroller interface clock input pin.
62 /CCE I Microcontroller interface chip enable signal input pin.At "L", BUS0 to BUS3 are active.
63 /RST I Reset signal input pin. At reset, "L".
64 VDD5 - Microcontroller interface 5V power supply pin.
Pin
No Symbol I/O Descroption
TMAX Detection Result
Longer than fixed period
Within fixed period
Shorter than fixed period
"PVDD3"
"HiZ"
"AVSS3"
TMAX Output

1-50 (No.49793)
4.17 TC94A20F-011 (IC1652) : DAC/SRAM built in type D-ROM decoder+ MP3 decoder
• Pin layout
• Block diagram
48 33 32
17
49
64 116
32 31 30 29 28 27 26 25
33
34
35
36
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
6261
6059
5857565554
53
52
51
5049
48
47
46
45
44
43
42
41
40
39
38
37
DIT DAC DAC
Bus
Switch
Address calc.
2sets
General output
port
C-Pointer
register
Y-Pointer
register
X-Pointer
register
ERAM
2k word
CROM
4k word
*7
Y-RAM
4k word
X-RAM
4k word
Flag
Timer
register
X0 X1 X2 Y0 Y1 Y2
MX AX AYMY MZ
ALU
A2A1A0 A3
round & limit round & limit
Audio I/F
Microcom. I/F
MAC
Program
control
Instruction
decoder
PROM
4k*3
=12k word
PRAM
256word
1Mbit
SRAM
SRAM I/F
Interrupt
control
DRAM I/F
General
inputbport
SubCode
I/F
VCO Timing
generator