Kenwood TM-742 User manual

Kenwood 742/942 Service manual
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144/430 MHz, FM MULTI BANDER
TM-742 A/E
144/430/1200 m H z FM TRIBANDER
TM-942 A
SERVICE MANUAL
KEN OOD
©1992-12 PRINTED IN JAPAN
B51 -8192-00 (B) 1094
Panel Ass'y
(A62-0221-03):
TM-742A
(A62-0222-03): TM-742E
(A62-01 97-03): TM-942A
Mettalllc cabinet (T P) Knob (S Q L)
(A01-2068-03) (K29-4808-04)
ifaV I ilsD
sifinr
MiSi
Knob
(K29-4806-04)
Panel Ass'y
(A62-021 9-03)
Knob Ass'y (V L)
(K29-4840-04)
Knob
(K29-4805-04)
Photo is TM-942A
CONTENTS
»
I
OVER VIE ................................ 2
CIRCUIT DESCRIPTION ............................................ 3
DESCRIPTION OF COMPONENTS ........................ 51
SEMICONDUCTOR DATA ..................................... 68
PARTS LIST ............................................................ 71
EXPLODED VIE ................................................. 116
PACKING......... ................ .120
ADJUSTMENT . . ........................................ .122
PC BOARD VIE S/SCHEMATIC DIAGRAM
C NTR L UNIT (X53-346X-XX) ....................... 135
DISPLAY UNIT (X54-31 30-11) .........................137
SCHEMATIC DIAGRAM .................................... 139
1200M TX-RX UNIT (X57-3600-1 1) ................ 143
430/440M TX-RX UNIT (X57-359X-XX) .......... 149
220M TX-RX UNIT (X57-381 0-10) ............ 153
1 44M TX-RX UNIT (X57-3580-XX) ........ 157
50M TX-RX UNIT (X57-3800-01 ) ..................... 161
28M TX-RX UNIT (X57-3790-01 ). . . ............ 165
BLOCK DIAGRAM........................ 169
LEVEL DIAGRAM .................................................175
TSU-7 (CTCSS UNIT) . ..........................................177
MC-45 (MULTI FUNCTION MICROPHONE) ... 179
MC-45DM (MULTI FUNCTION MICROPHONE
ITH AUTOPATCH) ......... ................................... 180
UT-28S/50S/UT-220S/1200
SPECIFICATION ... 181
SPECIFICATION.................................. BACK COVER

TM-742 A/742 E/942A
OVERVIE
List of Destinations
Model Destination Destination
code
Model Destination Destination
code
TM-742A
North America
K
TM-942A
North America
K
TM-742A
Canada
P
TM-942A
Canada
P
TM-742E
Europe E
TM-942A
ther countries
M
TM-742E
Europe
E2
TM-742E
Europe
E3
TM-742A
ther countries
M
TM-742A
ther countries
M2
Units for Each Model and Destination
Unit Name
Parts. No.
TM-742A/E
TM-942A
Band Units
UT-28S UT-50S
UT-220S
UT-1200
K
p E
E2
E3
M
M2 K p M M (50)
M (50)
K (50)
M (10)
Control Unit
X53-3460-1 1
o o o o
Control Unit X53-3460-21
o o
Control Unit X53-3460-22
o
Control
Unit
X53-3462-71
o o
Control Unit
X53-3462-72
o
Display Unit
X54-31 30-11
o o o o
0
o o o o o
28TX-RX
X57-3790-01
o
50TX-RX
X57-3800-01
o
144TX-RX
X57-3580-1 1
o o o
144TX-RX
X57-3580-1 2
o o
o o o o o
220TX-RX
X57-3810-10
o
440TX-RX
X57-3590-1 2
oo
o
430TX-RX
X57-3590-22
o o
430TX-RX X57-3592-72
o o o o o
1 200TX-RX
X57-3600-1 1
o ooo
BAND UNITS
Any of the following optional band units may be installed
in the TM-742A/742E.
The same instructions,apply for the Tri-Bander as for the
Dual-bander.
OPTIONAL BAND UNIT
TM-742A
U.S.A. Version
UT-28S UT-50S UT-220S UT-1200
TM-742A
UT-28S UT-50S UT-1200
TM-742E
UT-28S UT-50S UT-1200
i
i

TM-742 A/742 E/942A
CIRCUIT DESCRIPTION
UT-28S
28 TX-RX Unit Frequency Configuration
The 28 MHz unit incorporates a variable frequency
oscillator
(VF ), based on a phase-locked-loop (PLL)
synthesizer system, that allows a channel step of 5,10,
15, 20, or 25 kHz to be selected. The frequency in the
receive signal channel is mixed with a first local oscillation
frequency of 36.83-38.525 MHz to produce a first
intermediate
frequency (IF) of 8.83 MHz.
This frequency is then mixed with a second local
oscillation frequency of 9.285 MHz to produce a second
IF of 455 kHz. This is called a double-conversion system.
The signal in the transmission channel is produced by
direct oscillation, is frequency-divided by a PLL circuit,
amplified by a linear amplifier, then transmitted.
28^29 695 MHz
36.83~38.525 MHz
,28~29.695MHz
MIC AMP
ANT
SW
MIX, IF, DET
Fig. 1 Frequency configuration
I
I
28 TX-RX Unit Receive Signal Channel
• Outline
The received signal from the antenna passes through
a low-pass filter in the final transmission stage and then
through a transmission/reception selection diode switch
to the receiving front end. The signal then passes
through an antenna matching coil and is amplified to high
frequencies
by a M S field-effect transistor. The un 
wanted components of the signal are eliminated by a
bandpass filter consisting of a three-stage variable ca 
pacitor. The resulting signal goes to the first mixer, is
mixed with the first local signal from the PLL circuit, then
converted to the first IF of 8.83 MHz. The unwanted
near-by signal components are then eliminated by a two-
Item
Rating
Center frequency
(fo)
8830 kHz
Pass bandwidth
± 6 kHz or more at 3 dB
Attenuation
bandwidth
± 20 kHz or less at 40 dB
±40 kHz or less at 60 dB
Guaranteed
attenuation
70 dB or more within Fo ±-1 MHz
(Spurious: 40 dB or more)
Ripple
1 dB or less
Insertion loss
2 dB or less
Terminating
impedance
4.7 kn//0pF
stage MCF.
The first IF signal is amplified and input to FM IF HIC
IC6 (KCD04). This signal is then mixed with the second
local oscillation frequency of 9.285 MHz to produce the
second IF signal of 455 kHz. The unwanted near-by
signal components are then eliminated by an FM ceramic
filter. The resulting signal is inputto IC6 again, amplified
to the second IF signal, and detected to produce an
audio signal.
• Signal-strength meter
The signal-strength meter output voltage of FM IF
HIC IC6 (KCD04) is supplied to the control unit.
Item
Rating
Nominal
center
frequency
455KHZ
6 dB bandwidth ± 6 kHz or more (from 455 kHz)
50 dB bandwidth
± 12.5 kHz or less (from 455 kHz)
Ripple (within.
± 5 kHz of 455 kHz
3 dB or less
Insertion loss (at
maximum output point) •
6 dB or less
Guaranteed attenuation
(within ± 100 kHz of 455
kHz)
35 dB or more
I/ matcing impedance
2.0kn
Table 1 MCF (L71-0422-05) (28TX-RX unit XF1)
Table 2 Ceramic filter CF M455F (L72-0372-05)
(28TX-RX unit CF1)

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
• Shift-register circuit
The ES, CK, and DT serial data from the control unit
are sent to Cl (BU4094BF) to perform the control
operation outlined in the following table:
Pin No.
Name
Function
Pin No.
Name Function
Strobe
Enable input
Qs
Data Serial
data input
10
Q's
Clock Clock
input
11
Q8 TX/RX
selection. High when TX is set.
Q1
TX/RX selection. Low when TX is set
12
Q7
ATT switching: High when ATT is on
Q2 TX
power selection. Low when middle and low.
“ H ” when high.
13
Q6
High for AM; low for FM; High for narrow;
low for wide
Q3
TX power selection. Low when high and low.
“ H ” when middle.
14
Q5
High when off band
Q4
Low when off band
15 E
8V
Vss GND
16
VDD
8V
Table 3
ATT circuit
If there is cross modulation, the ATT circuit operates
to attenuate the received signal before it enters Q2 (FET
for high-frequency amplification).
28 TX-RX Unit Transmit Signal Channel
• Outline
In the transmission channel, the desired frequency is
produced by direct oscillation, and is directly frequency
modulated by means of a varicap diode.
• Modulator circuit
The audio signal from the control unit is input to
microphone
amplifier HIC ICS (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminates unwanted high-frequency
components. The voltage-controlled oscillator (VF )
signal is directly frequency modulated by means of a
varicap diode in the frequency modulator circuit.
• Younger-stage circuit
The signal output from the VC is input to drive
circuit HIC IC16 (KCB16). The amplifier can obtain a
stable drive output without adjustment because it has a
large bandwidth. An ARC circuit controls the collector
voltage in the Younger final stage.
• Power amplifier circuit
The drive signal is amplified to the specified level by
a discrete transistor. Q2 performs class B amplification,
and the collector output voltage is controlled by an ARC
circuit. Q202 amplifies the power by class C operation,
improving the efficiency of the final stage.
Z1 X58-3840- X
Q 202
L201
0201
I D17
Fig. 2 Power amplifier circuit
i
i

TM-742 A/742 E«42A
CIRCUIT DESCRIPTION
• APC circuit
The automatic transmission output control circuit
(APC) detects and partially amplifies the power amplifier
output with a diode, and controls the output control
voltage. Thecontrolvoltageisoutputin inverse proportion
to the output, so the control voltage output is always
constant. To protect the radio against excessive tem 
perature rise, the high-power unit has a thermal switch.
The high-power unit is automatically set to a low power
by the thermal switch if it exceeds the specified tem 
perature.
• 8T (8 V during transmission) and unlock signal
The signal output from pin 4 of IC1 is high during
reception, Q1 3 is turned on, and Q1 4 and Q11 are turned
off. No voltage appears at the coljector (8T) of Q11.
Serial data is output from the control unit during trans
mission and input to shift register IC1 . Pin 4 of IC1 is
then
made low. Therefore, Q1 3 is turned off, and 14and
Q11 are turned on. An 8 V voltage is applied to the
collector (8T) of Q1 1.
If the PLL circuit is unlocked during transmission, the
LD pin goes low, Q24 is turned off, Q13 is turned on,
Q14 is turned off, Q1 1 for 8T switching control is turned
off, and the 8T line does not operate.
8T
8C
I
8 V during reception
0 V during transmission
IC1@ — I
0.7 V during unlock
2 V during lock
C382I
C34Z2
28 TX-RX Unit PLL Synthesizer
The VC and PLL circuits are housed in a solid
shielding case as a hybrid integrated circuit. Compari 
son frequencies are produced by dividing a 9.285 MHz
reference oscillation frequency by 1857 to correspond
to the 5,10, 15, 20, and 25 kHz channel steps.
For 28 MHz, the relationship between f vco (RX) and
each frequency division ratio is given by
Therefore,f vco ={(1 1 5x64)+6}x9285/1 857
=(7360+6)x5
=36.83
MHz
The following table lists the pin functions of the PLL
circuit:
f vco = (28+8.83)={{nx64)+A}xf,
osc
./R
Where: f vco =VC output frequency
n: Binary 10-bit programmable counter setting value
A: Binary 6-bit programmable counter setting value
fosc : Reference oscillation frequency of 9.285 MHz
R: Binary 1 6-bit programmable counter setting value
1857
In this case, n is 155, and A is 6.
IC2:KCH09
2 V during lock
9.285 MHz E
Data input
Clock input
Enable input
-Modulation input
_ 8 V during transmission
" 0 V during reception
— ► Lock voltage
■ HET output
Pin name
Function
Pin name
Function
5C 5V
M
Modulation signal
input
LD
Lock signal (2 V
during locking) 9c
9v
NC
Unused
8CL
8 V (ripple filter)
XI
X
9.285 MHz
crystal
oscillation
ST
8 V during transmis 
sion; 0 V. during
reception
CV Lock voltage output
DP
Data input
E
GND
CP
Clock input
HT
HET output
EP
Enable input
Fig. 4Table
4 PLL circuit pin functions

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
UT-50S
50 TX-RX Unit Frequency Configuration
The 50 MHz unit incorporates a variable frequency
oscillator (VF ), based on a phase-locked-loop (PLL)
synthesizer system, that allows a channel step of 5,10,
15, 20, or 25 kHz to be selected. The frequency in the
receive signaI channel is mixed with a first locaI oscillation
frequency of 60.595-64.590 MHz to produce a first in-
termediatefrequency(IF)of 10.595 MHz. This frequency
is then mixed with a second local oscillation frequency
of 11.05 MHz to produce a second IF of 455 kHz. This
is called a double-conversion system. The signal in the
transmission channel is produced by direct oscillation,
and is frequency-divided by a PLL circuit, amplified by a
linear amplifier, then transmitted.
455 KHz
50-53.995MHZ
10.595 MHz
60.595~ 64.590 MHz
50-53.995 MHz
MIC AMP
RF AMP
TX AMP
ANT S
MIX, IF, DET
11.05 MHz
Fig. 5 Frequency Configuration
50 TX-RX Unit Receive Signal Channel
• Outline
The received signal by the antenna passes through a
low-pass filter in the final transmission stage and then
through a transmission/reception selection diode switch
to the receiving front end. The signal then passes
through an antenna matching coil and is amplified to high
frequencies
by a GaAs (gallium arsenide) field-effect
transistor. The unwanted components of the signal are
eliminated by a bandpass filter consisting of a three-
stage variable capacitor. The resulting signal goes to the
first mixer, is mixed with the first local signal from the
PLL circuit, then converted to the first IF of 10.595 MHz.
The unwanted near-by signal components are then
eliminated by a two-stage MCF.
The first IF signal is amplified and input to FM IF HIC
IC6 (KCD04). This signal is then mixed with the second
local oscillation frequency of 11.05 MHz to produce the
second IF signal of 455 kHz. The unwanted near-by
signal components are then eliminated by an FM ceramic
filter. The resulting signal is inputto IC again, amplified
to the second IF signal, and detected to produce an
audio signal.
Item
Rating
Center frequency
10.595 MHz
Pass bandwi(jth
±6.5 kHz or more at 3 dB
Attenuation banijwiijth ±23
kHz or less at 40 dB
±40 kHz or less at 60 dB
Guaranteed attenuation
70 dB or more within Fo ±1 MHz
(Spurious: 40 dB or more)
Ripple
1 dB or less
Insertion loss
1.5 dB or less
Terminating impedance
2.9 k //0pF
Item
Rating
Nominal center frequency
455KHZ
6 dB bandwidth
±6.0 kHz or more (from 455 kHz)
50 dB bandwidth
±12.5 kHz or less (from 455 kHz)
Ripple (within ±5 kHz
of 3455 kHz)
3 dB or less
insertion loss (at maximum
output point)
6 dB or less
Guaranteed
attenuation
(within ±100 kHz' of 455 kHz)
35 dB or more
Terminating impedance 2.0 kO.
Table 5 MCF {L71-0421-05) (50TX-RX unit XF1)
Table 6 Ceramic filter CF M455F (L72-0372-05)
(50TX-RX
unit CF1)
i
I

TM-742A/742E/942A
CIRCUIT DESCRIPTION
• Signal-strength meter
The signal-strength meter output voltage of FM IF
Flic IC6 (KCD04) is supplied to the control unit.
• Shift-register circuit
The ES, CK, and DT serial data from the control unit
are sent to iCI (BU4094BF) to perform the control op
eration outlined in the following table:
Pin No. Name
Function
Pin No.
Name
Function
Strobe
Enable input
Qs
Data
Serial data input
10
Q's
Clock Clock Input
11
Q8 TX/RX
selection. High when TX is set.
Q1
TX/RX selection. Low when TX is set
12
Q7
ATT switching: High when ATT is on
Q2
TX power selection. Low when middle and low.
“ H ” when high.
13
Q6
High for AM; low for FM
Q3
TX power selection. Low when high and low.
“ H ” when middle.
14
Q5
High when off band
Q4
Low when off band
15 E
8V
Vss GND
16
VDD 8V
Table 7
I
• ATT circuit
If there is cross modulation, the ATT circuit operates
50 TX-RX Unit Transmit Signal Channel
• Outline
In the transmission channel, the desired frequency is
produced by direct oscillation, and is directly frequency
modulated by means of a varicap diode.
• Modulator circuit
The audio signal from the control unit is input to
microphone amplifier FIIC ICS (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminates unwanted high-frequency
components. The voltage-controlled oscillator (VF )
signal is directly frequency modulated by means of a
varicap diode in the frequency modulator circuit.
• Younger-stage circuit
The signal output from the VC is input to drive
circuit Flic IC4 (KCB1 8). The amplifier can obtain a stable
drive output without adjustment because it has a large
bandwidth. An ARC circuit controls the collector voltage
in the Younger final stage.
• Power amplifier circuit
The drive signal is amplified to the specified level by
a discrete transistor. Q201 performs class B amplifica
tion, and the collector output voltage is controlled by an
ARC circuit. Q202 amplifies the power by class C
operation, improving the efficiency of the final stage.
to attenuate the received signal before it enters Q2 (FET
for high-frequency amplification).
Z1 X58-3840-0X
C201 L201
0201
Fig. 6 Power amplifier circuit

TM-742A/742B942A
CIRCUIT DESCRIPTION
• APC circuit
The automatic transmission output control circuit
(APC) detects and partially amplifies the power amplifier
output with a diode, and controls the output control
voltage. The control voltage is output in inverse proportion
to the output, so the control voltage output is always
constant. To protect the radio against excessive
temperature rise, the high-power unit has a thermal
switch. The high-power unit is automatically set to a low
power by the thermal switch if it exceeds the specified
temperature.
• LPF circuit
The low-pass filter sets the pole to the second and
third harmonics, and cuts the frequency, by having the
polar Chebyshev characteristics. To cut high frequen 
cies, a filter with Chebyshev characteristics is used
before the antenna.
o ” p
Fig. 7 LPF Circuit
• 8T (8 V during transmission) and unlock signal
The signal output from pin 4 of IC1 is high during
reception, Q1 3 is turned on, and Q1 4 and Q11 are turned
off. No voltage appears at the collector (8T) of Q11.
Serial data is output from the control unit during
transmission
and input to shift register IC1 . Pin 4 of IC1
is then made low. Therefore, Q1 3 is turned off, Q14and
Q11 are turned on. An 8 V voltage is applied to the
collector (8T) of Q1 1.
IfthePLLcircuitis unlocked during transmission, the
LD pin goes low, Q24 is turned off, Q13 is turned on,
Q1 4 is turned off, Q11 for8Tswitching control is turned
off,
and the 8T line does not operate.
8T
8C
8 V during reception;
0 V during transmission
010
IC1@ ----- 1
0.7 during unlock
2 V during lock
C382Z
2ZC35
C34Z2
ZZC40 ZIC41
i
i

TM-742 A/742 E/942 A
CIRCUIT DESCRIPTION
• 50 TX-RX Unit PLL Synthesizer
The VC and PLL circuits are housed in a solid
shielding case as a hybrid integrated circuit. Compari 
son frequencies are produced by dividing a 11.05 MHz
reference oscillation frequency by 2210 to correspond
to the 5, 10, 15, 20, and 25 kHz channel steps.
For 50 MHz, the relationship between f vco (RX) and
each
frequency division ratio is given by
f vc0 ” (50+10.595) ={(nx64) + A}xf 0SC /R
Where: f vco =VC output frequency
n: Binary 10-bit programmable counter setting value
A: Binary 6-bit programmable counter setting value
f osc : Reference oscillation frequency of 11.05 MHz
R: Binary 16-bit programmable counter setting value
In this case, n is 189, and A is 23.
Therefore, f vco ={(189x64)+23}x1 1050/2210
=(12096+23)x5
= 60.595 MHz
The following table lists the pin functions of the PLL
circuit:
IC2:KCH10
2 V during lock
11.05 MHz i
Data input
Clock
Input
Enable input
Modulation input
8 V during transmission;
0 V during reception
Lock voltage
HET output
Fig. 9
Pin
name
Function Pin name Function
5C 5V
M
Modulation signal
input
LD
Lock signal (2 V
during locking)
9C 9V
NC
Unused
8CL 8
V (ripple filter)
XI
X
11.05 MHz crystal
oscillation
ST
8 V during transmis 
sion; 0 V during
reception
Data input
CV
Lock voltage output
DP
Clock input
E
GND
CP
Enable input
HT
HET output
EP
Table 8 PLL circuit pin functions
I

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
144 TX-RX Unit Frequency Configuration
The 144 MHz unit incorporates a digital variable-
frequency oscillator (VF ) that can freely select a channel
step of 5, 10, 12.5, 15, 20, or 25 kHz with a Phase-
Locked-Loop (PLL) synthesizer system.
The frequency in the receive signal channel is mixed
with a first local oscillation frequency of 133.300-137.295
MHz to produce a first intermediate frequency of 10.7
MHz. This frequency is then mixed with a second local
oscillation frequency of 10.245 MHz to produce a second
intermediate frequency of 455 kHz. This is called a
double-conversion system.
The signal in the transmission channel is directly
oscillated andfrequency-divided by a PLL circuit, amplified
by a straight amplifier, then transmitted.
144- 147.995MHz
455KHZ
MCF
10.7MHz
RA
S 10.245MHz
1 33.300~ 1 37.295MHz
M
144~147.995MHz
ANT
SW
RF AMP
TX AMP MIC
AMP
Fig. 10 Frequency configuration
144 TX-RX Unit Receive Signal Channel
• Outline
For the 144 MHz unit,the received signal from an
antenna is passed through a low-pass filter in the final
transmission stage and sent through a transmission/
reception selection diode switch to the receiving front
end. The signal is then passed through an antenna
matching coil and amplified to high frequencies by a
GaAs (gallium arsenide) field-effect transistor. The
unwanted components
of the signal are eliminated by a
bandpass filter consisting of a three-stage variable
capacitor. The resultant signal is sent to the first mixer,
mixed with the first local signal from a PLL circuit, then
converted
to a first intermediate frequency of 10.7 MHz.
The unwanted near-by signal components are then
eliminated by a two-stage MCF.
Item
Rating
Nominal center frequency (fo)
10.7MHz
Pass bancd wiidth
±7.5kHz or less at 3dB
Attenuation band width
±25kHz or less at 40dB
±45kHz or less at 60dB
Ripple
I. dB or less
Insertion loss
1.5dBorless
Guaranteed attenuation
70dB or more within ±1 MHz
(Spurious : 40dB or more at fo - fo + 500kHz)
80dB or more at fo - (900 - 920kHz)
Terminating impedance 3kQ/0pF
Table 9 MCF (L7 1-0228-05) (144 TX-RX unit XF1)
Item
Rating
Nominal center frequency
455kHz± 1kHz
6dB bandwidth
±6kHz or more (from 455kHz)
50dB bandwidth
± 12.5kHz or less (from 455kHz)
Ripple
(within ±4kHz of 455kHz)
3dB or less
Insertion loss
6dB or less
Guaranteed attenuation
(within
1100kHz of 455kHz)
35dB or more
I/ matching impedance l.OkCl
Table 10 Ceramic filter CF M455F (L72-0372-05)
(144 TX-RX unit CF1)
i
i
10

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
The first intermediate-frequency signal is amplified
and input to FM IF HICIC5 (KCD04). This signal is then
mixed with a second local oscillation frequency of
10.245MHz to produce a second intermediate-
frequency signal of 455 kHz. The unwanted near-by
signal components are then eliminated by an FM
ceramic filter. The resultant signal is input to IC5 again,
amplified to a second intermediate-frequency signal,
and detected to produce an audio signal.
• Signal-strength meter
The signal-strength meter output voltage of FM IF
HIC IC5 (KCD04) is supplied to the control unit.
• Shift-register circuit
The ES, CK, and DT serial data from the control unit
are sent to IC1 (BU4094BF) to perform the control
operation outlined in the following table:
Pin N .
Name
Function
Pin No.
Name
Function
1
Strobe
Enable input
9
Qs
2
Data Serial
data input
10 Q's
3
Clock Clock
input
11
Q8
TX/RX selection. "H" when TX is set.
4
Q1
TX/RX selection. "L" when TX is set
12
Q7
439/144 MHz selection. "H" when 144MHz is
set.
5
Q2
TX power selection. "L" when middle and
low. "H" when high.
13
Q6
6
Q3
TX power selection. "L" when high
and low. "H" when middle.
14
Q5
7
Q4
15
E
8V
8
V ss
GND
16
V
V DD
8V
Table 11
ICS© IFl
K-models.
|iST ifamp I
R20 C23
RF AMP I
|1ST MIX
K-models
Fig. 11
-IC6©
11

TM-742A/742B942A
CIRCUIT DESCRIPTION
144 TX-RX Unit Transmit Signal Channel
• Outline
In the transnnission channel, the desired frequency is
directly oscillated and directly frequency modulated by
means of a varicap diode.
• Modulator circuit
The audio signal from the control unit is input to
microphone amplifier HIC IC7 (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminate unwanted high-frequency
components. The voltage-controlled oscillator (VC )
signal is directly frequency modulated by means of a
varicap diode in the frequency modulator circuit.
• Younger-stage circuit
The
signal output from the VC is input to drive
circuit HIC ICS (KCB1 1). The amplifier can obtain a stable
drive output without adjustment because it has a wide
band. An ARC circuit controls the collector voltage in the
younger final stage.
• Power amplifier circuit
A drive signal is input to power module IC10 and
amplified to the specified level.
• APC circuit
The automatic transmission output control circuit
(APC) detects and partially amplifies the power module
output with a diode and controls the output control
voltage. The control voltage is output in inverse proportion
to the output, so the control voltage output is always
constant. To protect the set against excessive
temperature rise, the high-power unit has a thermal
switch. The high-power unit is automatically setto a low
power by the thermal switch when it exceeds the
specified temperature.
144 TX-RX Unit PLL Synthesizer
The VC and PLL circuit are housed in a solid
shielding case as a hybrid integrated circuit. Com 
parison frequencies of 6.25 kHz and 5 kHz are produced
by dividing a 12.8 MHz reference oscillation frequency
by 2048 and 2560 to correspond to 5, 10,12.5, 15, 20,
and 25 kHz channel steps.
For 144 MHz, the relationship between f VC0 (Rx)
and each frequency division ratio is given by
f V co=( 1 44 -10.7)= {(n x 128) + A) x f n?r - R
osc
Where: f vc0 = VC output frequency
n : Binary 1 0-bit programmable counter setting value
A : Binary 7-bit programmable counter setting value
f osc : Reference oscillation frequency of 12.8 MHz
0 V during lock
12.8 MHz
Data input
Clock input
Enable input
Modulation
Lock voltage
HET output
Fig. 12 IC11 KCH05
R: Binary 14-bit programmable counter setting value
2048
In this case, n is 208, and A is 36.
Therefore, f vco = {(208 x 128) + 36} x 12800 / 2560
= (26624 + 37} X 5
= 133300 kHz = 133.300 MHz
The following table lists the pin functions of the PLL
circuit:
Pin
name
Function
Pin
name
Function
5C
5V
MO
Modulation signal
input
LD Lock
signal (on during
lock)
IOC
10V
NC Unused
8CL 8V
(ripple filter)
XI
[ 12.8 MHz crystal
NC Unused
XO
oscillation
CV
Lock voltage output
DP
Data input
E
GND
CP Clock
input
HT
HET output
EP Enable
Input
Table 12
i
i
12

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
• 8T (8 V during transmission) and unlock signal
A 0.7 V voltage is applied to the base of Q1 3 during
reception, Q13 is set on, Q14 is set off, and Q1 l.is set
off. No voltage appears at the collector (8T) of Q1 1.
Serial data is output from the control unit during
transmission
and input to shift register IC1 . Pin 4 of IC1
is then set lov\/. Therefore, Q1 3 is changed from on to
off, Q1 4 from off to on, and Q1 1 from off to on. An 8 V
voltage is applied to the collector (8T) of Q1 1.
An unlock circuit is activated only during trans
mission. The LD signal output from the PLL circuit is
Red with the signal at pin 4 of IC1 using Dll as shown
in the figure, so the LD signal is set high during unlock.
Therefore, no voltage appears at the collector (8T) of
Q11 and no transmission wave is output to the
reception state.
8C
8T
R40
- v —
W VT
TTT m
Fig. 13
UT-220S
220 TX-RX Unit Frequency Configuration
The 220 MHz unit incorporates a variable frequency
oscillator
(VF ), based on a phase-locked-loop (PLL)
synthesizer system, that allows a channel step of 5,10,
12.5,15,
20, or 25 kHz to be selected. The frequency in
the receive signal channel is mixed with a first local
oscillation frequency of 189.175-194.17 MHz to produce
a first intermediate frequency (IF) of 30.825 MHz. This
frequency is then mixed with a second local oscillation
frequency of 30.37 MHz to produce a second IF of 455
kHz. This is called a double-conversion system. The
signal in the transmission channel is produced by direct
oscillation, and is frequency-divided by a PLL circuit,
amplified
by a linear amplifier, then transmitted.
220~229.995MHz
V
MCF
30.825MHz
1st
MIX
ANT S
I
I
RF AMP
On
455KHZ
MIX , IF, DET
-►ORA
T
30.37MHz
PA
TX AMP
189.175 199.17MHz
PLL Mr
220'V' 229.995
MHz
Fig. 14 Frequency configuration
MIC AMP
- M
13

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
220 TX-RX Unit Receive Signal Channel
• Outline
The received signal from the antenna passes through
a low-pass filter in the final transmission stage and then
through
a transmission/reception selection diode switch
to the receiving front end. The signal then passes
through
an antenna matching coil and is amplified to high
frequencies by a GaAs (gallium arsenide) field-effect
transistor. The unwanted components of the signal are
eliminated bya bandpass filterconsisting of a three-stage
variable capacitor. The resulting signal goes to the first
mixer (GaAs field-effect transistor), is mixed with the
first local signal from the PLL circuit, then converted to
a first If of 30.825 MHz. The unwanted near-by signal
components are then eliminated by a two-stage MCF.
The first IF signal is amplified and input to FM IF HIC
IC5 (KCD04). This signal is then mixed with the second
local oscillation frequency of 30.37 MHz to produce the
second IF signal of 455 kHz. The unwanted near-by
signal componentsare then eliminated by an FM ceramic
filter. The resulting signal is inputto IC5 again, amplified
to the second IFsignal, and detected to producean audio
signal.
Item
Rating
Center frequency (fo) 30,825 MHz
Pass bandwiidth
± 7.5 kHz or more at 3 dB
Attenuation bandwiijth
± 28 kHz or less at 40 dB
Guaranteed attenuation
60 dB or more within Fo ± 1 MHz
(Spurious: 40 dB or more)
Ripple 1.5
dB or less
Insertion loss 3
dB or less
Terminating impedance
4.7 kn//0pF
Table 13 MCF (L71-0420-05) (220 TX-RX unit XF1)
Item
Rating
Nominal center
frequency
455KHZ
6
dB bandwidth
± 6 kHz or more (from 455 kHz)
50 dB bandwidth
± 12.5 kHz or less (from 455 kHz)
Ripple (within
± 5 kHz of 455 kHz)
3 dB or less
Insertion loss (at
maximum output point)
6 dB or less
Guaranteed attenuation
(within ± 100 kHz of 455
kHz)
35 dB or more
I/ matcing impedance
2.0ka
• Signal-strength meter
The signal-strength meter output voltage of FM IF
HIC IC5 (KCD04) is supplied to the control unit.
• Shift-register circuit
The ES, CK, and DT serial data from the control unit
are sent tolCT (BU4094BF) to perform the control op
eration outlined in the following table:
Pin No.
Name
Function
1
Strobe
Enable input
2
Data Serial
data input
3
Clock Clock
input
4
01
TX/RX selection. Low when TX is set.
5
02
TX power selection. Low when middle and
low. High when high.
6
03
TX power selection. Low when high and
low. High when middle.
7
04
9
03
10
03
11
08
12
07
13
06
14
05
15
E
8V
Table 15
(220TX-RX unit CF1)
i
14

TM-742 A/742 E/942 A
CIRCUIT DESCRIPTION
r
220 TX-RX Unit Transmit Signal Channel
• Outline
In the transmission channel, the desired frequency is
produced by direct oscillation, and is directly frequency
modulated by means of a varicap diode.
• Modulator circuit
The audio signal from the control unit is input to
microphone amplifier HIC IC7 (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminates unwanted high-frequency
components. The voltage-controlled oscillator (VF )
signal is directly frequency modulated by means of a
varicap diode in the frequency modulator circuit.
• Younger-stage circuit
The signal output from the VC is input to drive
circuit HIC ICS (KCB1 5). The amplifier can obtain a stable
drive output without adjustment because it has a large
bandwidth. An APC circuit controls the collector voltage
in the Younger final stage.
• Power amplifier circuit
The drive signal is input to power module IC10 and
amplified to the specified level.
220 TX-RX Unit PLL Synthesizer
The VC and PLL circuits are housed in a solid
shielding case as a hybrid integrated circuit. Compari 
son frequencies are produced by dividing a 12.8 MHz
reference oscillation frequency by 2248 and 2560 to
correspond to the 5,10,12.5,15,20, and 25 kHz channel
steps.
For 220 MHz, the relationship between f vco (RX) and
each frequency division ratio is given by
f vco =(220+30.825)={(nx128)+A}xf osc /R
Where: f vco =VC output frequency
n: Binary 10-bit programmable counter setting value
A: Binary 7-bit programmable counter setting value
f osc : Reference oscillation frequency of 12.8 MHz
R: Binary 1 0-bit programmable counter setting value
2560
In this case, n is 295, and A is 75.
Therefore, f vco ={{295x128)+75}x12800/2560
={33760+75)x5
= 189.175 MHz
The following table lists the pin functions of the PLL
circuit:
• APC circuit
The automatic transmission output control circuit
(APC) detects and partially amplifies the power amplifier
output with a diode and controls the output control
voltage. The control voltage is output in inverse proportion
to the output, so the control voltage output is always
constant.
• 8T (8 V during transmission) and unlock signal
A 0.7 V voltage is applied to the base of Q13 during
reception, Q1 3 is turned on, and Q14and Q1 1 are turned
off. No voltage appears at the collector (8T) of Q1 1.
Serial data is output from the control unit during trans
mission and input to shift register IC1 . Pin 4 of IC1 is
then
made low. Therefore, Q13 is turned off, and Q14
and Q1 1 are turned on. An 8 V voltage is applied to the
collector (8T) of Q1 1.
The unlock circuit is activated only during transmis 
sion. The LD pin signal output from the PLL circuit is
Red with the signal at pin 4 of IC1 using D1 1, as shown
in the figure, so the LD signal is made high during unlock.
Therefore, no voltage appears at the collector (8T) of
Q11, and no transmission signal is output during re 
ception.
IC2(KCH09)
Modulation input
0 V during locking
12.8 MHz i
Data input
Clock input
Enable input
Lock voltage
HET output
Fig. 15
Pin name
Function
Pin name
Function
5C
5V
M
Modulation signal
input
LD
Lock signal (0 V
during locking)
9C 9V
NC
Unused
8CL 8
V (ripple filter)
XI
12.8 MHz crystal NC
X
oscillation
CV
Lock voltage output
DP
Data input
E
GND
CP
Clock input
HT
HET output
EP Enable input
Table 16 PLL circuit pin functions
15

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
430 TX-RX Unit Frequency Configuration
The 430 MHz unit incorporates a digital variable-
frequency oscillator (VF ) that can freely select a
channel step of 5,10,12.5,15,20, or 25 kHz with a PLL
synthesizer system. The frequency in the receive
signal channel is mixed with a first local oscillation
frequency of 451.6-461.595 MHz (459.6-471.595 MHz
for K-models) to produce a first intermediate frequency
of 21.6 MHz. The frequency is then mixed with a
second local oscillation frequency of 21.145 MHz to
produce a second intermediate frequency of 455 kHz.
This is called a double-conversion system.
The signal in the transmission channel is directly
oscillated and frequency-divided by a PLL circuit,
amplified by a straight amplifier, then transmitted.
MCF ’
21.6MHz
455KHZ
430-439.995 MHz
(438-449.995
MHz)
RA
21.145MHz
451.6-461.595 MHz
(459.6-471.595 MHz)
M
430-439.995 MHz
TX AMP
ANT SW
MIC AMP
RF AMP
(438-449.995 MHz)
* The alphanumeric characters enclosed in
parentheses are used for K-models.
Fig. 16 Frequency Configuration
430 TX-RX Unit Receive Signal Channel
• Outline
A
430 MHz band antenna input signal is passed
through the antenna selection diode in the final stage
and sent through a front-stage antenna matching coil to
the high-frequency two-stage amplifierand helical block
of a GaAs (gallium arsenide) PET and junction FET. The
signal is then input to the first mixer. The first mixer
input signal is mixed with the first local signal from the
PLL circuit and converted to a first intermediate-
frequency signal of 21.6 MHz. The unwanted near-by
signal components are then eliminated by a two-stage
MCF.
The first intermediate-frequency signal is amplified
and input to FM IF HIC IC1 (KCD04). This signal is then
mixed with a second local oscillation frequency of
21.145 kHz to produce a second intermediate frequency
of 455 kHz. The unwanted near-by components of the
intermediate-frequency signal are eliminated by an FM
ceramic filter. The intermediate-frequency signal is
input to IC1 again. The second intermediate-frequency
signal is amplified and detected by IC1 to produce an
audio signal.
• Signal-strength meter
The signal-strength meter output voltage of FM IF
HIC IC1 (KCD04) is supplied to the control unit.
• Shift-register circuit
The ES, CK, and DT serial data from the control unit
are sent to IC3 (BU4094BF) to perform the control
operation outlined in the following table:
Pin No.
Name
Function
Pin No.
Name
Function
1
Strobe
Enable input
9
Qs
2
Data Serial
data input
10
Q's
3
Clock Clock
input
11
Q8
4
Q1
TX/RX selection. "L" when TX is set
12
Q7
5
Q2
TX power selection. "L" when middle and
low. "H" when high.
13
Q6
6
Q3
TX power selection. "L" when high and
low. "H" when middle.
14 Q5
7
Q4
15
E
8V
8
V ss
GND
16
V DD
8V
i
i
Table 17
16

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
430 TX-RX Unit Transmit Signal Channel
• Outline
In the transmission channel, the desired frequency is
directly oscillated and directly frequency modulated by
means of a varicap diode.
• Modulator circuit
The
audio signal from the control unit is input to
microphone amplifier HIC IC2 (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminate unwanted high-frequency
components. The VC signal is directly frequency
modulated
by a varicap diode in the frequency modulator
circuit.
• Younger-stage circuit
The signal output from the VC is input to drive
circuit HIC IC6(KCB1 4). The amplifier can obtain a stable
drive output without adjustment because it has a wide
band. An ARC circuit controls the collector voltage in the
younger final stage.
• Power amplifier circuit
A drive signal is input to power module IC7 and
amplified
to the specified level.
• APC circuit
The automatic transmission output control circuit
(ARC) detects and partially amplifies the power module
output with a diode and controls the output control
voltage. The control voltage is output in inverse
proportion
to the output, so the control voltage output
. is always constant. To protect the set against excessive
temperature rise, the high-power unit has a thermal
switch. The high-power unit is automatically set to a low
power by the thermal switch when it exceeds the
specified temperature.
»
430 TX-RX Unit PLL Synthesizer
The VC and RLL circuit are housed in a solid shielding
case as a hybrid integrated circuit. Comparison
frequencies of 6.25 and 5 kHz are produced by dividing
a 12.8 MHz reference oscillation frequency by 2048 and
2560 to correspond to 5, 10, 12.5, 15, 20, or 25 kHz
channel steps.
For 430 MHz, the relationship between f vco (RX) and
each frequency division ratio is given by
f vco = (430 + 21.6)= {(n x128) + A}x f osc R
Where: f vco = VC output frequency
n: Binary 10-bit programmable counter setting value
A: Binary 7-bit programmable counter setting value
fosc= Reference oscillation frequency of 12.8 MHz
8R
R: Binary 14-bit programmable counter setting value
2560 (in 5,10,1 5,and 20 kHz steps)
2048 (in 12.5 and 25 kHz steps)
In 5,10,15, and 20 kHz steps, n is 705 and A is 80.
Therefore, f vco = (705 x 128) x 12800 / 2560
= (90240 -1- 80} X 5
= 451600
= 451.6 MHz
See the 144 MHz band unit (X57-3580-00) for the
function of each pin of IC10 in the RLL circuit.
• 8T (8 V during transmission) and unlock signal
See the 144 TX/RX unit description on page 13. (The
figure on the under indicates the 430 MHz unit.)
8C
m m
tC3@ —
Shift register
I _____ I
Fig. 17
-8T
17

TM-742A/742B942A
CIRCUIT DESCRIPTION
TM-942A/UT-1 200 I
1200 TX-RX Unit Frequency Configuration
The 1200 MHz unit incorporates a digital variable-
frequency oscillator (VF ) thatfreely can select a channel
step of 10, 12.5, 20,or 25 kHz \A7ith a PLL synthesizer
system.
The frequency in the receive signal channel is mixed
with a frequency of 1200.3 to 1240.20 MHz obtained
when a first local oscillation frequency of 600.15 to
620.145 MHz is multiplied by 2 to produce a fist
1240~1299.99MHz
V
ANT S
PA TX AMP
intermediate frequency of 59.7 MHz. This frequency is
then mixed with a second local oscillation frequency of
59.245 MHz to produce a second intermediate
frequency
of 455 kHz. This is called a double-conversion
system.
The signal in the transmission channel is oscillated
and frequency-divided by a PLL circuit,then multiples
the frequency of 630 to 649.995 MHz by two to
produce a frequency of 1260 to 1299.99 MHz. This
signal is amplified by a straight amplifier, then
transmitted.
MCF
59.7MHz
rCZ
455KHZ
(R)
V S> / 1180.3-1240.
MIX,IF, DET
T -------
59.245 MHz
►ORA
29MHz
1240*1299. 99MHz
PLL MIC AMP
-OMO
Fig. 18 Frequency Configuration
1200 TX-RX Unit Receive Signal Channel
• Outline
The received signal from an antenna is passed
through a low-pass filter in the transmission final stage
and sent through a transmission/reception selection
diode switch to the receiving front end. The signal is
then amplified to high frequencies by a microwave
GaAs (gallium arsenide) PET and sent to a dielectric
filter. The unwanted components of the signal are
eliminated by a microwave transistor in another stage
and the dielectric filter. The resultant signal is input to
the first mixer. The front end block is matched by a
microstrip line to ensure high sensitivity and high
reliability. A GaAs FET is used in the first mixer to
obtain a good two-signal characteristic. This signal is
mixed with the first local signal from a PLL circuit
by the first mixer and converted to a first intermediate
frequency of 59.7 MHz. The unwanted near-by signal
components are eliminated by a two-stage MCF. The
resultant signal is produced as a first intermediate-
frequency
signal.
The first intermediate-frequency signal is amplified
and input to FM IF HIC IC2 (KCD04). This signal is then
mixed with a second local oscillation frequency of
59.245 kHz to produce a second intermediate
frequency of 455 kHz. The intermediate-frequency
signal is passed through a ceramic filter to obtain
a sharp characteristic. The signal is then input to an
HIC again, amplified, then demodulated and output
from the HIC.
• Signal-strength meter
The signal-strength meter output voltage of FM IF
HIC IC2 (KCD04) is supplied to the control unit.
• Shift-register circuit
The FS, CK, and DT serial data from the control unit
are sent to IC5 (BU4094BF) to perform the control
operation outlined in the following table:
i
i
18

TM-742A/742 E/942A
CIRCUIT DESCRIPTION
Pin No.
Name
Function
Pin No. Name
Function
Strobe
Enable input
Qc
Data Serial
data input
10
Q'c
Clock
Clock Input
11
Q8
TX/RX selection. "L" when TX is set
(Set low faster than Q1).
Q1
TX/RX selection. "L" when TX Is set
12 Q7 ALT. "H" when on.
Q2
TX power selection. "L" when middle and low.
"H" when high.
13 Q6
Q3
TX power selection. "L" when high and low.
"H" when middle.
14 Q5
Q4
15 QE
8V
GND
16
8V
Table 18
1200 TX-RX Unit Transmit Signal Channel
• Outline
In the transmission channel, the desired frequency is
oscillated by half and directly frequency modulated by
means of a varicap diode.
• Modulator circuit
The
audio signal from the control unit is input to
microphone amplifier HIC IC4 (KCA04). IC4 consists of
a preemphasis circuit, amplifier, limiter, and splatter
circuit that eliminate unwanted high-frequency
components. The VC signal is directly frequency
modulated by means of a varicap diode in the frequency
modulator circuit.
• Younger-stage circuit
The signal output from the VC is input to predrive
circuit IC7 (KCB09). The amplifier can obtain a stable
drive output without adjustment because it has a wide
band.
• Antenna selection circuit
Figure 19 shows the antenna selection circuit. The
receiver circuit obtains a low insertion loss and isolation
with a two-stage breaker circuit consisting of a V4 strip
circuit.
The pin diode used as a switching device has a low
junction capacitance. The high-frequency capacitance
of the diode does not depend on the reverse bias
voltage.
Figure 20 shows the equivalent circuit during
transmission. A current flows through each diode using
8T. The impedance becomes very low. At that time, the
receiver side uses a V4 strip circuit. Therefore, the
impedance becomes very high when the receiver side
is viewed from point (A). The voltage from a power
module
is transferred to the antenna.
Figure 21 shows the equivalent circuit during
reception. The bias is switched off, so each diode is
in a high-resistance state. The antenna and receiving
circuit are connected by a strip line.
I
• Power amplifier circuit
The signal amplified in the predrive stage is amplified
again by drive circuit HIC ICS (KCB10), then input to
power module IC1 0 and amplified to the specified level.
• APC circuit
The automatic transmission output control circuit
(APC) detects and partially amplifies the power module
output with a diode and controls the output control
voltage. The control voltage is output in inverse proportion
to the output, so the control voltage output is always
constant.
19