Kenwood NEXEDGE NXR-800 User manual

SERVICE MANUAL
© 2007-10 PRINTED IN JAPAN
B51-8795-00 (N)193
UHF DIGITAL BASE-REPEATER
NXR-800
This product uses Lead Free solder.This product complies with the RoHS directive for the European market.
MICROPHONE
VOLUME
COM OFF/
POWERCTRL OCXO BUSY TX
12
MON
TAKE
OVER
RPT
DISABLE
ABC
345678
STATUS
TEST/SPKR
RX TX
CONTROL I/O SYNC
12
LAN REF OUT REF IN
FUSE
75
DC 13.8V
Badge
(B43-1188-04)
Main panel
(A62-1142-02)
Knob (VOL)
(K29-4539-04)
Lead wire with
connector (DSUB-9P)
(E37-1311-05)
Lead wire with
connector (DSUB-25P)
(E37-1310-05)
Lead wire with
connector (BNC-RX)
(E37-1307-05)
Lead wire with
connector (ACC15)
(E37-1313-05)
Lead wire with
connector (BNC-REF.)
(E37-1304-05)x2
Modular jack
(E58-0526-05)
RF coaxial
receptacle (BNC)
(E04-0463-05)
Fanmotor
(F09-0488-05)
DC cord
(E30-7581-05)
Blade fuse
(F05-7521-05)
Cover (Fan)
(F07-1930-05)
Modular jack
(E58-0516-05)
Modular jack
(E58-0533-05)x2
CONTENTS
GENERAL........................................................... 2
SYSTEM SET-UP ............................................... 3
REALIGNMENT ................................................. 3
OPERATING FEATURES ................................... 5
INSTALLATION.................................................. 6
CIRCUIT DESCRIPTION .................................... 8
COMPONENTS DESCRIPTION....................... 24
TERMINAL FUNCTION ................................... 28
PARTS LIST ..................................................... 39
EXPLODED VIEW ............................................ 68
PACKING.......................................................... 70
ADJUSTMENT ................................................ 71
PC BOARD ....................................................... 82
BLOCK DIAGRAM ......................................... 104
INTERCONNECTION DIAGRAM .................. 108
SCHEMATIC DIAGRAM ................................ 112
OPTIONAL ACCESSORIES ........................... 136
SPECIFICATIONS ......................... BACK COVER

NXR-800
2
GENERAL
Document Copyrights
Copyright 2007 by Kenwood Corporation. All rights re-
served.
No part of this manual may be reproduced, translated,
distributed, or transmitted in any form or by any means,
electronic, mechanical, photocopying, recording, or other-
wise, for any purpose without the prior written permission
of Kenwood.
Disclaimer
While every precaution has been taken in the preparation
of this manual, Kenwood assumes no responsibility for er-
rors or omissions. Neither is any liability assumed for dam-
ages resulting from the use of the information contained
herein. Kenwood reserves the right to make changes to any
products herein at any time for improvement purposes.
Firmware Copyrights
The title to and ownership of copyrights for firmware
embedded in Kenwood product memories are reserved for
Kenwood Corporation. Any modifying, reverse engineer-
ing, copy, reproducing or disclosing on an Internet website
of the firmware is strictly prohibited without prior written
consent of Kenwood Corporation. Furthermore, any resell-
ing, assigning or transferring of the firmware is also strictly
prohibited without embedding the firmware in Kenwood
product memories.
NXDN Transceivers:
The AMBE+2(TM) voice coding technology is embedded
in the firmware under the license of Digital Voice Systems,
Inc.
INTRODUCTION
SCOPE OF THIS MANUAL
This manual is intended for use by experienced techni-
cians familiar with similar types of commercial grade com-
munications equipment. It contains all required service
information for the equipment and is current as of the pub-
lication date. Changes which may occur after publication
are covered by either Service Bulletins or Manual Revisions.
These are issued as required.
ORDERING REPLACEMENT PARTS
When ordering replacement parts or equipment informa-
tion, the full part identification number should be included.
This applies to all parts : components, kits, or chassis. If the
part number is not known, include the chassis or kit number
of which it is a part, and a sufficient description of the re-
quired component for proper identification.
PERSONAL SAFETY
The following precautions are recommended for personal
safety :
• DONOT transmit if someone is within two feet (0.6 me-
ter) of the antenna.
• DONOT transmit until all RF connectors are secure and
any open connectors are properly terminated.
• SHUT OFF this equipment when near electrical blasting
caps or while in an explosive atmosphere.
• All equipment should be properly grounded before pow-
erup for safe operation.
• This equipment should be serviced by only qualified tech-
nicians.
SERVICE
This transceiver is designed for easy servicing. Refer to
the schematic diagrams, printed circuit board views, and
alignment procedures contained within.

NXR-800
3
Merchandise received
Choose the type of transceiver
See page 3.
A personal computer (IBM PC or compatible), programming interface
(RS-232C Cross-cable), and programming software (KPG-109D) are
required for programming.
See page 75.
The RX RF BPF (L132~L135 on RX unit) must be aligned to obtain the
maximum sensitivity at a programmed frequency.
OCXO?
Repeater programming & setup
KXK-3 installation
YES
NO
Delivery
See page 6.
When using the Very Narrow Mode of the
NX-800 repeater, install the KXK-3 (OCXO).
(Option)
Frequency range RF power Type
TX/RX 450~480MHz 5W K
External speaker? KES-5 installation
YES
NO (Option)
See page 6.
REALIGNMENT
SYSTEM SET-UP
1. Modes
User mode
PC mode
Firmware programming mode
PC programming mode
PC test mode PC tuning mode
Mode Function
User mode Use this mode for normal operation.
PC mode
Use this mode to make various settings by
means of the FPU through the RS-232C
port.
PC programming
mode
Use to read and write frequency data and
other features to and from the repeater.
PC test mode Use to check the repeater using the PC.
This feature is included in the FPU.
Firmware program-
ming mode
Use when changing the firmware program
of the flash memory.
2. How to Enter Each Mode
Mode Operation
User mode Power on.
PC mode Received commands from PC.
Firmware programming mode Received commands from PC.
3. PC Mode
3-1. Preface
The NXR-800 repeater is programmed by using a personal
computer, programming interface and KPG-109D software.
3-2. Connection Procedure
1. Connect the NXR-800 to the personal computer with the
interface cable.
2. When power is applied, the user mode is entered imme-
diately. When the PC sends a command, the repeater en-
ters the PC mode and displays “PC” on the 17-segment
LED. When data is being transmitted to the PC from
the repeater, the TX LED flashes. The BUSY LED flashes
when data from the PC is being received by the repeater.

NXR-800
4
Note:
• The data stored in the personal computer must match the
model type, when it is written into the flash memory.
• Change the NXR-800 to PC mode, then attach the RS-
232C Cross-cable.
3-3. KCT-53U Description (USB adapter: Option)
The KCT-53U is cable which connects the RS-232C Cross-
cable to a USB port on a computer.
When using the KCT-53U, install the supplied CD-ROM
(with driver software) in the computer. The KCT-53U driver
runs under Windows 2000 or XP.
3-4. Programming Software Description
The KPG-109D is the programming software for NXR-800
supplied on a CD-ROM. This software runs under Windows
2000, XP or Vista on an IBM-PC or compatible machine.
The data can be input to or read from NXR-800 and ed-
ited on the screen. The programmed or edited data can be
printed out. It is also possible to tune the transceiver.
3-5. Programming With IBM PC
Data can be programmed into the flash memory in RS-
232C format via the COM connector.
NXR-800
Cross cable
IBM-PC
KPG-109D
Transceiver Transceiver
D-SUB
(9-pin)
RS-232C
Cross-cable
RS-232C
Cross-cable
PC
USB
KCT-53U
PC
Fig. 1
4. Firmware Programming Mode
4-1. Preface
The NXR-800 uses flash memory to allow it to be easily
upgraded when new features are released in the future.
4-2. Connection Procedure
Connect the NXR-800 to the personal computer (IBM PC
or compatible) with the RS-232C Cross-cable. (Connection is
the same as in the PC mode.)
Notes:
You can only program firmware from the DB-9 COM con-
nector on the front panel. Using the 25-pin logic interface
on the rear panel will not work.
4-3. Programming
1. Start up the programming software (Fpro. exe).
2. Set the communications speed (normally, 115200 bps)
and communications port in the configuration item.
3. Set the firmware to be updated by file name item.
4. Turn the NXR-800 power on.
5. Check the connection between the NXR-800 and the per-
sonal computer, and make sure that the NXR-800 is in the
program mode.
6. Press write button in the window. A window opens on
the display to indicate progress of writing.
7. If writing ends successfully, the NXR-800 restarts.
8. If you want to continue programming other NXR-800s,
repeat steps 3 to 6.
Notes:
It automatically enters the firmware program mode by the
writing request from the programming software (KPG-109D).
4-4. Function
Baud rate is decided automatically with setting of pro-
gramming software.
Note:
Normally, write in the high-speed mode (115200 bps).
REALIGNMENT

NXR-800
5
1. Two 17-segment LED Displays
• Channel display (1~30): While operating normally in user
mode.
• When the displayed channel is contained in scan se-
quence, the right side decimal point is displayed.
• When the displayed channel is the priority channel, the
left side decimal point is displayed.
• “PC” is displayed while in PC mode.
• “PG” is displayed while in firmware programming mode.
• “E1” is displayed when FPU data is not written.
• “E2” is displayed when the channel data is not written.
• “E3” is displayed when PLL is unlocked.
Receiver PLL unlocked = BUSY LED blinks.
Transmitter PLL unlocked = TX LED blinks.
• “E4” is displayed when PTT is attempted on a channel
number that has no frequency data programmed.
• “E5” is displayed when IP address configuration is error.
• “SC” is displayed while in scan mode.
A
All segments ON
BCDEFGH I
JKLMNOPQR
STUVWXYZ
ab cde f gh i
jklmnopqr
stuvwxyz
12345678
90#$%( ) =
|@+ *,./\
_- []
OPERATING FEATURES

NXR-800
6
INSTALLATION
1. OCXO (KXK-3)
1. Before installing the KXK-3, be sure to turn the power off.
2. Remove the top cover of the TX unit.
3. Mount the KXK-3 using the 5 screws.
4. Carefully connect and lock the flat cable to CN1 and
CN803, with the conductor side facing in.
5. Connect the coaxial cable to CN2 and CN407.
6. Connect the 2-pin cable to CN3 and CN807.
CN807
CN1
CN3
CN2
CN803
CN407
Conductor side
Fig. 1
2. External Speaker (KES-5)
The NXR-800 has a internal built-in speaker, and the ex-
ternal speaker output from the TEST/SPKR connector (15-
pin) on the rear of the radio is 3W/4Ω. Use external speaker
KES-5.
2-1. Connection for the KES-5 With the NXR-800
■When taking the AF output from the TEST/SPKR
connector (15-pin) on the rear of the radio
The following tools are required for changing the connec-
tor.
• Extracting tool
The following extracting tool is recommended:
Molex Inc. Order No.: 11-03-0002 (W05-0878-00)
1. Remove the connector with jumper from the external
speaker connector on the rear panel of the radio. (Fig. 2-1)
Note: Save the jumper, which is required when the radio
is used without the external speaker.
2. Remove the terminals with the jumper from the connec-
tor housing holes number 9 and 12 using the extracting
tool.
Removing the jumper lead (Fig. 2-2)
1) Insert the extracting tool (11-03-0002) into the connec-
tor while pushing the jumper lead in the direction of (a).
2) Push the extracting tool into collapse the barbs of the
crimp terminal.
3) Pull out the lead while continuing to push the extract-
ing tool in the direction (b).
3. Reinsert the terminal with the black and white stripe lead
into hole number 12, and the terminal with the black lead
into hole number 6. (Fig. 2-3)
4. Attach the connector to the external speaker connector
on the radio.
Notes:
• Relationship between TEST/SPKR connector (15-pin) con-
nection and speaker output.
• When pins 9 and 12 are shorted: Built-in internal speaker
is used.
• When pins 9 and 12 are open and output is from pins 6
and 12: KES-5 is used.
Square-type plug
(E31-3228-05)
Accessory
Fig. 2-1
Jumper lead
Crimp termial
Crimp termial
Barbs
Extracting tool
(11-03-0002)
(a)
(b)
Fig. 2-2

NXR-800
7
INSTALLATION
Crimp terminal
(E23-0613-05)
12
15
13
1
3
6
Black lead
Black/White lead
Fig. 2-3
3. How to Attach the Supplied Accessories
1. Attach the front glass to the front panel with the supplied
screw. (q)
2. To attach the handles on the both sides of the chassis,
refer to illustration. (w)
Front glass
Handle
Handle
:
@
@
Fig. 3

NXR-800
8
CIRCUIT DESCRIPTION
1. Outline
The NXR-800 is a UHF repeater operating in the 450~
480MHz frequency range.
2. Transmitter unit
The transmitter unit (X56-312 A/3) consists of the follow-
ing circuit.
(1) Internal/external reference circuit
(2) Transmitter reference 19.2MHz PLL circuit
(3) Transmitter Modulation 19.2MHz PLL circuit
(4) Transmitter DDS circuit
(5) Transmitter main PLL circuit
(6) Driver circuit
(7) Modulation level adjustment circuit
(8) AVR circuit
(9) Other circuits
2-1. Internal/external reference circuit
The internal/external reference circuit automatically
switches signals used as reference signals among the
5.99MHz internal DDS, the 10MHz external reference signal
and the 10MHz OCXO unit.
If no OCXO unit is installed, and there is no external refer-
ence signal, the 5.99MHz internal DDS (IC601) is selected
as the reference signal.
If the OCXO unit is installed and there is no external refer-
ence signal, the 10MHz OCXO unit is selected as the refer-
ence signal.
If an external reference signal (CN408/ 10MHz/ 0dBm or
higher/ Zin=50Ω) is input, the external reference signal is
selected as the reference signal irrespective of an existing
OCXO unit.
The internal/external reference circuit consists of Q419,
Q418, D401, D402, D405, D404, Q430, Q422, D601, IC405
and IC406.
The DDS circuit consists of X601, IC602, IC601, Q606,
CF601, Q603 and D602.
If either the OCXO 10MHz or external reference 10MHz
is selected as the reference signal, the reference output ter-
minal outputs the reference signal (CN403/ 10MHz/ +9dBm/
Zout=50Ω). This circuit consists of Q431, Q420 and Q425.
SW
OSC
X601
BUFF
IC602
BUFF
IC407
PLL IC
IC404
BPF
CF601
DDS
IC601 Q606
LPF
LPF
LPF
LPF
Q603
Q422Q430
LPF
Q425Q420Q431
Q419
D601
D602
SW
D404
D405
CN403
REF_OUT
CN408
REF_IN
CN407
OCXO
TX UNIT
2-2. Transmitter reference 19.2MHz PLL circuit
The transmitter reference 19.2MHz PLL circuit produces
a reference frequency signal for the transmitter modulation
19.2MHz PLL circuit, the Receiver unit (X55-310) Receiver
DDS circuit and the Control Unit (X53-414) DSP IC.
This circuit consists of Q401, Q402, Q412, Q415, Q416,
Q417, X401, IC401, IC404 and IC407.
The 5.99MHz or 10MHz signal produced by the internal/
external reference circuit is amplified by IC407 and supplied
to the PLL IC (IC404) reference signal pin.
The VCXO (X401) signal enters buffer amp Q417 and is
amplified by Q415. The higher harmonic wave is attenuated
by LPF and returns to IC404. Its phase is compared with
that of the reference frequency 10kHz.
The phase difference signal produced by the comparing
phase is converted to a DC voltage by a lag-lead type loop
filter. This DC voltage is input to the X401 control voltage
terminal for controlling the VCXO oscillating frequency.
The DC voltage passes through the IC401 operational am-
plifier, and is output as a voltage signal (CVT-REF) for moni-
toring the reference 19.2MHz PLL circuit lock voltage.
The stabilized 19.2MHz reference oscillating signal en-
ters the Q417 buffer amplifier and is amplified by Q412 and
Q416. The higher harmonic wave is attenuated by LPF, fed
to IC302 and used as the reference frequency signal for the
transmitter modulation 19.2MHz PLL circuit.
The 19.2MHz reference oscillating signal is also used as
the reference signal for the receiver unit (X55-310) and con-
trol unit (X53-414).
It enters the Q417 buffer amplifier for the receiver unit
(X55-310) and is amplified by Q401. The higher harmonic
wave is attenuated by LPF and is output from CN406.
It enters the Q417 buffer amplifier for the control unit
(X53-414) and is amplified by Q402. The higher harmonic
wave is attenuated by LPF and is output from CN405.
Fig. 1 Internal/external reference circuit

NXR-800
9
2-3. Transmitter modulation 19.2MHz PLL circuit
The transmitter modulation 19.2MHz PLL circuit produces
the reference frequency signal for the Transmitter DDS cir-
cuit and modulates the low-frequency components.
The circuit consists of IC302, IC303, IC305, IC306, X301,
Q304, Q305, and Q307.
The signal generated by the VCXO (X301) is fed to the
buffer amplifier Q307.
The VCXO (X301) signal enters buffer amplifier Q307 and
is amplified by Q305. The higher harmonic wave is attenu-
ated by the LPF and returns to IC303. Its phase is com-
pared with that of the reference frequency 5kHz.
The phase difference signal produced by the comparing
phase is converted to a DC voltage by a lag-lead type loop
filter. This DC voltage is input to the IC305 invert amplifier
(B/2) and is synthesized with the modulating signal. This
DC voltage is input to the X301 control voltage terminal for
controlling the VCXO oscillating frequency 19.2MHz.
The DC voltage passes through the IC306 operational am-
plifier, and is output as a voltage signal (CVT-MOD) for moni-
toring the modulating 19.2MHz PLL circuit lock voltage.
The 19.2MHz oscillating signal is fed to the Q307 buffer
amplifier and is amplified by Q304. The higher harmonic
wave is attenuated by the LPF, fed to IC307, and is used as
the reference frequency signal of the transmitter DDS cir-
cuit.
Q415
Internal
/External
Ref circuit
1/R
1/N
PD
Fref.=19.2MHz
R=1920
Fpd=10kHz
8V #2
Q417X401
8V #2
IC407
5V #3
Q416
5V #1
Q401
5V #2
Q402
5V #2
Q412
5V #18V #2
5V #3
5V #3
19.2MHz 19.2MHz
IC401
OP-AMP
28
6
5.99MHz
or
10MHz
IC404
PLL IC
CVT-REF
TX Mod
19.2MHz
PLL circuit
RX unit
Control
unit
CN406
19.2MHz
CN405
19.2MHz
Fig. 2 Transmitter reference 19.2MHz PLL circuit
Q305
TX Ref
19.2MHz
PLL circuit
1/R
1/N
PD
Fref.=19.2MHz
R=3840
Fpd=5kHz
8V #2
Q307X301
IC302
5V #2
IC305
5V #2 8V #2 8V #2
8V #2
5V #2
19.2MHz
IC306
OP-AMP
Q304
5V #2
28
6
19.2MHz
IC303
PLL IC
CVT-MOD
TX DDS
circuit
19.2MHz
Mod signal
Fig. 3 Transmitter modulation 19.2MHz PLL circuit
CIRCUIT DESCRIPTION

NXR-800
10
TX Mod
19.2MHz
PLL circuit IC307
5V #2
5V #1
19.2MHz
Q211
CF201
5V #1
4.5MHz
Q212
5V #1
Q213
5V #1
TX main
PLL circuit
4.5MHz
IC202
DDS IC ATT ATT
Fig. 4 Transmitter DDS circuit
2-5. Transmitter main PLL circuit
The transmitter main PLL circuit consists of the VCO
(Q102 and Q103), PLL IC (IC101), IC102, Q104 and Q106
and produces the transmitter frequency signal.
The VCO Q102 produces transmitter frequencies from
450.000MHz to 464.995MHz.
The VCO Q103 produces transmitter frequencies from
465.000MHz to 480.000MHz.
The signal produced by the VCO (Q102 or Q103) is fed to
the buffer amplifier and is amplified by Q106. The higher
harmonic wave is attenuated by LPF and returns to the PLL
IC (IC101).
IC101 divides the VCO oscillating frequency signal and
transmitter PLL reference signal (4.5MHz), and compares
the phase with the 100kHz comparison frequency.
The phase difference signal produced by the comparing
phase is converted to a DC voltage by a lag-lead type loop
filter.
The DC signal is applied to varicaps D101, D102, D107,
and D108 to lock the VCO oscillator frequency with the de-
sired oscillator frequency.
At the same time, the DC signal passes through the
IC102 operational amplifier for monitoring the transmitter
main PLL lock voltage.
The output from the VCO passes through the buffer am-
plifier Q104 and is supplied to the drive circuit.
Q106
TX DDS
circuit 1/R
1/N
PD
Fref.=4.5MHz
R=45
Fpd=100kHz
5V #2
Q104Q102
9V’ 9V’
9V’
5V #2
450~
464.995MHz
450~
480MHz
IC102
OP-AMP
49
6
4.5MHz
IC101
PLL IC
CVT
Driver
circuit
D108
D107D101
Q103
9V’ 465~
480MHz
D102
ATT ATT
Fig. 5 Transmitter main PLL circuit
2-4. Transmitter DDS circuit
The transmitter DDS circuit produces the transmitter
main PLL reference frequency signal 4.5MHz.
This circuit consists of IC307, IC202, CF201, Q210, Q211,
Q212 and Q213.
The 19.2MHz signal from the transmitter modulation
19.2MHz PLL circuit is amplified by IC307 and supplied to
the IC202 reference signal pin.
IC202 produces the transmitter main PLL 4.5MHz refer-
ence frequency signal based on 19.2MHz on signal.
The spurious output by IC202 is attenuated by CF201
and LPF, 4.5MHz reference frequency signal is amplified
by Q211, Q212, and Q213, and fed to the transmitter main
PLL.
The comparison frequency of the transmitter main PLL is
100kHz and the PLL frequency step is 100kHz.
However, minute frequency step such as 2.5kHz and
3.125kHz because the DDS output frequency is variable.
CIRCUIT DESCRIPTION

NXR-800
11
2-6. Driver circuit
The driver circuit amplifies the transmitter frequency sig-
nal to the level required for input to the Final Unit (X45-382
A/5).
This circuit consists of RF amplifiers Q201, Q202 and
Q203, switches Q204, Q205 and Q206, and operating am-
plifier IC201.
DC switches Q204, Q205, and Q206 turns the power
supply voltage of RF amplifiers Q201, Q202, and Q203 on
and off.
The transmitter main PLL circuit output is attenuated by
attenuators R201, R202 and R203, by approximately 7dB.
So, the input level to Q201 is approximately -12dBm (63µW).
Q201 amplifies it by approximately 12dB. So, the output
level is approximately 0dBm (1mW).
The Q201 output is amplified by Q202 by approximately
10dB. Furthermore, it is amplified by Q203 by approxi-
mately 10dB. The Q203 output is approximately +20dBm
(100mW). This output level is output from driver output con-
nector CN802 and is connected to the Final Unit (X45-382
A/5).
Q203 has an AGC (Auto Gain Control) circuit. D201 recti-
fies a part of the Q203 output and converts it into DC volt-
age. It is compared with the control voltage (D_PC) by the
operation amplifier IC201. The Q203 Gate terminal voltage
is controlled for the stabilizing Q203 output (+20dBm).
Q201 Q203
TX main
PLL circuit
Q202
8V #1
Final
unit
D201
ATT
SW
450~
480MHz
D_PC
IC201
(A/2)
IC201
(B/2)
8V #1’
CN802
450~480MHz
+20dBm
8V #1’
Q204~206
Fig. 6 Driver circuit
2-7. Modulation level adjustment circuit
The level adjustment circuit adjusts the modulation signal
level to provide the required level of modulation. This circuit
consists of IC301, IC304, IC305, and IC308.
The audio signal comes from the Control Unit (X53-413)
through pin 4. The modulating signal is input to IC304 from
this.
IC304 is an electronic volume control IC.
The modulation waveform balance adjustment, maximum
AF Dev. change, and adjustment are performed according
to data from the MPU using the FPU.
The modulation signal is produced by the modulating low-
pitched tone to the transmitter modulation 19.2MHz PLL cir-
cuit and adds the high-pitched modulation to the transmitter
main PLL.
IC305 is an inverting amplifier (B/2) for inverting the am-
plification (A/2) of the modulating signal and synthesizing
the VCXO (X301) control voltage and modulating signal.
IC301 is a reference voltage generator (A/2) in modulat-
ing level adjusting circuit and non-inverting amplification of
modulating signal with a cutoff signal of approximately 9kHz
(B/2).
Control
unit
TX Mod 19.2MHz
PLL circuit
VCXO_CV
TX main
PLL circuit
VCO_MOD
Mod
signal
CN804
41
IC304
IC308 (B/2)
5V #2 IC301
(B/2)
5V #2
IC305
(A/2)
IC305
(B/2)
5V #2
5V #2
5V #2
TX Mod 19.2MHz
PLL CP
3
2
10
Fig. 7 Modulation level adjustment circuit
CIRCUIT DESCRIPTION

NXR-800
12
2-8. AVR circuit
IC104, IC603, IC704, IC705, IC706, IC807, IC808 and
IC809 are AVR ICs.
Each circuit contains its own power regulator IC to main-
tain isolation between circuits.
2-9. Other circuits
In addition, IC701 is an EEPROM. The transmitter ad-
justment data adjusted for each unit is written into the
EEPROM. If the unit is installed in another set, it is not nec-
essary to adjust it again from the beginning, but only fine-
tuning is necessary for each unit.
The temperature sensor (IC804) monitors the tempera-
ture of the transmitter unit (X56-312 A/3).
The D/A converters (IC701 and IC802) converts the AGC
setting (D_PC) of the driver circuit and control voltage value
(PWR_CONT, PWR_PRT) of the Final Unit (X45-382 A/5).
The A/D converter (IC803) converts the transmitter unit
(X56-312 A/3) temperature, VCO & VCXO control voltage
(CVT, CVT-REF and CVT-MOD), Final Unit (X45-382 A/5) PA
current(PA_CURR), fan current (FAN_CURR), detection volt-
age (FWD_PWR, RFL_PWR), etc.
The shift register (IC703) controls each part of the trans-
mitter unit (X56-312 A/3) based on serial data of the Control
Unit (X53-413).
CN801
VBATT +13.8V IC704
IC809
SW
Ripple
filter
IC807
IC706
IC705 IC603
IC104
IC808 8V #1
8V #2
8V
9V
CN807
8V #2
OCXO
9V’
8V #1
8V #1’
5V #1
5V #2
5V #3
3.3V
Fig. 8 AVR circuit
3. Final unit
The RF final amplifier unit (X45-382 A/5) amplifies the
transmitter power to a specified level.
This unit consists of the following circuits:
(1) Transmitter power module
(2) High pass filter
(3) Forward/Reflect power detector circuit
(4) Antenna switch
(5) Harmonic filter circuit
(6) APC circuit
(7) High temperature detector circuit
(8) FAN action control circuit
(9) Current detector circuit
(10) AVR Circuit
(11) Other Circuits
3-1. Transmitter power module
The power module IC10 uses power module RA13H4452
M101 to improve its efficiency. The driver output of the
transmitter unit passes through an attenuator and enters the
power module IC10 pin 1. Power module IC10 amplifies
the RF power according to the voltage at the amplification
control pin 2 (VGG) and outputs it through pin 4 (Pout).
RA13H4452M101
:Pin @VGG .VDD ;Pout
Fig. 9 Transmitter power module
3-2. High pass fileter
The T type single stage high pass filter prevents the Pow-
er Amplifier Module from being broken by static electricity.
CIRCUIT DESCRIPTION

NXR-800
13
3-3. Forward/Reflect power detector circuit
The forward / Reflect power detector circuit consists of a
CM coupling type detection circuit formed by a Micro strip
line and the differential amplifier IC4.
A part of the transmitter power is detected by diodes D9
and D10 and is converted into DC voltage.
ATT
IC4
Diff. AMP D10
DET
ATT
D9
DET
Reflect
Foward
Directional coupler
Fig. 10 Forward/Reflect power detector circuit
3-4. Antenna switch
If a common antenna is used for the transmitter signal
and receiver signal, switch transmitter and receiver signals
by connecting CN19 to the RX Unit.
If different antennas are used for the transmitter and re-
ceiver, it functions as an On/Off switch for the transmitter
circuit.
3-5. Harmonic filter circuit
The harmonic filter circuit uses a three-stage “pi” type
Chebyshev type LPF.
This circuit removes harmonics from the transmitter out-
put and sends the filtered signal to the antenna connecter
(CN22).
3-6. APC circuit
The APC circuit stabilizes the transmitter power so that
the output power specified by the Control Voltage from the
MPU is obtained. It consists of a Forward/Reflect power
detector circuit and Differential amplifiers (IC2 and IC5).
It compares the voltage detected by the Forward/Reflect
power detector circuit (voltage detected by the Forward
Power) and the Control Voltage (PWR_CONT) from the
MPU (IC802: X56-312 A/3). It stabilizes the output power
by changing pin 2 (Vgg).
The voltage detected (that detected Reflect Power) by
the Forward/Reflect power detector circuit is compared to
the Control Voltage (PWR_PRT) from the MPU (IC802: X56-
312 A/3). When a load V.S.W.R. is connected to the An-
tenna Connecter and is more than 1.5, it functions so that
the output power gets smaller as the detection voltage (that
detected Reflect Power) gets larger.
3-7. High temperature detector circuit
The high temperature detector circuit consists of a ther-
mal switch IC (IC7) and a switching FET (Q2).
This circuit lowers the transmitter power when the final
unit temperature is too high (83°C or higher).
Q2
SW
Pout
VDDVGG
Pin
IC10
RA13H4452M101
IC7
Temp
protection
IC
Fig. 12 High temperature detector circuit
ATT
IC4
Diff. AMP
D10
DET
ATT
D9
DET
Reflect
Foward
IC5
Add. AMP
Diff. AMP
IC2
Diff. AMP
Directional coupler
HPF
Pout
VDDVGG
Pin
IC10
RA13H4452M101
+
PWR_PRT
PWR_CONT
Fig. 11 APC circuit
CIRCUIT DESCRIPTION

NXR-800
14
3-8. FAN action control circuit
The FAN action control circuit consists of a FAN, a current
detection resistance (R11), a Differential amplifier (IC15), a
Switching FET (Q3), and a Switching FET (Q14). It detects
the normal and abnormal state by monitoring the current
flowing FAN motor, and stops operation when failure oc-
curs.
Q3
SW
M
Q14
SW
IC12
AVR
IC15
Diff. AMP FAN_CURR
FAN_CONT
VBATT
R11
Fig. 13 FAN action control circuit
3-9. Current detector circuit
The current detector circuit monitors the current of the
Power Amplifier Module. It consists of a current detection
resistance (R4) and a current detection IC (IC1). It detects
the normal and abnormal state of the Power Amplifier Mod-
ule by monitoring the current of the Power Amplifier Mod-
ule. If a failure occurs, it stops operation.
IC1
Current
sense IC
PA_CURR
R4
Fig. 14 Current detector circuit
3-10. AVR circuit
IC3, IC11 and IC12 are AVR ICs.
They maintain isolation of each power supply.
+8V
IC11
+5V
IC12
+5V OP AMP
OP AMP
IC3
SW
Q4,5
SW
Q3,14
ANT SW
Temp
protection IC
FAN
Power amplifier
module
CN2
+VBATT
IC2,5,8
IC10
IC6
IC7
Fig. 15 AVR circuit
3-11. Other circuits
Circuit IC9 saves various adjustment values of the Final
Unit in the EEPROM.
4. Receiver Unit
The receiver unit (X55-310) consists of the following cir-
cuits:
(1) Front-end circuit
(2) 1st-Mixer circuit
(3) 1st-IF circuits
(4) Demodulator circuits
(5) Squelch circuit
(6) Receiver DDS circuit
(7) Receiver PLL circuits
(8) AVR circuit
(9) Other circuits
There are four modulating modes that can receiver de-
modulate, including Analog_Wide, Analog_Narrow, NXDN_
Narrow, and NXDN_Very-Narrow.
4-1. Front-end circuit
The front-end circuit consists of L132 and L133 helical
BPF, Q1 Low Noise Amplifier (LNA), and L134 and L135 he-
lical BPF. Adjusting four helical BPF forms the BPF having a
pass band width of 5MHz with a center frequency from 450
to 480MHz.
+9V is applied to the Q1 collector power supply. -3V pro-
duced by IC701, IC702 and IC703 mounted on a negative
power unit (X45-382 D/5) is applied to the emitter power
supply. The collector current is monitored by the IC4 cur-
rent detection circuit. Detected DC voltage is input to pin
15 of IC30 (ADC).
BPF
L132,133
BPF
L134,135
Q1
LNA
IC4
IC30
+9V
15
RX ANT
CN5
RX unit
X55-310
IC701
+9V IC702 +5V IC703 –5V –3V
Power supply unit
X45-382 D/5
CN701
Fig. 16 Front-end circuit
CIRCUIT DESCRIPTION

NXR-800
15
4-2. 1st-Mixer circuit
The unwanted out-of-band RF components produced by
Q1 are attenuated by the BPF. Only the desired signal is
transmitted to the A1 Double Balanced Mixer (DBM). Here,
the desired signal is mixed with the first hetero signal.
49.95MHz is produced as the 1st Intermediate Frequency
(IF1).
BPF
L134,135
A1
Mixer IF1
49.95MHz
1st local
400.05~430.05MHz
Fig. 17 1st-Mixer circuit
4-3. 1st-IF circuits
The IF1 signal produced by the 1st-Mixer circuit is trans-
mitted through either one of two 1st-IF circuits with differ-
ent bandwidth. The signal passes through the WIDE band
consisting of D9, XF1, Q19, XF3, Q28 and D13 only in Ana-
log_Wide mode. Meanwhile, the signal passes through the
NARROW band consisting of D10, XF2, Q20, XF4, Q29, and
D14 only in Analog_Narrow, NXDN_Narrow or NXDN_Very-
Narrow mode.
XF1 and XF2 is 2 pole and XF3 and XF4 are 4 pole Mono-
lithic Crystal Filters (MCF). They are BPF for removing spu-
rious noise occurring close to the desired signal. The DC
switch consists of Q31, Q32, Q26 and Q25, switches the
WIDE and NARROW bands of the 1st-IF circuits.
D9
SW
D13
SW
Q25
SW
Q32
SW
Q31
SW
Q26
SW
L46,52
XF1
L74,90
XF3
Q19 Q28
Analog Wide
8WR
8WR
D10
SW
D14
SW
L47,53
XF2
L75,91
XF4
Q20 Q29
Analog Narrow
NXDN Narrow
NXDN Very-Narrow
8NR
8NR
+8V
IF_SW
4-4. Demodulator circuits
The desired signal that passed through the 1st-IF circuits
passes through the distributor consisting of LC parts and is
fed to the IF system IC_IC12, IC13. The signal in Analog_
Wide or Analog_Narrow mode is mixed with the second
local oscillator hetero signal by the mixer in IC12. 450kHz is
produced as the 2nd Intermediate Frequency (IF2).
It passes through D15, CF2, D16, D19, CF5 and D20 path
if the modulation mode is Analog_Wide. It passes through
D15, CF3, D16 and D19, CF7 and D20 path if the modulation
mode is Analog_Narrow. The base band signal FM-detected
by the quadrature detection circuit consisting of L128, Q57,
and Q58 and is amplified to a signal level of approximately
100mVrms by IC20 and is then transmitted to the control
unit (X53-413) from CN42 (pin12).
The signal in NXDN_Narrow or NXDN_Very-Narrow mode
is mixed with the second local oscillator hetero signal by the
mixer in IC13. 450kHz is produced as the 2nd Intermediate
Frequency (IF2). Here, irrespective of modulation modes,
it passes through the CF4 and CF6 path. It is transmitted
as the base band signal via IC14 to the CN43 control unit,
X53-414.
CF2, CF3, CF4, CF5, CF6 and CF7 are hexode Ceramic
Filters. They are BPF for removing spurious noise occurring
close to the desired signal.
Fig. 18 1st-IF circuits
CIRCUIT DESCRIPTION

NXR-800
16
4-5. Squelch circuit
The desired noise of the noise component output from IF
system IC_IC12 (pin18) is extracted by the BPF. After pass-
ing through Q40, it is DC-detected as the squelch voltage by
D17, D18 and input to ADC_IC30 (pin11).
The MPU mounted in the control unit (X53-413) compares
it with a predetermined reference voltage and turns the Au-
dio signal on and off. The strength of the receiver signal in-
put from CN5 is output as the RSSI voltage from IF system
IC_IC12 (pin21), and is input to_IC30 (ADC) pin12 via IC29
A/2.
4-6. Receiver DDS circuit
The 19.2MHz Internal reference clock produced by trans-
mitter unit (X56-312 A/3) is distributed to CN45 of the re-
ceiver unit (X55-310). It passes through Q39, Q30, and IC8,
and is input to IC7 (DDS-IC) pin6 as the Master clock. Ap-
proximately 6MHz signal is generated as the 1st-PLL Refer-
ence clock.
IC7 has a resolution of 32 bits for realizing the frequency
step minters than the 1st-PLL comparison frequency. The
generated Reference clock is output via Q12, CF1, and Q5.
CF1 is a Ceramic Filter. It is the BPF for removing unneces-
sary spurious noise included in the generated Reference
clock.
D15
SW
D16
SW
CF2
CF3
D19
SW
D20
SW
DET
CF5
CF7
QUAD
10
864
15
17 IC20
(A/2)
Q40
IC29 (A/2)
D17,18
IC30
11 18
12
1821
24
1
48 10
DIV
2nd local
49.5MHz
2nd local
49.5MHz
6
CF4
CF6
14
5DR
3DR
5NR
Analog Wide
Analog Narrow
NXDN Narrow
NXDN Very-Narrow
IC12
IC13
IC14
CN42
12
22
CN43
LPF LPF LPF LPFBPF
+5V
Q5
+5V +5V
Q12
+5V
Q30
+5V
Q39
CF1
IC7
DDS
14 6
+5V
IC8
15
DIV CN45
Fig. 19 Demodulator circuits
Fig. 20 Receiver DDS circuit
CIRCUIT DESCRIPTION

NXR-800
17
4-7. Receiver PLL circuits
The receiver unit (X55-310) has the 1st-PLL circuit for
controlling the VCO that generates the hetero signal to the
first local oscillator, and the 2nd-PLL circuit for controlling
the VCO that generates the hetero signal to the second lo-
cal oscillator.
The 1st-PLL circuit consists of the VCO (Q7 and Q8), the
Buffer amplifier (Q17), the RF amplifiers (Q16 and Q3), the
PLL-IC (IC5), the Active loop filters (Q2 and Q4) and the
Band switches (Q14, Q10, Q11 and Q59). The signal in the
400.05 through under 415.05MHz band generated by VCO
Q7 and the 415.05 through 430.05MHz band generated by
VCO Q8 is input to IC5 (pin5) via Q17 and Q16 as the Fin
signal. The 6MHz reference signal generated by the DDS-
IC (IC7) is input to IC5 (pin8) via Q3. Two signals, Fin and
REFin, are phase-compared as the 100kHz comparison fre-
quency by each frequency divider. The VCO output with the
frequency synchronized is input to the 1st-Mixer as the first
local oscillator Lower hetero signal approximately +17dBm
via Q17, Q23, and Q18. The control voltage is input to IC30
(ADC) pin16 via IC6.
Meanwhile, the 2nd-PLL circuit consists of the VCO (Q24),
the Buffer amplifier (Q33), the RF amplifier (Q38, Q22), and
the PLL-IC (IC11). The 99.0MHz signal generated by Q24 is
input to IC11 (pin5) as the Fin signal via Q38. The 19.2MHz
Internal reference clock distributed by the transmitter unit
(X56-312) is input as the REFin signal to IC11 (pin8) via Q22.
Two signals, Fin and REFin, are phase-compared by each
frequency divider as the comparison frequency of 200kHz.
The VCO output with the frequency synchronized is input to
IC9 (prescaler IC) pin2 via Q33 and Q21. The 49.5MHz sig-
nal is frequency-divided into halves by IC9 and is excited by
Q53 and distributed. One is input to IC12 (pin1) via Buffer
amplifier_Q35. The other is input to IC13 (pin4) via Buffer
amplifier_Q36. Both are input as approximately -16dBm for
the second local oscillator Lower hetero signal. The control
voltage at this point is input to IC30 (ADC) pin10 via IC33.
Q17
1/N
1/R
PD
+5V
+5V
+9V
Q3
+5V
20
8
IC5
5
Fin
LPF
LPF
Q16
+9V
LPF
Q23
+9V
Q18
REFin
+9LV
+9LV
+9LV
+9LV
SW
Q10
SW
Q11
Q7
400.05~415.05MHz
Q8
415.05~430.05MHz
Div.
Active
LPF
IC6 16 IC30
ADC IC9
1/2
IC33 10 IC30
ADC
Q2,4
Q33
1/N
1/R
PD
+5V
+5V
+9R
Q22
+5V
20
8
IC11
5
Fin
LPF
LPF
LPF
LPF
LPF
LPF
Q38
+5V
Q21
+5V+3V
Q53
+5VA
Q35
+5VD
Q36
REFin
Div.
Div.
ATT
ATT
ATT
ATT
Q24
99.0MHz
27
49.5MHz
SW
SW
Q14
Q59
4-8. AVR circuit
The power supply voltage supplied from the power unit
(X45-382 C/5) is distributed from the receiver unit (X55-310)
CN44 to IC24 (8V), IC25 (8V), IC26 (9V), and IC27 (9V) via
the Q52 DC switch. The output of IC24 is supplied to the
1st-IF circuits, the 1st-Local amplifiers and the IF system IC_
IC12 via IC15 (5V). Further, the output of IC25 is distributed
to IC16 (5V), IC17 (5V), IC18 (5V) and IC19 (5V). The output
of IC16 is supplied to IF system IC_IC13. The output of
IC17 is supplied to the 2nd-Local amplifiers. The output of
IC18 is supplied to the 1st-PLL and the 2nd-PLL. The output
of IC19 is supplied to the DDS circuit. The output of IC26 is
supplied to LNA_Q1. The output of IC27 is supplied to the
VCO buffer amplifiers_Q17, Q33, the 1st-VCO and the 2nd-
VCO via Active ripple filters_Q9, Q27, and to the Active loop
filter_Q2, Q4 via the Active ripple filters_Q6.
Fig. 21 Receiver PLL circuits
CIRCUIT DESCRIPTION

NXR-800
18
SW +8V
+5V
CN44
+B Q52
SW
Q32
IC24
+5V
IC16
+5V
IC17
+5V
IC18
+3V
IC10
+3.3V
IC22
+5V
Q9
Q27
Q6
IC19
+8V
IC25
Q18,23
1st local amplifiers
IC14
2nd IF amplifier
IC19
Pre-scaler
Q21,53
2nd local amplifiers
IC13
IF systemIC
Q19,28
WIDE pass
SW
Q25
Q20,29
Narrow pass
IC15
IC12
IF system IC
Q1
LNA (Collector)
Q1
LNA (Emitter)
+9V
IC26
+9V
IC27
+5V
IC701
–5V
IC702
–3V
IC703
IC5,11
1st/2nd PLLʹs
IC7
DDS
Q17,33
1st/2nd VCO buffer amplifiers
Q7,8
1st local VCOʹs
Q24
2nd local VCO
Q2,4
active loop filter
4-9. Other circuits
Other circuits include the EEPROM (IC31), the temper-
ature sensor IC (IC35), the DAC (IC23) and the ADC (IC30).
IC31 saves various adjustment values of the receiver unit.
IC35 is built-in for detecting changes in temperature. IC23
offsets the RSSI voltage (pin1) (detected by the IF system
IC (IC12)) and the 1st-VCO_A, VCO_B control voltage (pin2,
pin3).
IC30 monitors the 1st-VCO control voltage (pin16), the
LNA current detection value (pin15), the temperature de-
tected by the temperature sensor IC (IC35 pin14), the RSSI
voltage detected by the IF system IC (IC12 pin12), the
squelch voltage detected by the IF system IC (IC12 pin11),
and the control voltage of the 2nd-VCO (pin10), and outputs
each state in serial data (IC30 pin18), sends the signal from
CN42 (pin22) to the control unit (X53-413). The signal is pro-
cessed by the MPU.
IC33
2nd CV
IC32
A/2
1st
VCO_A
1st
VCO_B
IC12
ASQL
IC35
TEMP.
IC6
1st CV
IC12
RSSI
IC4
LNA
10 18
11
12
14
15
16
IC30
IC31
EEPROM
5
6
1
2
6
7
8
3
IC23
CN42
11
9
8
22
32
30
Fig. 23 Other circuits
Fig. 22 AVR circuit
CIRCUIT DESCRIPTION

NXR-800
19
5. Base-Band Signal Processing Part
The base-band circuit is located on unit X53-413. This
circuit enables the selection of the Analog Signal Processing
mode and the Digital Signal Processing mode, and adjusts
the level of the base-band signals in each mode. This circuit
consists of IC2, IC3, IC5, IC8, IC9, IC12, IC14, IC19, IC20
and IC21.
The type of input modulation signals are local microphone
terminal, low-speed data (LSD), high-speed data (HSD), ex-
ternal audio input (TA), and external data input (TD), and also
the type of output demodulation signals are receiving audio
output (RA), and receiving data output (RD).
The multiplexer (IC2, IC3, IC14) selects the signal path,
the electronic volume (IC8) adjusts the signal level, and the
operational amplifiers (IC5, IC9, IC12, IC19, IC20, and IC21)
amplify and sum various signals.
5-1. Demodulation circuit
(Analog/NXDN signal processing)
In case of the Analog Signal Processing mode, the de-
tected audio signal obtained from the IF SYSTEM IC (X55-307
IC8) is amplified by IC5 (A/2), input into the AINR terminal
of CODEC IC (IC4), and then processed as an audio signal
by the DSP (IC37). The processed audio signal from the
AOUTR terminal of IC4 is amplified to a sufficient level by
IC12 (A/2), and is then passed through the anti-aliasing filter
at IC12 (B/2).
In case of the NXDN Signal Processing mode, the de-
tected audio/data signal obtained from the IF SYSTEM IC
(X55-307 IC7) is input into the ADC (X53-414 IC312). Re-
ceiving signal processing is performed by RX_DSP (X53-414
IC323), and voice decode processing is performed by TX_
VOCODER DSP (X53-414 IC324). The processed audio sig-
nal from the AOUTL terminal of CODEC IC (X53-414 IC309)
is amplified to a sufficient level by IC20 (D/4), and is then
passed through the anti-aliasing filter at IC20 (C/4).
The audio signal path is selected by multiplexer (IC14)
depending on the Analog mode (IC14 is setting Y=Y0) or
the NXDN mode (IC14 is setting Y=Y1). The audio signal
is then routed through an electronic volume (IC8) V3/V4 to
multiplexer IC (IC25), and is amplified to a sufficient level to
drive the loudspeaker using an audio power amplifier (IC29).
5-2. Audio amplifier aircuit
The audio amplifier circuit is located in the control section
of the Control unit (X53-413).
The 3W output audio power is available from the pin15
test connector “SPO, SPG” on the rear panel to the external
speaker in the case of a 13.8V power supply voltage and 4
ohm load.
5-3. Microphone circuit
The signal from the microphone is passed through the
AGC circuit located in the DISPLAY circuit (X56-312 B/3)
so that it may not saturate. This circuit consists of IC926,
D933, D934 Q931, and Q932. The AGC controls the ampli-
fier gains using the detected audio signal depending on the
positive and negative peaks of the signal amplitude. The
audio signal goes to the control section of the Control unit
(X53-413) from the DISPLAY circuit (X56-312 B/3).
5-4. Modulation circuit
(Analog/NXDN signal processing)
The transmitting audio signal goes to the input terminal of
the multiplexer IC (IC3) for microphone muting.
In case of the Analog Signal Processing mode (multiplexer
IC3 is setting X=X0), the audio signal is amplified by IC9 (A/4),
input to the AINL terminal of the CODEC IC (IC4), and audio
processed by the DSP (IC37). The processed audio signal
from the the AOUTL terminal of IC4 is amplified to a suf-
ficient level by IC9 (B/4), and is then passed through an anti-
aliasing filter at IC9 (C/4), and amplified by the summing (TD)
amplifier IC9 (D/4).
On the other hand, in the case of the NXDN Signal Pro-
cessing mode (multiplexer IC3 is setting X=X1), the audio
signal is amplified by IC20 (A/4), input to the AINL terminal
of the CODEC IC (X53-414 IC309), and processed by the
TX_VOCODER DSP (X53-414 IC324). The processed audio
signal from the AOUTR terminal of IC309 passes through
the anti-aliasing filter at IC19 (B/2).
6. Control Circuit
The control circuit consists of two units, X53-413 and
X53-414.
Unit X53-413 mainly has the power supply circuit, base-
band signal path selection circuit (level adjustment is in-
cluded), analog mode voice codec circuit, and RF controller
circuit.
Unit X53-414 has the mode selection (analog or NXDN)
circuit, NXDN mode communication processing circuit, LAN
interface circuit, and Compact Flash interface circuit.
6-1. X53-413
■RF control MPU
The IC34 RF control MPU is a 16-bit single chip micropro-
cessor incorporating 256Kbite of ROM and 20Kbite of RAM.
This MPU controls the Flash ROM, DSP, receiver unit,
transmitter unit, and EEPROM of each unit, and the display
circuit, and has communication I/F with external devices.
■DSP
The DSP circuit is in charge of the filtering of transmitting
and receiving signals, and the encoding and decoding of
sub-audible signals (encode: QT, DQT, DTMF, decode : QT,
DQT, DTMF).
This circuit consists of IC37, IC30, IC31, IC4, IC5, IC9,
and IC12.
The receiving signal, DET is converted from analog to
digital by IC4 with a sampling frequency of 16.128kHz. The
digitized audio signal is sent to the DSP (IC37) to process
the sub-audible signal and audio signal. The processed digi-
tal audio signal is applied to CODEC IC4, and is converted
from digital to analog. The analog signal is output from
pin16 (AOUTR). The audio signal is then amplified by IC12
(A/2), passes through the low-pass filter at IC12 (B/2), is se-
lected by the multiplexer IC14 (Y0=Y) and is then input into
an electronic volume IC8.
CIRCUIT DESCRIPTION

NXR-800
20
On the other hand, the transmitting audio signal output
from IC3 is amplified by IC9 (A/4), applied to pin 3 (AINL)
of CODEC IC4, and is then converted from analog to digital
at a sampling frequency of 16.128kHz. The digitized trans-
mitting audio signal is AGC-processed, pre-emphasized
and filtered, except for the 300Hz to 3kHz range, by DSP
IC37, and is then feed back to CODEC IC4, converted from
CODEC IC
IC4: AK4550VTP
RX detected signal (AINR) (AOUTR)
(AOUTL)
(AINL)
RD
TA
TX modulation signal
Local Mic
2
3
REPEAT
RX
TX
16
15
TD
RA
RX audio amp.
TX VCO
(Modulation circuit)
300Hz 3kHz
[Frequency response]
RX
TX
REPEAT
(De-emphasis)
(Pre-emphasis)
(300Hz~3kHz Flat)
digital to analog, and the analog signal is output from pin15
(AOUTL). The transmitting signal from the AOUTL is am-
plified by IC9 (B/4), passed through the IC9 (C/4) low-pass
filter, and sent to the IC9 (D/4) summing amplifier.
IC31 is a counter IC. The clock required for the CODEC
and DSP is generated by dividing the 16.515072MHz clock
signal supplied by the DSP IC37.
■Shift register circuit
The MPU (IC34) transmits serial data to shift registers
IC923 from IC923 to IC960 and from IC960 to IC963 in the
display circuit (X56-312 B/3, C/3).
Additionally, it transmit serial data to the control unit (X53-
413) IC1 and IC22 and the transmitter unit (X56-312) IC703.
This serial data can control various functions of each unit.
■Power supply circuit
This circuit consists of X53-413 IC6, IC10, IC11, IC15,
IC16 and 18, and X53-414 IC305, IC306, IC307 and IC329.
IC10 is a DC/DC converter that converts 13.8V to 5.0V.
IC11 is a DC/DC converter that converts 13.8V to 8.0V. IC16
is the 5.0V AVR and connected to IC10. IC6, IC15, IC305
and IC329 is the 3.3V AVR. IC18 is the 1.8V AVR. IC306 is
the 1.5V AVR. IC18 and IC306 is connected to IC329.
■Flash ROM (RF control MPU)
IC17 is an 8M bit Flash ROM and contains MPU firmware
for controlling the RF.
■EEPROMs circuit
The EEPROM is a built in receiver unit (X55-310), trans-
mitter unit (X56-312) and Final unit (X45-382).
The RF control MPU controls these EEPROMs by the IIC
bus.
6-2. X53-414
■Main MPU
The Main MPU (IC703) is a 32-bit RISC microprocessor
incorporating a 16K bite cache memory.
The main MPU controls the Flash ROM, SDRAM, SRAM,
LAN IC, RS-232C driver, receiver and real-time clock (RTC)
IC besides RF control MPU and UART communication with
modem control MPU.
■LAN interface
NXR-800 is equipped with a 100Base-TX or 10Base-T
LAN interface. This circuit consists of IC719, IC720 and
J700. IC719 is a control IC. IC720 is a EEPROM, and saves
the MAC address.
■Real time clock (RTC) circuit
This circuit consists of IC710 and X701. IC710 is a Real
Time Clock. X701 is a crystal oscillator. IC710 is connected
to IC703 (Main_MPU) via the IIC bus. The oscillating fre-
quency of X701 is 32.768kHz. It is backed up by a recharge-
able lithium battery (BA300). The IC710 clock data is used
after resetting the backup.
■RS-232C circuit
NXR-800 is equipped with a RS-232C interface. It is con-
nected to a PC with pin9 female RS-232C cross cable. It
uses the FPU and writes the firmware. IC705 is a RS-232C
driver receiver IC, and interfaces at the TTL232C level.
Fig. 24 An audio signal course and the frequency characteristic
CIRCUIT DESCRIPTION