Lattice Semiconductor MachXO2 Series Parts list manual

July 2017 Technical Note TN1204
www.latticesemi.com 1TN1204_3.9
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The MachXO2™ is an SRAM-based Programmable Logic Device that includes an internal Flash memory which
makes the MachXO2 appear to be a non-volatile device. The MachXO2 provides a rich set of features for program-
ming and configuration of the FPGA. You have many options available to you for building the programming solution
that fits your needs. Each of the options available will be described in detail so that you can put together the pro-
gramming and configuration solution that meets your needs.
MachXO2 Features
Key programming and configuration features of MachXO2 devices are:
• Instant-on configuration from internal Flash PROM – powers up in milliseconds
• Single-chip, secure solution
• Multiple programming and configuration interfaces:
— 1149.1 JTAG
— Self download
— Slave SPI
— Master SPI
— Dual Boot
— I2C
— WISHBONE bus
• User Flash Memory (UFM) for non-volatile data storage:
— Configuration Flash memory overflow
— EBR Initialization data
— Application specific data
• Transparent programming of non-volatile memory
• Optional dual boot with external SPI memory
• Optional security bits for design protection
MachXO2 Programming and
Configuration Usage Guide

MachXO2 Programming and Configuration Usage Guide
2
Definition of Terms
This document uses the following terms to describe common functions:
•BIT – The BIT file is the configuration data for the MachXO2 that is stored in an external SPI Flash. It is a binary
file and is programmed unmodified into the SPI Flash.
•Configuration – Configuration refers to a change in the state of the MachXO2 SRAM memory cells.
•Configuration Data – This is the data read from the non-volatile memory and loaded into the FPGA’s SRAM
configuration memory. This is also referred to as a bitstream, or device bitstream.
•Configuration Mode – The configuration mode defines the method the MachXO2 uses to acquire the configura-
tion data from the non-volatile memory.
•Internal Flash Memory – JED file or bit file can be programmed directly into the internal flash sector. User does
not need to know where an actual page of the configuration data starts. The MachXO2 configuration engine han-
dles the parsing in the flash to SRAM transfer.
•JEDEC– The JEDEC file contains the configuration data programmed into the MachXO2 Configuration Flash,
User Flash Memory, Feature Row, and Feature Bits. Format information is provided later in this technical note.
•Offline mode – Offline mode is a term that is applied to both non-volatile memory programming and SRAM con-
figuration. When using offline mode programming/configuration the FPGA no longer operates in user mode. The
contents of the non-volatile or SRAM configuration memory are updated, but the MachXO2 does not perform
your logic operations until offline mode programming/configuration is complete.
•Number Formats – The following nomenclature is used to denote the radix of numbers
— 0x: Numbers preceded by ‘0x’ are hexadecimal
— b (suffix): Numbers suffixed with ‘b’ are binary
— All other numbers are decimal
•Port – A port refers to the physical connection used to perform programming and some configuration operations.
Ports on the MachXO2 include JTAG, SPI, I2C, and WISHBONE physical connections.
• Programming: Programming refers to the process used to alter the contents of the internal or external non-vola-
tile configuration memory.
•Transparent Mode – Transparent mode is used to update the Configuration Flash, and User Flash Memory
while leaving the MachXO2 in User Mode.
•User Mode – The MachXO2 is in user mode when configuration is complete, and the FPGA is performing the
logic functions you have programmed it to perform.
Configuration Details
MachXO2 devices contain two types of memory, SRAM and Flash. SRAM memory contains the active configura-
tion, essentially the “fuses” that define the behavior of the FPGA. The active configuration is, in most cases,
retrieved from a non-volatile memory. The non-volatile memory holds the configuration data that is loaded into the
FPGAs SRAM. The MachXO2 provides an internal Flash memory that stores the configuration data loaded into the
MachXO2 SRAM.

MachXO2 Programming and Configuration Usage Guide
3
Configuration Process and Flow
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration
and wake-up.
Figure 1. Configuration Flow
The MachXO2 sysCONFIG ports provide industry standard communication protocols for programming and config-
uring the FPGA. Each of the protocols shown in Table 1 provides a way to access the MachXO2 device’s internal
Flash memory, or to load its configuration SRAM. The Memory Space Accessibility section provides information
about the capabilities of each sysCONFIG port.
The sysCONFIG ports capable of accessing the Flash memory have a priority order. Table 1 lists each of the sys-
CONFIG ports in their priority order. The MSPI configuration port does not have the ability to alter the Flash mem-
ory space, and as a result is not a factor in the sysCONFIG port priority scheme. The priority scheme is important
to be aware of, as a Configuration Logic operation using a low priority sysCONFIG port can be interrupted by a
higher priority sysCONFIG port. The operation of the Configuration Logic is not defined when a low priority sys-
CONFIG port is interrupted by a higher priority sysCONFIG port. Do not permit simultaneous access to the Config-
uration Logic using a sysCONFIG port.
Power not stable
PROGRAMN or
INITN=Low
INITN=Low
User Mode
Configuration
Write SRAM Memory
ERROR
Power Up
VCC > 1.06V or
VCC > 2.1V (HC devices)
VCCIO > 1.06V
INITN and DONE
Driven Low
Initialization
Wake Up
DONE Released
INITN Released
Device refresh
Device refresh
Device refresh
Device refresh:
• PROGRAMN falling edge
• IEEE 1532 REFRESH command
PROGRAMN de-asserted and t
INITL
expired
All configuration data received

MachXO2 Programming and Configuration Usage Guide
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Power-up Sequence
In order for the MachXO2 to operate, power must be applied to the device. During a short period of time, as the
voltages applied to the system rise, the FPGA will have an indeterminate state.
As power continues to ramp, a Power On Reset (POR) circuit inside the FPGA becomes active. The POR circuit,
once active, makes sure the external I/O pins are in a high-impedance state. It also monitors the VCC and VCCIO0
input rails. The POR circuit waits for the following conditions:
•V
CC > 1.06 V (or 2.1 V for HC devices)
•V
CCIO0 > 1.06 V
When these conditions are met the POR circuit releases an internal reset strobe, allowing the device to begin its
initialization process. The MachXO2 asserts INITN active low, and drives DONE low. When INITN and DONE are
asserted low the device moves to the initialization state, as shown in Figure 1.
Figure 2. Configuration from Power-On-Reset Timing
Initialization
The MachXO2 enters the memory initialization phase immediately after the Power On Reset circuit drives the
INITN and DONE status pins low. The purpose of the initialization state is to clear all of the SRAM memory inside
the FPGA.
The FPGA remains in the initialization state until all of the following conditions are met:
•Thet
INITL time period has elapsed
• The PROGRAMN pin is deasserted
• The INITN pin is no longer asserted low by an external master
The dedicated INITN pin provides two functions during the initialization phase. The first is to indicate the FPGA is
currently clearing its configuration SRAM. The second is to act as an input preventing the transition from the initial-
ization state to the configuration state.
During the tINITL time period the FPGA is clearing the configuration SRAM. When the MachXO2 is part of a chain
of devices each device will have different tINTIL initialization times. The FPGA with the slowest tINTIL parameter can
prevent other devices in the chain from starting to configure. Premature release of the INITN in a multi-device chain
may cause configuration of one or more chained devices to fail to configure intermittently.
The active-low, open-drain initialization signal INITN must be pulled high by an external resistor when initialization
is complete. To synchronize the configuration of multiple FPGAs, one or more INITN pins should be wire-ANDed. If
one or more FPGAs or an external device holds INITN low, the FPGA remains in the initialization state.
DONE
INITN
VCC/VCCIO
tINITL

MachXO2 Programming and Configuration Usage Guide
5
Configuration
The rising edge of the INITN pin causes the FPGA to enter the configuration state. The FPGA is able to accept the
configuration bitstream created by the Diamond development tools.
The MachXO2 begins fetching configuration data from non-volatile memory. The memory used to configure the
MachXO2 is either the internal Flash, or an external SPI Flash. The MachXO2 does not leave the Configuration
state if there are no memories with valid configuration data. It is necessary to program the non-volatile memory
internal or attached to the FPGA, or to program it using the JTAG port. Only JTAG, SSPI and I2Cmode are allowed
to be used as programming mode when the device is in a blank/erased state.
During the time the FPGA receives its configuration data the INITN control pin takes on its final function. INITN is
used to indicate an error exists in the configuration data. When INITN is high, configuration proceeds without issue.
If INITN is asserted low, an error has occurred and the FPGA will not operate.
Wake-up
Wake-up is the transition from configuration mode to user mode. The MachXO2’s fixed four-phase wake-up
sequence starts when the device has correctly received all of its configuration data. When all configuration data is
received, the FPGA asserts an internal DONE status bit. The assertion of the internal DONE causes a Wake Up
state machine to run that sequences four controls. The four control strobes are:
• Global Output Enable (GOE)
• Global Set/Reset (GSR)
• Global Write Disable (GWDISn)
• External DONE
The first phase of the Wake-Up process is for the MachXO2 to release the Global Output Enable. When it is
asserted, permits the FPGA’s I/O to exit a high-impedance state and take on their programmed output function.
The FPGA inputs are always active. The input signals are prevented from performing any action on the FPGA flip-
flops by the assertion of the Global Set/Reset (GSR).
The second phase of the Wake-Up process releases the Global Set/Reset and the Global Write Disable controls.
The Global Set/Reset is an internal strobe that, when asserted, causes all I/O flip-flops, Look Up Table (LUT) flip-
flops, distributed RAM output flip-flops, and Embedded Block RAM output flip-flops that have the GSR enabled
attribute to be set/cleared per their hardware description language definition.
The Global Write Disable is a control that overrides the write enable strobe for all RAM logic inside the FPGA. The
inputs on the FPGA are always active, as mentioned in the Global Output Enable section. Keeping GWDIS
asserted prevents accidental corruption of the instantiated RAM resources inside the FPGA.
The last phase of the Wake-Up process is to assert the external DONE pin. The external DONE is a bi-directional,
open-drain I/O only when it is enabled. An external agent that holds the external DONE pin low prevents the wake-
up process of the MachXO2 from proceeding. Only after the external DONE, if enabled, is active high does the final
wake-up phase complete. Wake-Up completes uninterrupted when the external DONE pin is not enabled.
Once the final wake-up phase is complete, the FPGA enters user mode.
The wake-up process is illustrated in Figure 18.

MachXO2 Programming and Configuration Usage Guide
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User Mode
The MachXO2 enters User Mode immediately following the Wake-Up sequence has completed. User Mode is the
point in time when the MachXO2 begins performing the logic operations you designed. The MachXO2 remains in
this state until one of three events occurs:
• The PROGRAMN input pin is asserted
• A REFRESH command is received via one of the configuration ports
• Power is cycled
Clearing the Configuration Memory and Re-initialization
The current user mode configuration of the MachXO2 remains in operation until it is actively cleared, or power is
lost. Several methods are available to clear the internal configuration memory of the MachXO2. The first is to
remove power and reapply power. Another method is to toggle the PROGRAMN pin. Lastly you can reinitialize the
memory through a Refresh command. Any active configuration port can be used to send a Refresh command.
• Assertion of the PROGRAMn input
• Cycling power to the MachXO2
• Sending the Refresh command using a configuration port
Invoking one of these methods causes the MachXO2 to drive INITN and DONE low. The MachXO2 enters the ini-
tialization state as described earlier.
Memory Space Accessibility
The two internal memories, Flash and SRAM, of the MachXO2 have the ability to be read and written. Each port on
the MachXO2 has a different level of access to each memory space. Table 2 provides a cross-reference of the
MachXO2 ports and the memory space they can access.
As can be seen from Table 1, the JTAG port has the ability to read and write both of the internal memory spaces.
No other port has ability to read the SRAM configuration memory. The JTAG port has the ability to access the two
memory spaces in either Offline or Transparent mode. Every other port has some limitation on the functions that
can be performed.
Table 1. Memory Space Accessibility of Different Ports
Port
On-Chip Flash SRAM
Read Write Read Write
J TA G Ye s Ye s Ye s Ye s
SPI Port
I2C Port
Yes Yes No Refresh2
Yes Yes No Refresh2
Internal WISHBONE Yes1Ye s 1No No
1. In Transparent mode only.
2. See the Clearing the Configuration Memory and Re-initialization section.

MachXO2 Programming and Configuration Usage Guide
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On-chip Flash Programming
As shown in Table 1, on-chip Flash is programmed with different programming modes. These programming modes
are discussed in the next sections. Within the different programming modes, there are two methods of program-
ming the on-chip Flash: Offline and Background programming.
Offline Programming - This method requires the device to enter into programming mode. When in programming
mode, the device stops working, until the programming is completed. When using Diamond Programmer, the
Offline Mode is selected using operations starting with FLASH. Unless noted by the operation, the Flash sectors
accessed are Feature, Configuration and UFM.
Background Programming - This method allows the device to continue operating in User Mode, while the config-
uration logic programs the on-chip Flash memory. When the on-chip Flash memory programming is completed, the
device can download into the SRAM with REFRESH instruction. When using Diamond Programmer, the Back-
ground Mode is selected using operations starting with XFLASH. Unless noted by the operation, the Flash sectors
accessed are Configuration and UFM.
Note that if background programming is used on the MachXO2-2000U, MachXO2-4000 and MachXO2-7000, the
system must put the right side PLL in reset state during background programming. The required duration, erase
portion, of the background Flash programming time is specified in Table 97 of TN1246, Using User Flash Memory
and Hardened Control Functions in MachXO2 Devices Reference Guide. The left side PLL can stay active during
background programming.
Bitstream/PROM Sizes
The MachXO2 is a SRAM based FPGA. The SRAM configuration memory must be loaded from a non-volatile
memory that can store all of the configuration data. The size of the configuration data is variable. It is based on the
amount of logic available in the FPGA, and the number of pre-initialized Embedded Block RAM (EBR) components.
A MachXO2 design using the largest device, with every EBR pre-initialized with unique data values, and generated
without compression turned on requires the largest amount of storage.
Storing configuration data in the MachXO2's internal Flash memory has special considerations. The Flash memory
in the MachXO2 provides three independent sectors. The first sector is dedicated for use in holding compressed
configuration data, and is called Configuration Flash. The second sector, called the User Flash Memory, provides
three different functions. It provides additional Configuration Flash storage for large configuration data images, it
can store EBR contents, or it is available for use as general purpose Flash memory. The third sector is the Feature
Row.
Figure 3. Flash Memory Space of a MachXO2 Device
Row Size = M
Row Size = N
128 Bits
Configuration Flash
Usercode
UFM
Feature Row

MachXO2 Programming and Configuration Usage Guide
8
The Configuration Flash is, for most designs, large enough to store the compressed configuration data that is
loaded into the SRAM configuration memory. However, as the amount of logic in the design increases, and the
amount of pre-initialized EBR increases, the size of the configuration data also increases. The increase in size can
cause the configuration data to overflow into the UFM sector. It is also possible, but unlikely, that the configuration
data can get too large for the internal Flash memory altogether. In the event configuration data grows too large to fit
in the combined Configuration Flash/UFM memory space the design needs to be modified so that it is smaller, or
an external configuration memory must be used. You can provide input to the software generating the configuration
data to prevent the overflow into the UFM.
In the event the configuration data is too large for the combined Configuration Flash and UFM memory you can
store the device bitstream in an external SPI Flash. Table 2 shows the maximum uncompressed bitstream sizes
allowing you to select a SPI Flash.
Table 2. Maximum Configuration Bits
Device
Uncompressed Bitstream Size
Without EBR
Uncompressed Bitstream Size
With EBR
Maximum
Internal Flash Units
LCMXO2-256 0.09 N/A 0.071 Mb
LCMXO2-256HC 0.09 N/A 0.071 Mb
LCMXO2-256ZE 0.09 N/A 0.071 Mb
LCMXO2-640 0.19 0.20 0.17 Mb
LCMXO2-640HC 0.19 0.20 0.17 Mb
LCMXO2-640ZE 0.19 0.20 0.17 Mb
LCMXO2-640UHC 0.19 0.20 0.17 Mb
LCMXO2-1200 0.35 0.41 0.33 Mb
LCMXO2-1200HC 0.35 0.41 0.33 Mb
LCMXO2-1200ZE 0.35 0.41 0.33 Mb
LCMXO2-1200UHC 0.35 0.41 0.33 Mb
LCMXO2-2000 0.51 0.58 0.47 Mb
LCMXO2-2000HC 0.51 0.58 0.47 Mb
LCMXO2-2000HE 0.51 0.58 0.47 Mb
LCMXO2-2000ZE 0.51 0.58 0.47 Mb
LCMXO2-2000U 0.51 0.58 0.47 Mb
LCMXO2-2000UHC 0.51 0.58 0.47 Mb
LCMXO2-2000UHE 0.51 0.58 0.47 Mb
LCMXO2-4000 0.93 1.02 0.80 Mb
LCMXO2-4000HE 0.93 1.02 0.80 Mb
LCMXO2-4000HC 0.93 1.02 0.80 Mb
LCMXO2-4000ZE 0.93 1.02 0.80 Mb
LCMXO2-7000 1.47 1.70 1.38 Mb
LCMXO2-7000HE 1.47 1.70 1.38 Mb
LCMXO2-7000HC 1.47 1.70 1.38 Mb
LCMXO2-7000ZE 1.47 1.70 1.38 Mb

MachXO2 Programming and Configuration Usage Guide
9
Feature Row
The MachXO2 includes a Feature Row that is used to control FPGA resources. For example, the Feature Row is
used to determine how the MachXO2 SRAM configuration memory is loaded. In other FPGAs this operation is con-
trolled using external I/O pins. The Feature Row permits more flexibility in selecting the functions available for con-
figuration, increases the number of available I/O on the device, and eliminates the need to make changes to your
hardware.
Feature Row can be erased or programmed independently. When Feature Row is erased, Feature Row sets its
value back to HW default mode state. Feature Row can be modified using Programming File Utility under Tools >
Feature Row Editor.
Figure 4. Feature Row Example
A relationship of Feature Row option and Diamond Spreadsheet View is shown in Table 3 and Table 4.
Table 3. Feature Row Option and Diamond Spreadsheet View
A full list of the functions controlled by the Feature Row and their default values are shown in Table 4.
MASTER_SPI_PORT CONFIGURATION
BOOT_SEL[2:1],
MSPI_Persistent_Enable
ENABLE CFG1001
ENABLE EXTERNAL 011
EFB_USER CFG1000
DISABLE CFG1000
1. “CFG” includes CFG, CFG_EBRUFM, or CFGUFM.

MachXO2 Programming and Configuration Usage Guide
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Table 4. MachXO2 Feature Row Elements
It is strongly recommended that the Feature Row only be modified during development, and rarely, if ever,
upgraded in the field. The reason for this recommendation is the Feature Row is responsible for controlling the
availability of the Configuration Ports. It is possible to cause active Configuration Ports to become unavailable, pre-
venting future updates.
Changing the Feature Row can prevent the MachXO2 from configuring. The PROGRAMN, INITN, and DONE
control and status pins are enabled and disabled using the Feature Row. Care must be taken when PROGRAMN is
recovered for use as a general purpose I/O: Erasing and re-programming the Feature Row causes the GPIO to
temporarily revert to PROGRAMN input. In this case, if the general purpose I/O is driven or held low the MachXO2
will not complete its configuration process.
Similar care must be taken when using I2Cinterface when recovering the SSPI interface for GPIO. Erasing and re-
programming the Feature Row will temporarily re-enable all configuration interfaces. If the SSPI chip select (SN) is
recovered as GPIO by the user design but is driven or held low, the SSPI interface will assert priority over the I2C
interface and interrupt the programming or configuration process, not allowing the process to compete successfully.
Feature Row can be erased or altered by Diamond Programmer. It will be erased and reprogrammed during Flash erase,
program and verify sequence, both offline and online. During offline flash programming, if you do not want Feature Row
to be erased and reprogrammed, Lattice recommends that you use XFLASH Erase, Program, Verify, Refresh operation.
Feature Row settings can be altered using the Diamond Spreadsheet View. Spreadsheet View allows you to edit
the configuration settings for the MachXO2, and then saves your settings in the Lattice Preference File (LPF).
These settings are applied to the MachXO2 configuration data during the Map, Place, and Route build phases.
Key Features
• Not intended to be modified in the field; only for development.
• Change in Feature Row settings may cause active configuration ports to become unavailable.
• Can be altered using Diamond Programmer or Diamond Spreadsheet View.
• Will be erased and re-programmed during Flash updates. So keep Feature Row contents consistent.
Feature SW Default Mode State (Programmed) HW Default Mode State (Erased)
PROGRAMN Persistence Disabled Enabled
INITn Persistence Disabled Disabled
DONE Persistence Disabled Disabled
Custom IDCODE 0x00000000 0x00000000
TraceID™ 00000000 00000000
Security1OFF OFF
JTAG Port Persistence Enabled Enabled
SSPI Port Persistence Disabled Enabled
I2C Port Persistence Disabled Enabled
MSPI Port Persistence Disabled Disabled
I2C Programmable Primary 
Configuration Address2, 3 yyyxxxxx00 1111000000
UFM OTP OFF OFF
SRAM OTP OFF OFF
Config Flash OTP OFF OFF
my_ASSP Enable OFF OFF
1. Enabled/disabled using the CONFIG_SECURE preference.
2. “y” and “x” are user programmable from IPexpressTM.
3. 1111000001 is a reserved address when the device is erased.

MachXO2 Programming and Configuration Usage Guide
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Configuration Modes
The MachXO2 configuration SRAM memory must be loaded with valid configuration data before the FPGA will
operate. The MachXO2 provides only four methods of getting the configuration data into the SRAM memory. Each
of these methods has its own set of advantages. The four methods available are shown in Table 5.
Table 5. Configuration Modes
The primary configuration mode, for a majority of MachXO2 designs, is Self-Download Mode. It has an advantage
in configuration speed because the internal configuration clock runs at frequencies higher than can be applied to
an external memory. It does not require an extra PROM, which increases the cost of your product. It does not rely
on an external programmer to load the SRAM using the JTAG port.
The External Download mode’s advantage is that it makes all of the User Flash Memory available for your use. You
do not have to be concerned about the Configuration Flash image overflowing into the UFM, or overflowing the
available internal Flash memory.
The Dual Boot mode’s advantage is the MachXO2 configures more reliably. The MachXO2 loads the internal Flash
memory image first, and should that fail, a fail-safe configuration data image can be downloaded into the
MachXO2’s SRAM, allowing the FPGA to continue to operate. A failed reprogramming of the internal memory, usu-
ally as a result of a loss of power, is the primary reason MachXO2 would fail to configure.
The JTAG port’s advantage is that it provides the widest set of functions and features for programming, configuring,
and testing the MachXO2 system.
sysCONFIG™ Ports
Table 6. MachXO2 Programming and Configuration Ports
sysCONFIG Pins
The MachXO2 provides a set of sysCONFIG I/O pins that you use to program and configure the FPGA. The sys-
CONFIG pins are grouped together to create ports (i.e. JTAG, SSPI, I2C, MSPI) that are used to interact with the
FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins in a config-
uration port group may be active, and used for programming the FPGA, or they can be reconfigured to act as gen-
eral purpose I/O.
Recovering the configuration port pins for use as general purpose I/O requires you to adhere to the following guide-
lines:
• You must DISABLE the unused port. You can accomplish this by using the Diamond Spreadsheet View’s Global
Preferences tab. Each configuration port is listed in the sysCONFIG options tree.
Mode Number of Pins Max. Frequency
1149.1 JTAG 4 (5) 25 MHz
Self-Download Mode 0 N/A
External Download 4 50 MHz
Dual Boot Download 0/4 N/A / 50 MHz
Interface Port Description
JTAG JTAG (IEEE 1149.1 and IEEE 1532 compliant) 4-wire or 5-wire JTAG Interface
sysCONFIG
SSPI Slave Serial Peripheral Interface (SPI)
MSPI Master Serial Peripheral Interface (SPI)
I2C Inter-integrated Circuit (I2C) Interface
Internal WISHBONE Internal WISHBONE bus interface

MachXO2 Programming and Configuration Usage Guide
12
• You must prevent external logic from interfering with device programming. Make sure that recovered sysCONFIG
pins are not asserted when the MachXO2 is in Feature Row HW Default Mode state. One example is driving
PROGRAMN with an active low signal after the MachXO2 is in Feature Row HW Default Mode state. Failure to
reprogram the Feature Row with PROGRAMN disabled prevents the FPGA from configuring and entering user
mode.
• Use care when using JTAGENB to selectively enable and disable the JTAG port. Any external logic connected to
the JTAG I/O must not contend with the JTAG programming port.
Table 7 lists the default state of the shared sysCONFIG pins. As you can see, a Default Mode Feature Row device
has the JTAG, SPI Slave and I2C ports enabled. Upon entry to User Mode the MachXO2, the default state of the
SSPI, and I2C sysCONFIG pins become general purpose I/O. This means you lose the ability to program the
MachXO2 using SSPI, or I2C when using the default sysCONFIG port settings. To retain the SSPI, or I2C sysCON-
FIG pins in user mode, be sure to ENABLE them using the Diamond Spreadsheet View editor.
Unless specified otherwise, the sysCONFIG pins are powered by the VCCIO0 voltage. It is crucial you take this into
consideration when provisioning other logic attached to Bank 0.
The function of each sysCONFIG pin is described in detail.
Table 7. Default State of the sysCONFIG Pins1
Table 8. Default State in Diamond for Each Port
Self Download Port Pins
PROGRAMN: The PROGRAMN is an input used to configure the FPGA. The PROGRAMN pin, when enabled, is
sensitive to a high-to-low transition, and has an internal weak pull-up. When PROGRAMN is asserted low, the
FPGA exits user mode and starts a device configuration sequence at the Initialization phase, as described earlier.
Holding the PROGRAMN pin low prevents the MachXO2 from leaving the Initialization phase. The PROGRAMN
Pin Name
Associated
sysCONFIG Port
Pin Function in
Feature Row Erased Mode
(Configuration Mode)
Pin Direction
(Configuration Mode)
Default Function
in User Mode2
PROGRAMN SDM PROGRAMN Input with weak pull up User-defined I/O
INITN SDM I/O I/O with weak pull up User-defined I/O
DONE SDM I/O I/O with weak pull up User-defined I/O
MCLK/CCLK SSPI/MSPI SSPI Input with weak pull up User-defined I/O
SN SSPI/MSPI SSPI Input with weak pull up User-defined I/O
SI/SISPI SSPI/MSPI SSPI Input User-defined I/O
SO/SPISO SSPI/MSPI SSPI Output User-defined I/O
CSSPIN MSPI I/O I/O with weak pull up User-defined I/O
SCL I2CI
2CBi-Directional User-defined I/O
SDA I2CI
2CBi-Directional User-defined I/O
1. All pins will be in Configuration Mode until the device is configured and enters User Mode.
2. Disabled sysConfig Pins will assume h/w default behavior in User Mode, that is, high-impedance with a weak pull down.
sysConfig Port Diamond Default 1
SDM_PORT Disable
SLAVE_SPI_PORT Disable
I2C_PORT Disable
MASTER_SPI_PORT Disable
JTAG_PORT Enable
1. This Default setting can be modified in the Diamond Spreadsheet View, Global Preferences tab.

MachXO2 Programming and Configuration Usage Guide
13
has a minimum pulse width assertion period in order for it to be recognized by the FPGA. You can find this mini-
mum time in DS1035, MachXO2 Family Data Sheet in the AC timing section.
Be aware of the following special cases when the PROGRAMN pin is active:
• If the device is currently being programmed via JTAG then PROGRAMN will be ignored until the JTAG mode pro-
gramming sequence is complete.
• Toggling the PROGRAMN pin during device configuration will interrupt the process and restart the configuration
cycle. Please keep PROGRAMN pin de-asserted (held High) during device configuration.
• Asserting PROGRAMN on a device in Feature Row HW Default Mode state disables the SSPI and I2C ports.
Start SSPI or I2C programming operations after PROGRAMN is deasserted.
• PROGRAMN is active during power-up, even when PROGRAMN has been reserved as a general purpose I/O.
Do not allow any input signal attached to PROGRAMN to transition from high to low at a frequency greater than
the VCC (min) to INITN rising edge time period. High to low PROGRAMN assertions more frequently prevent the
MachXO2 from configuring, causing the FPGA to remain in a continuous RESET condition. See Figure 5.
• PROGRAMN must be deasserted, even if recovered for GPIO, whenever the Feature Row is erased or re-pro-
grammed. If asserted, configuration may not complete successfully.
Figure 5. Period PROGRAMN is Always Observed
Figure 6. Configuration from PROGRAMN Timing
INITN: The INITn pin is a bidirectional open-drain control pin. It has the following functions:
• After power is applied, after a PROGRAMN assertion, or a REFRESH command it goes low to indicate the
SRAM configuration memory is being erased. The low time assertion is specified with the tINTIL parameter.
• After the tINTIL time period has elapsed the INITn pin is deasserted (i.e. is active high) to indicate the MachXO2
is ready for its configuration bits. The MachXO2 begins loading configuration data from either the internal Flash
memory or an external SPI Flash.
• INITn can be asserted low by an external agent before the tINTIL time period has elapsed in order to prevent the
FPGA from reading configuration bits. This is useful when there are multiple programmable devices chained
together. The programmable device with the longest tINTIL time can hold all other devices in the chain from start-
ing to get data until it is ready itself. 
PROGRAMN
INITN
VCC VCC min.
PROGRAMN transitions observed
DONE
INITN
PROGRAMN
tPRGMJ
tINITL
tDPPINIT
tDPPDONE

MachXO2 Programming and Configuration Usage Guide
14
• The last function provided by INITn is to signal an error during the time configuration data is being read. Once
tINTIL has elapsed and the INITn pin has gone high, any subsequent INITn assertion signals the MachXO2 has
detected an error during configuration.
The following conditions will cause INITN to become active, indicating the Initialization state is active:
• Power has just been applied
• PROGRAMN falling edge occurred
• The IEEE 1532 REFRESH command has been sent using a slave configuration port (JTAG, SSPI, I2C or WISH-
BONE).
If the INITN pin is asserted due to an error condition, the error can be cleared by correcting the configuration bit-
stream and forcing the FPGA into the Initialization state.
Figure 7. Configuration Error Notification
The INITN pin of a MachXO2 device is not visible external to the device when in the Feature Row HW Default Mode
state. The INITN pin, when in this mode, is pulled high by default. The INITN behavior described in Figure 7 is only
visible outside the MachXO2 when the INITN pin is enabled.
The INITN can be recovered as a general purpose I/O. By default, the INITN pin is disabled. You can use the Dia-
mond Spreadsheet View to enable it.
If an error is detected when reading the bitstream, INITN will go low, the internal DONE bit will not be set, the
DONE pin will stay low, and the device will not wake up. The device will fail configuration when the following hap-
pens:
• The bitstream CRC error is detected
• The invalid command error detected
• A time out error is encountered when loading from the on-chip Flash
• The program done command is not received when the end of on-chip SRAM configuration or on-chip Flash
memory is reached
DONE: The DONE pin is a bi-directional open drain with a weak pull-up that signals the FPGA is in User mode.
DONE is first able to indicate entry into User mode only after an internal DONE bit is asserted. The internal DONE
bit defines the beginning of the FPGA Wake-Up state.
The DONE output pin is controlled by the SDM_PORT configuration parameter that is modified in the Diamond
Spreadsheet View. By default the DONE pin is a general purpose I/O when the MachXO2 is in the Feature Row
HW Default Mode state. The default mode causes the MachXO2 to automatically sequence through the Wake-Up
sequence after the internal DONE bit is asserted. The FPGA does not stall waking up waiting for the DONE pin to
be asserted high.
The FPGA can be held from entering User mode indefinitely by having an external agent keep the DONE pin
asserted low. In order to use DONE to stall entering User mode the SDM_PORT must enable the DONE I/O, and
the FPGA Feature Row must be programmed. (This feature is supported in Diamond 3.5 and later. Earlier versions
DONE
INITN
PROGRAMN
tINITL
Configuration
Error
Configuration
Started

MachXO2 Programming and Configuration Usage Guide
15
of Diamond do not enable the stall feature when SDM_PORT enables DONE I/O). A common reason for keeping
DONE driven low is to allow multiple FPGAs to be completely configured. As each FPGA reaches the DONE state,
it is ready to begin operation. The last FPGA to configure can cause all FPGAs to start in unison.
The DONE pin drives low in tandem with the INITN pin when the FPGA enters Initialization mode. As described
earlier, this condition happens when power is applied, PROGRAMN is asserted, or an IEEE 1532 Refresh com-
mand is received via an active configuration port.
Sampling the DONE pin is a way for an external device to tell if the FPGA has finished configuration. However,
when using IEEE 1532 JTAG to configure SRAM the DONE pin is driven by a boundary scan cell, so the state of
the DONE pin has no meaning during IEEE 1532 JTAG configuration (once configuration is complete, DONE takes
on the behavior defined by the SDM_PORT setting in the Feature Row). The DONE pin is also pulled high when
the FPGA is in the Feature Row HW Default Mode state. This behavior can make a part appear to be successfully
configured to other logic monitoring the DONE pin.
Master and Slave SPI Configuration Port Pins
Table 9. Master SPI Configuration Port Pins
Table 10. Slave SPI Configuration Port Pins
MCLK/CCLK: The MCLK/CCLK, when active, are clocks used to sequentially load the configuration data for the
FPGA. The pin functions as:
The MCLK/CCLK pin’s default state for a MachXO2 in the Feature Row HW Default Mode state is to act as the con-
figuration clock (i.e., CCLK). This allows an external Slave SPI master controller to program the MachXO2. The
maximum CCLK frequency and the data setup/hold parameters can be found in the AC timing section of DS1035,
MachXO2 Family Data Sheet. The Feature Row must be configured to ENABLE the Slave SPI Port if you want to
use the port to reprogram the MachXO2 after it enters user mode.
The MCLK/CCLK pin functions as a Master Clock (MCLK) when the MachXO2 is configured in Dual Boot or Exter-
nal Boot modes. A 1K pull-up resistor is recommended when using these modes. The MCLK becomes an output
Pin Name Function Direction Description
MCLK/CCLK MCLK Output with weak pullup
Master clock used to time data transmission/reception from the
MachXO2 Configuration Logic to a slave SPI PROM. A 1K pull-up
resistor is recommended on MCLK for External and Dual Boot
configuration modes.
CSSPIN CSSPIN Output Chip select used to enable an external SPI PROM containing con-
figuration data
SI/SISPI SISPI Output SISPI carries output data from the MachXO2 Configuration Logic
to the slave SPI PROM
SO/SPISO SPISO Input SPISO carries output data from the slave SPI PROM to the
MachXO2 Configuration Logic
SN SN/IO Input MachXO2 Configuration Logic slave SPI chip select input. Pull
high externally whenever the MSPI port is active.
Pin Name Function Direction Description
MCLK/CCLK CCLK Input with weak pullup Clock used to time data transmission/reception from an external
SPI master device to the MachXO2 Configuration Logic.
SI/SISPI SI Input SI carries output data from the external SPI master to the
MachXO2 Configuration Logic
SO/SPISO SO Output SO carries output data from the MachXO2 Configuration Logic to
the external SPI master
SN SN Input with weak pullup MachXO2 Configuration Logic slave SPI chip select input. SN is
an active low input.

MachXO2 Programming and Configuration Usage Guide
16
and provides a reference clock for a SPI Flash attached to the MachXO2’s Master SPI Configuration port. MCLK
actively drives until all of the configuration data has been received. When the MachXO2 enters user mode the
MCLK output tri-states. This allows the MCLK to become a general purpose I/O. The MCLK is reserved for use, in
most post-configuration applications, as the reference clock for performing memory transactions with the external
SPI PROM.
The MachXO2 generates MCLK from an internal oscillator. The initial frequency of the MCLK is nominally 2.08
MHz. The MCLK frequency can be altered using the MCCLK_FREQ parameter. You can select the MCCLK_FREQ
using the Diamond Spreadsheet View. For a complete list of the supported MCLK frequencies, see Table 11.
Table 11. MachXO2 MCLK Valid Frequencies (MHz)
During the initial stages of device configuration the frequency value specified using MCCLK_FREQ is loaded into
the FPGA. Once the MachXO2 accepts the new MCLK_FREQ value the MCLK output begins driving the selected
frequency. Make certain when selecting the MCLK_FREQ that you do not exceed the frequency specification of
your configuration memory, or of your PCB. Review the MachXO2 AC specifications in DS1035, MachXO2 Family
Data Sheet when making MCLK_FREQ decisions.
SN: The SN pin is the Slave SPI ports chip select. An external SPI bus master asserts the SN pin active low in
order to perform actions using the MachXO2’s programming and configuration logic. The SN pin is available when
the MachXO2 is in the Feature Row HW Default Mode state, and in user mode when the Slave SPI port is set to the
ENABLE setting. The SN pin is a general purpose I/O in user mode when the Slave SPI port is set to the DISABLE
setting.
Proper operation of the MachXO2 depends upon maintaining the SN pin in the correct state:
• SN must be deasserted (that is, held High) when configuring using Master SPI mode. SN signal needs to be
clean during power up. Noise on SN pins may cause device failing to download from flash. SN must be asserted
when configuring using Slave SPI mode.
• SN must be deasserted when the MachXO2 is in user mode, and SPI memory transactions are initiated using
the internal WISHBONE bus
• SN must be deasserted when accessing the Configuration Logic in the MachXO2 using I2C
• When SN is asserted, CSSPIN must be deasserted. Deasserting CSSPIN places the shared SPI pins into a high
impedance state.
— The Master SPI port and the Slave SPI port share three common pins, SI/SISPI, SO/SPISO, and
MCLK/CCLK. The MachXO2 permits both ports to be available at the same time. They are not permitted to
be accessed at the same time. The Slave SPI and the Master SPI port must be time multiplexed when both
ports are enabled.
• SN must be deasserted, even if recovered for GPIO, whenever the Feature Row is Erased via I2CsysConfig port
(e.g. embedded reconfiguration). If asserted, configuration may not complete successfully.
Lattice recommends the SN pin be pulled high externally to augment the weak internal pull-up.
CSSPIN: The CSSPIN pin is an active low chip select used by the Master SPI configuration mode to enable an
external SPI Flash. When the MachXO2 is programmed to configure in either External or Dual Boot mode the
2.08 9.17 33.25
2.46 10.23 38.00
3.17 13.30 44.33
4.29 14.78 53.20
5.54 20.46 66.50
7.00 26.60 88.67
8.31 29.56 133.00

MachXO2 Programming and Configuration Usage Guide
17
CSSPIN pin is asserted to the attached SPI Flash. The MachXO2 asserts CSSPIN until all configuration data bytes
have been loaded, at which time the CSSPIN enters a high impedance state.
When the MachXO2 is in the Feature Row HW Default Mode state the CSSPIN is a general purpose I/O with a
weak pulldown. It must have an external pullup resistor when the External and Dual Boot configuration modes are
used. CSSPIN must ramp in tandem with the SPI PROM VCC input. It remains a general purpose I/O when the
FPGA enters user mode. You must ENABLE the Master SPI port to reserve CSSPIN for use by the internal SPI
Master logic.
When configuring from an external SPI Flash, ensure that the SPI Flash VCC and the MachXO2 VCCIO2 are at the
same level. Ensure that the SPI Flash VCC meets is at the recommended operating level.
Some SPI PROM manufacturers require the chip select input of the PROM ramp in unison to the PROMs VCC rail.
The CSSPIN pin, by default, has a weak pull-down resistor internally. Adding a 4.7 kOhm to 10 kOhm pull-up resis-
tor to the CSSPIN pin on the MachXO2 is recommended.
SI/SISPI: The SI/SISPI is a dual function bi-directional pin. The direction depends upon whether a Master or Slave
mode is active. The SI/SISPI is an input data pin when using the Slave SPI mode and is an output data pin when
using the Master SPI mode. In Master SPI mode, the MachXO2 drives SI/SISPI until all configuration data bytes
have been loaded, at which time the SI/SISPI enters a high impedance state.
At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE
in order to preserve this pin as SI/SISPI and allow access to the SPI interface.
SO/SPISO: The SO/SPISO pin is a dual function bi-directional pin. The direction depends upon whether a Master
or Slave mode is active. The SO/SPISO is an input data pin when using the Master SPI mode and is an output data
pin when using the Slave SPI mode.
At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE
in order to preserve this pin as SO/SPISO and allow access to the SPI interface.
I2C Configuration Port Pins
SCL: The MachXO2 provides an I2C configuration port. The SCL is the I2C Serial Clock pin, and is used to initiate
and time transactions on the I2C bus. It is a bi-directional, open-drain signal that is an output when the MachXO2
I2C controller is mastering transactions on the bus, and is an input when an external I2C master is accessing
resources inside the MachXO2. SCL requires an external pull-up resistor in order to operate.
The SCL pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the
I2C_PORT and instantiate the Embedded Function Block (EFB) for the I2C port to continue to be available in user
mode (see the I2C Configuration Mode section for details.) The SCL pin becomes a general purpose I/O if you do
not ENABLE the I2C_PORT.
SDA: The SDA pin is the I2C serial data input/output pin. It is bi-directional, open-drain, and requires an external
pull-up resistor in order to operate. The pin changes direction dynamically during data transactions on the I2C bus.
The current state depends on the current bus master and the operation being performed by that master.
The SDA pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the
I2C_PORT and instantiate the EFB if you want the I2C port to continue to be available in user mode (see the I2C
Configuration Mode section for details.) The SDA pin becomes a general purpose I/O if you do not ENABLE the
I2C_PORT.
JTAG Configuration Port Pins
The JTAG pins provide a standard IEEE 1149.1 Test Access Port (TAP). The JTAG port is the only configuration
port on the MachXO2 that is capable of performing configuration, programming, and multi-device configuration
functions. Programming and configuration over the JTAG port uses IEEE 1532 compliant commands. In addition to
the IEEE 1532 capabilities, the MachXO2 provides all of the mandatory IEEE 1149.1 Test Access Port commands
allowing printed circuit board assembly verification.

MachXO2 Programming and Configuration Usage Guide
18
The JTAG port is enabled by default when the MachXO2 is in the Feature Row HW Default Mode state. Like all of
the other configuration port pins the JTAG pins can become general purpose I/O. Unlike the other ports, the default
state for the JTAG port is to remain active in user mode (i.e. ENABLE state). The JTAG pins can be recovered to be
general purpose I/O by setting the JTAG_PORT preference to the DISABLE state. It is recommended the JTAG
port remain dedicated programming pins.
The JTAG port, when set in the DISABLE state, enables the JTAGENB input. JTAGENB permits the JTAG pins to
be multiplexed. Asserting JTAGENB high causes the JTAG pins to take on the IEEE 1149.1 personality. De-assert-
ing JTAGENB (i.e. driven low) causes the JTAG port pins to become general purpose I/O. Design the JTAG port cir-
cuitry carefully when taking advantage of JTAG port pin multiplexing. Avoid bus contention between logic attached
to the JTAG port.
When the device is programmed through IEEE 1149.1 control, the sysCONFIG programming pins, such as DONE,
cannot be used to determine programming progress. This is because the state of the boundary scan cell will drive
the pin, per the IEEE JTAG standard, rather than normal internal logic.
Table 12. JTAG Port Pins
TDO: The Test Data Output (TDO) pin is used to shift out serial test instructions and data. When TDO is not being
driven by the internal circuitry, the pin will be in a high impedance state. The only time TDO is not in a high imped-
ance state is when the JTAG state machine is in the Shift IR or Shift DR state. This pin should be wired to TDO of
the JTAG connector, or to TDI of a downstream device in a JTAG chain. An internal pull-up resistor on the TDO pin
is provided. The internal resistor is pulled up to VCCIO Bank 0.
TDI: The Test Data Input (TDI) pin is used to shift in serial test instructions and data. This pin should be wired to
TDI of the JTAG connector, or to TDO of an upstream device in a JTAG chain. An internal pull-up resistor on the
TDI pin is provided. The internal resistor is pulled up to VCCIO of Bank 0.
TMS: The Test Mode Select (TMS) pin is an input pin that controls the progression through the 1149.1 compliant
state machine states. The TMS pin is sampled on the rising edge of TCK. The JTAG state machine remains in or
transitions to a new TAP state depending on the current state of the TAP, and the present state of the TMS input. An
internal pull-up resistor is present on TMS per the JTAG specification. The internal resistor is pulled to the VCCIO
of Bank 0.
TCK: The test clock pin (TCK) provides the clock used to time the other JTAG port pins. Data is shifted into the
instruction or data registers on the rising edge of TCK and shifted out on the falling edge of TCK. The TAP is a
static design permitting TCK to be stopped in either the high or low state. The maximum input frequency for TCK is
specified in the DC and Switching Characteristics section of DS1035, MachXO2 Family Data Sheet. The TCK pin
does not have a pull-up. An external pull-down resistor of 4.7 kOhms is recommended to avoid inadvertently clock-
ing the TAP controller as power is applied to the MachXO2.
JTAGENB: The JTAG ENABLE pin, also known as the IEEE 1149.1 conformance pin, is an input pin that can be
used to multiplex the JTAG port. The JTAGENB pin is only active in user mode. The JTAGENB pin is a user I/O
while the JTAG port is in the ENABLE state. Figure 8 shows the default behavior of the JTAG port of a MachXO2
device.
Pin Name
Pin Function
(Configuration Mode)
Pin Direction
(Configuration Mode)
Default Function
(User Mode)
TDI TDI Input with weak pull-up TDI
TDO TDO Output with weak pull-up TDO
TCK TCK Input TCK
TMS TMS Input with weak pull-up TMS
JTAGENB I/O Input/output with weak pull-down I/O

MachXO2 Programming and Configuration Usage Guide
19
Figure 8. Default JTAG Port with JTAG_PORT = ENABLE
The JTAG port can become general purpose I/O. By setting the JTAG_PORT preference in the Diamond Spread-
sheet View to the DISABLE state. When the JTAG port is in the DISABLE state the JTAGENB pin becomes a dedi-
cated input. Driving the JTAGENB low disables the JTAG port and the four JTAG pins become general purpose
I/Os. Driving the JTAGENB input high enables the JTAG port. Figure shows JTAG port behavior under the control
of the JTAGENB.
Figure 9. JTAG Port Behavior with JTAG_PORT = DISABLE
It is critical when using the JTAGENB feature that logic attached to the JTAG I/O pins not contend with a JTAG program-
ming system. The external logic must ignore any JTAG transactions performed by an external programming system.
Lattice parallel port or USB download cables provide an output called ispEN. The ispEN signal can be attached to the
JTAGENB input to control the availability of the JTAG port. An alternate mechanism to control the JTAGENB input is to
use a shunt that can be installed or removed as required.
Configuration Modes
The MachXO2 provides multiple options for loading the configuration SRAM from a non-volatile memory. The previ-
ous section described the physical interface necessary to interact with the MachXO2 configuration logic. This sec-
tion focuses on describing the functionality of each of the different configuration modes. Descriptions of important
settings required in the Diamond Spreadsheet View are also discussed.
SDM Mode
Self Download Mode is the primary configuration method for the MachXO2. The advantages of Self Download
Configuration Mode include:
•Speed: The MachXO2 is ready to run in a few milliseconds depending on the density of the device.
•Security: The configuration data is never seen outside the device during the load to SRAM. You can prevent the
internal memory from being read.
•Reduced cost: There is no need to purchase a PROM specifically reserved for programming the MachXO2.
•Reduced board space: Elimination of an external PROM allows your board to be smaller.
•Improved reliability: The MachXO2 can boot from an external PROM if the internal Flash memory gets cor-
rupted during a system update.
TCK/IO
TMS/IO
TDI/IO
TDO/IO
TCK
TMS
TDI
TDO
MachXO2
IO/JTAGENB
TCK/IO
TMS/IO
TDI/IO
TDO/IO
I/O
I/O
I/O
I/O
IO/JTAGENB
TCK/IO
TMS/IO
TDI/IO
TDO/IO
JTAGENB = ‘1’
TCK
TM
TDIS
TDO
VCCIO
MachXO2 MachXO2
GND
JTAGENB = ‘0’

MachXO2 Programming and Configuration Usage Guide
20
The MachXO2 retrieves the configuration data from the internal Flash memory when it is using Self Download
Mode. SDM is triggered when power is applied, a REFRESH command is received, or by asserting the PRO-
GRAMN pin. As shown in Figure 6, the internal Flash memory has three sectors. The first sector, in most cases, is
large enough to store the MachXO2 device’s configuration data. The size of the configuration data changes based
on how well it can be compressed and how many pre-initialized EBR components are in the design. As the size of
the configuration data increases, the Configuration Flash sector can overflow. The overflow can be handled by
allowing the configuration data to overflow into the User Flash Memory sector. It is, in rare cases, possible for the
configuration data to overflow the Configuration Flash (CFM), and the User Flash Memory (UFM). Self Download
Mode cannot be used when the Configuration Flash and User Flash Memory overflow occurs. Master SPI Configu-
ration Mode must be used in the event of the CF/UFM overflow.
The normal situation for the configuration data is to fit completely within the Configuration Flash sector. Designs
that do not use very much pre-initialized EBR will almost always meet this condition. The UFM is available for use
as an internal Flash memory array. It is recommended that the CONFIGURATION option be set to CFG. This set-
ting prevents the configuration data from overflowing into the UFM, assuring that data provisioned for the UFM is
not overwritten during a device update.
The User Flash Memory, which is the second Flash sector, provides three different use models:
• Configuration data overflow from Configuration Memory
• Initialization of EBR and user-defined storage
• User-defined storage
Diamond, by default, builds the pre-initialized EBR data into the configuration data image. This may cause the con-
figuration data to overflow into the UFM sector. In order to change the default state you need to use the Diamond
Spreadsheet tool to modify the sysCONFIG’s CONFIGURATION entry. The default state for the CONFIGURATION
entry is to be set to CFG.
The configuration data can be logically split to place the pre-initialization data for the EBR into the UFM. Setting the
CONFIGURATION option to CFG_EBRUFM causes the Diamond software to place the configuration data into the
Configuration Flash, and the EBR initialization data into the UFM. This locates the EBR initialization data into the
first pages of the UFM. The current Diamond development tools do not provide a way to map the EBR initialization
data stored in the UFM to the associated EBR in the FPGA fabric.
In addition to the automatic assignment of the initialized EBR data, you have the ability to add a data block for your
own purposes. Using IPexpress, you can associate a memory initialization file to the UFM. This data is stored in the
last memory locations of the UFM in order to prevent collisions with the EBR initialization data.
The user-defined storage mode of operation permits the sector to behave like a general purpose Flash memory.
You can choose to use IPexpress to pre-initialize data, or you can use it as if it were a discrete Flash memory
device with a single erasable sector.
In all three cases, the UFM can only be erased by erasing the whole sector. It is your responsibility to restore con-
figuration data, EBR initialization data, and your implementation specific data. In other words, you need to read all
data in the UFM, merge your changes, erase the UFM, and write the new data back into the UFM.
Master SPI Configuration Mode (MSPI)
Master SPI Configuration Mode is the only other self-controlled configuration mode available to the MachXO2.
When the MachXO2 has the Master SPI Configuration mode (MSPI) enabled it is able to automatically retrieve the
configuration data from an externally attached SPI Flash. The MSPI configuration port is not available when the
MachXO2 is in the Feature Row HW Default Mode state. When configuring using the MSPI mode be sure to enable
the MSPI port in the Feature Row. Lattice recommends having a secondary configuration port available, one that is
active when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased), that allows you to
recover the MachXO2 in the event of a programming error.