Lattice Semiconductor ECP5 Versa Instruction Manual

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
FPGA-TN-02035-1.3
October 2020

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-TN-02035-1.3
Disclaimers
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document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 3
Contents
Acronyms in This Document.................................................................................................................................................9
1. Introduction................................................................................................................................................................10
2. External Interface Description....................................................................................................................................10
3. High-Speed I/O Interface Building Blocks...................................................................................................................11
3.1. Edge Clocks........................................................................................................................................................11
3.2. Primary Clocks...................................................................................................................................................11
3.3. DQS Lane...........................................................................................................................................................11
3.4. PLL .....................................................................................................................................................................12
3.5. DDRDLL..............................................................................................................................................................12
3.6. DQSBUF.............................................................................................................................................................12
3.7. DLLDEL...............................................................................................................................................................13
3.8. Input DDR (IDDR)...............................................................................................................................................13
3.9. Output DDR (ODDR)..........................................................................................................................................13
3.10. Edge Clock Dividers (CLKDIV) ............................................................................................................................13
3.11. Input/Output DELAY..........................................................................................................................................13
4. Building Generic High Speed Interfaces .....................................................................................................................14
4.1. Types of High-Speed DDR Interfaces.................................................................................................................14
5. High-Speed DDR Interface Details ..............................................................................................................................15
5.1. GDDRX1_RX.SCLK.Centered..............................................................................................................................15
5.2. GDDRX1_RX.SCLK.Aligned.................................................................................................................................16
5.3. GDDRX2_RX.ECLK.Centered..............................................................................................................................17
5.4. GDDRX2_RX.ECLK.Aligned.................................................................................................................................18
5.5. GDDRX2_RX.MIPI ..............................................................................................................................................20
5.6. GDDRX71_RX.ECLK............................................................................................................................................21
5.7. GDDRX1_TX.SCLK.Aligned.................................................................................................................................22
5.8. GDDRX1_TX.SCLK.Centered ..............................................................................................................................22
5.9. GDDRX2_TX.ECLK.Aligned.................................................................................................................................23
5.10. GDDRX2_TX.ECLK.Centered ..............................................................................................................................24
5.11. GDDRX71_TX.ECLK............................................................................................................................................25
5.12. Generic DDR Design Guidelines ........................................................................................................................25
5.12.1. Using the High Speed Edge Clock Bridge......................................................................................................25
5.12.2. Receive Interface Guidelines........................................................................................................................26
5.12.3. Transmit interface Guidelines ......................................................................................................................26
5.12.4. Clocking Guidelines for Generic DDR Interface............................................................................................26
5.13. Timing Analysis for High Speed DDR Interfaces ................................................................................................27
5.13.1. Frequency Constraints..................................................................................................................................27
5.13.2. DDR Input Setup and Hold Time Constraints ...............................................................................................27
5.13.3. DDR Clock to Out Constraints for Transmit Interfaces.................................................................................28
6. ECP5 and ECP5-5G Memory Interfaces ......................................................................................................................31
6.1. DDR Memory Interface Requirements..............................................................................................................33
6.2. Features for Memory Interface Implementation..............................................................................................34
6.2.1. DQS Grouping...............................................................................................................................................34
6.2.2. DLL-Compensated DQS Delay Elements.......................................................................................................35
6.2.3. Data Valid Module........................................................................................................................................35
6.2.4. READ Pulse Positioning Optimization...........................................................................................................36
6.2.5. Dynamic Margin Control on DQSBUF...........................................................................................................38
6.2.6. Read Data Clock Domain Transfer Using Input FIFO ....................................................................................38
6.2.7. DDR Input and Output Registers (IDDR/ODDR)............................................................................................38
6.3. Memory Interface Implementation ..................................................................................................................38
6.3.1. Read Implementation...................................................................................................................................38
6.3.2. Write Implementation (DQ, DQS, and DM)..................................................................................................40
6.3.3. Write Implementation (DDR2, DDR3/DDR3L Address, Command, and Clock) ............................................41

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-TN-02035-1.3
6.3.4. Write Implementation (LPDDR2 and LPDDR3 Address, Command, and Clock) ...........................................42
6.4. DDR Memory Interface Design Rules and Guidelines .......................................................................................44
6.5. DDR2/DDR3 Memory Interface Termination Guidelines ..................................................................................45
6.5.1. Termination for DQ, DQS, and DM...............................................................................................................45
6.5.2. Termination for CK .......................................................................................................................................45
6.5.3. Termination for Address, Commands, and Controls ....................................................................................46
6.5.4. Termination for DDR3/DDR3L DIMM ...........................................................................................................46
6.6. DDR Memory Interface Pinout Guidelines ........................................................................................................46
6.7. Pin Placement Considerations for Improved Noise Immunity ..........................................................................47
7. Using Clarity Designer to Build and Plan High Speed DDR Interfaces.........................................................................49
7.1. Configuring DDR Modules in Clarity Designer...................................................................................................50
7.2. Configuring SDR Modules..................................................................................................................................50
7.3. Configuring DDR Generic modules....................................................................................................................53
7.4. Configuring 7:1 LVDS Interface Modules...........................................................................................................57
7.5. Configuring DDR Memory Interfaces ................................................................................................................58
7.6. Building DDR Interfaces in Clarity Designer ......................................................................................................62
7.7. Planning DDR Interfaces in Clarity Designer......................................................................................................63
8. DDR Software Primitives and Attributes.....................................................................................................................64
8.1. Input/Output DELAY..........................................................................................................................................64
8.2. DELAYF...............................................................................................................................................................65
8.3. DELAYG..............................................................................................................................................................65
8.4. DELAY Attribute Description .............................................................................................................................66
8.5. DDRDLL (Master DLL) ........................................................................................................................................66
8.5.1. DDRDLLA.......................................................................................................................................................66
8.6. DLL Delay (DLLDEL)............................................................................................................................................67
8.7. Generic DDR Input and Output Primitives ........................................................................................................68
8.8. Input DDR Primitives .........................................................................................................................................68
8.8.1. IDDRX1F........................................................................................................................................................68
8.8.2. IDDRX2F........................................................................................................................................................69
8.8.3. IDDR71B........................................................................................................................................................69
8.9. Output DDR Primitives ......................................................................................................................................70
8.9.1. ODDRX1F ......................................................................................................................................................70
8.9.2. ODDRX2F ......................................................................................................................................................70
8.9.3. ODDR71B......................................................................................................................................................71
8.10. Memory DDR Primitives....................................................................................................................................71
8.10.1. DQSBUF (DQS Strobe Control Block)............................................................................................................71
8.10.2. DQSBUFM.....................................................................................................................................................72
8.11. Input and Output Memory DDR Primitives.......................................................................................................73
8.12. Memory Input DDR Primitives...........................................................................................................................74
8.12.1. IDDRX2DQA ..................................................................................................................................................74
8.13. Memory Output DDR Primitives for DQ Output................................................................................................75
8.13.1. ODDRX2DQA.................................................................................................................................................75
8.14. Memory Output DDR Primitives for DQS Output..............................................................................................75
8.14.1. ODDRX2DQSB...............................................................................................................................................75
8.15. Memory Output DDR Primitives for Tristate Output Control ...........................................................................76
8.15.1. TSHX2DQA....................................................................................................................................................76
8.15.2. TSHX2DQSA ..................................................................................................................................................76
8.16. Memory Output DDR Primitives for Address and Command............................................................................77
8.16.1. OSHX2A.........................................................................................................................................................77
9. Soft IP Modules...........................................................................................................................................................78
9.1. Detailed Description of Each Soft IP..................................................................................................................78
9.1.1. GDDR_SYNC..................................................................................................................................................78
9.1.2. RX_SYNC .......................................................................................................................................................79
9.1.3. MEM_SYNC...................................................................................................................................................80

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 5
9.1.4. BW_ALIGN....................................................................................................................................................80
9.1.5. MIPI_FILTER..................................................................................................................................................81
Technical Support Assistance .............................................................................................................................................83
Revision History..................................................................................................................................................................84

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-TN-02035-1.3
Figures
Figure 2.1. External Interface Definitions ...........................................................................................................................10
Figure 3.1. ECP5 and ECP5-5G Device Clocking Diagram....................................................................................................11
Figure 3.2. DDRDLL Connectivity ........................................................................................................................................12
Figure 5.1. GDDRX1_RX.SCLK.Centered Interface (Static Delay) ........................................................................................15
Figure 5.2. GDDRX1_RX.SCLK.Centered Interface (Dynamic Data Delay)...........................................................................15
Figure 5.3. GDDRX1_RX.SCLK.Aligned Interface (Static Delay)...........................................................................................16
Figure 5.4. GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay) ...................................................................17
Figure 5.5. GDDRX2_RX.ECLK.Centered Interface (Static Delay)........................................................................................18
Figure 5.6. GDDRX2_RX.ECLK.Centered Interface (Dynamic Data Delay)...........................................................................18
Figure 5.7. GDDRX2_RX.ECLK.Aligned Interface (Static Delay)...........................................................................................19
Figure 5.8. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay) ...................................................................19
Figure 5.9. GDDRX2_RX.MIPI..............................................................................................................................................20
Figure 5.10. GDDRX71_RX.ECLK Interface ..........................................................................................................................21
Figure 5.11. GDDRX1_TX.SCLK.Aligned Interface ...............................................................................................................22
Figure 5.12. GDDRX1_TX.SCLK.Centered Interface.............................................................................................................23
Figure 5.13. GDDRX2_TX.ECLK.Aligned Interface ...............................................................................................................23
Figure 5.14. GDDRX2_TX.ECLK.Centered Interface ............................................................................................................24
Figure 5.15. GDDRX71_TX.ECLK Interface ..........................................................................................................................25
Figure 5.16. RX Centered Interface Timing.........................................................................................................................27
Figure 5.17. RX Aligned Interface Timing............................................................................................................................28
Figure 5.18. tCO Min and Max Timing Analysis ..................................................................................................................29
Figure 5.19. Transmit Centered Interface Timing...............................................................................................................29
Figure 5.20. Transmit Aligned Interface Timing..................................................................................................................30
Figure 6.1. Typical DDR2/DDR3/DDR3L Memory Interface................................................................................................31
Figure 6.2. Typical LPDDR2/LPDDR3 Memory Interface.....................................................................................................32
Figure 6.3. DQ-DQS During Read ........................................................................................................................................32
Figure 6.4. DQ-DQS During Write .......................................................................................................................................32
Figure 6.5. DQ-DQS Grouping.............................................................................................................................................34
Figure 6.6. DQSBUF Block Functions...................................................................................................................................35
Figure 6.7. READ Signal Training Process............................................................................................................................37
Figure 6.8. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Read Side Implementation ..........................................................39
Figure 6.9. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Write Side (DQ, DQS, and DM) ....................................................40
Figure 6.10. DDR2, DDR3/DDR3L Address, Command, and Clock Generation ...................................................................41
Figure 6.11. LPDDR2 Output for CA Generation.................................................................................................................42
Figure 6.12. LPDDR2 Output for CSN, CKE, and CLOCK Generation ...................................................................................43
Figure 6.13. LPDDR3 Output Side for CA Generation .........................................................................................................43
Figure 6.14. LPDDR3 Output Side for CSN, CKE, ODT, and CLOCK Generation...................................................................44
Figure 7.1. Clarity Design Main Window.............................................................................................................................49
Figure 7.2. SDR Option Selected in the Catalog Tab of Clarity Designer.............................................................................50
Figure 7.3. SDR Configuration Tab......................................................................................................................................51
Figure 7.4. DDR_Generic Option Selected in the Catalog Tab of Clarity Designer..............................................................53
Figure 7.5. DDR_Generic Pre-Configuration Tab ................................................................................................................53
Figure 7.6. DDR_Generic Configuration Tab.......................................................................................................................54
Figure 7.7. GDDR_7:1 Option Selected in the Catalog Tab of Clarity Designer ..................................................................57
Figure 7.8. GDDR_7:1 LVDS Configuration Tab...................................................................................................................57
Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer .................................................................58
Figure 7.10. DDR_MEM Configuration Tab.........................................................................................................................59
Figure 7.11. DDR_MEM Clock/Address/Command Tab......................................................................................................61
Figure 7.12. DDR_MEM Advanced Settings Tab.................................................................................................................62
Figure 7.13. DDR Modules Paced Using Clarity Design Planner..........................................................................................63
Figure 8.1. DELAYF Primitive...............................................................................................................................................65
Figure 8.2. DELAYG Primitive ..............................................................................................................................................65

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 7
Figure 8.3. DDRDLLA Primitive............................................................................................................................................66
Figure 8.4. DLLDELD Primitive ............................................................................................................................................67
Figure 8.5. IDDDRX1F Primitive ..........................................................................................................................................68
Figure 8.6. IDDRX2F Primitive.............................................................................................................................................69
Figure 8.7. IDDR71B............................................................................................................................................................69
Figure 8.8. ODDRX1F...........................................................................................................................................................70
Figure 8.9. ODDRX2F...........................................................................................................................................................70
Figure 8.10. ODDR71B Primitive.........................................................................................................................................71
Figure 8.11. DQSBUFM Primitive........................................................................................................................................72
Figure 8.12. IDDRX2DQA Primitive .....................................................................................................................................74
Figure 8.13. ODDRX2DQA...................................................................................................................................................75
Figure 8.14. ODDRX2DQSB Primitive..................................................................................................................................75
Figure 8.15. TSHX2DQA Primitive.......................................................................................................................................76
Figure 8.16. TSHX2DQSA Primitive .....................................................................................................................................76
Figure 8.17. OSHX2A Primitive ...........................................................................................................................................77
Figure 9.1. GDDR_SYNC Ports.............................................................................................................................................78
Figure 9.2. RX_SYNC Ports ..................................................................................................................................................79
Figure 9.3. MEM_SYNC Ports..............................................................................................................................................80
Figure 9.4. BW_ALIGN Ports...............................................................................................................................................80
Figure 9.5. MIPI_FILTER Ports.............................................................................................................................................81

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-TN-02035-1.3
Tables
Table 4.1. Generic High-Speed I/O DDR Interfaces.............................................................................................................14
Table 6.1. DDR Memory Configurations Support ...............................................................................................................33
Table 6.2. DDRDLL Connectivity..........................................................................................................................................35
Table 6.3. DDRDLL Connectivity..........................................................................................................................................36
Table 6.4. I/O Standards for DDR Memory.........................................................................................................................45
Table 7.1. SDR Configuration Parameters...........................................................................................................................52
Table 7.2. DDR_Generic Pre-Configuration Parameters.....................................................................................................54
Table 7.3. DDR_Generic Configuration Tab Parameters.....................................................................................................55
Table 7.4. Clarity Designer DDR_Generic Interface Selection ............................................................................................56
Table 7.5. GDDR_7:1 LVDS Configuration Parameters .......................................................................................................58
Table 7.6. DDR_MEM Configuration Tab Parameters ........................................................................................................60
Table 7.7. DDR_MEM Clock/Address/Command Parameters ............................................................................................61
Table 7.8. DDR_MEM Advanced Settings Tab Parameters.................................................................................................62
Table 8.1. Software Primitives............................................................................................................................................64
Table 8.2. DELAYF Port List .................................................................................................................................................65
Table 8.3. DELAYG Port List.................................................................................................................................................65
Table 8.4. DELAYF and DELAYG Attributes..........................................................................................................................66
Table 8.5. DDRDLLA Port List ..............................................................................................................................................67
Table 8.6. DDRDLL Attributes .............................................................................................................................................67
Table 8.7. DLLDELD Port List...............................................................................................................................................67
Table 8.8. DLLDELD Attributes............................................................................................................................................68
Table 8.9. IDDRX1F Port List ...............................................................................................................................................68
Table 8.10. IDDRX2F Port List .............................................................................................................................................69
Table 8.11. IDDRX2F Port List .............................................................................................................................................69
Table 8.12. ODDRX1F Port List............................................................................................................................................70
Table 8.13. ODDRX2F Port List............................................................................................................................................70
Table 8.14. ODDR71B Port List ...........................................................................................................................................71
Table 8.15. DQSBUF Port List..............................................................................................................................................72
Table 8.16. DQSBUFM Attributes .......................................................................................................................................73
Table 8.17. Summary of all DDR Memory Primitives..........................................................................................................73
Table 8.18. DQSBUF Port List..............................................................................................................................................74
Table 8.19. Memory Primitive Attributes ...........................................................................................................................74
Table 8.20. ODDRX2DQA Port List ......................................................................................................................................75
Table 8.21. ODDRX2DQA Port List ......................................................................................................................................76
Table 8.22. TSHX2DQA Port List..........................................................................................................................................76
Table 8.23. TSHX2DQSA Port List........................................................................................................................................77
Table 8.24. OSHX2A Port List..............................................................................................................................................77
Table 9.1. List of Soft IPs supported ...................................................................................................................................78
Table 9.2. Soft IP Used in Each Interface ............................................................................................................................78
Table 9.3. GDDR_SYNC Port List description ......................................................................................................................79
Table 9.4. GDDR_SYNC Port List description ......................................................................................................................79
Table 9.5. MEM_SYNC Port Description .............................................................................................................................80
Table 9.6. BW_ALIGN Port Description...............................................................................................................................81
Table 9.7. MIPI_FILTER Port Description ............................................................................................................................82

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 9
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CLKDIV
Edge Clock Dividers
DDR
Double Data Rate
DLL
Delay-Locked Loops
DM
Data Mask
DSP
Digital Signal Processing
IDDR
Input DDR
ECLK
Edge Clock
ODDR
Output DDR
PCB
Printed Circuit Board
PCLK
Primary Clock
PIO
Programmable I/O
SDR
Single Data Rate
SSN
Simultaneous Switching Noise

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-TN-02035-1.3
1. Introduction
The ECP5™ and ECP5-5G™ devices support high-speed I/O interfaces, including Double Data Rate (DDR) and Single Data
Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge
of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling the
performance. ECP5 and ECP5-5G device I/O also have dedicated circuitry that is used along with the DDR I/O to support
DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 SDRAM memory interfaces.
This document discusses how to utilize the capabilities of the ECP5 and ECP5-5G devices to implement high-speed
generic DDR interface and the DDR memory interfaces. Refer to the Implementing DDR Memory Interfaces section of
this document for more information.
2. External Interface Description
This technical note uses two types of external interface definitions, centered and aligned. A centered external interface
means that, at the device pins, the clock is centered in the data opening. An aligned external interface means that, at
the device pins, the clock and data transition are aligned. This is also sometimes called edge-on-edge.
Figure 2.1 shows the external interface waveform for SDR and DDR.
Figure 2.1. External Interface Definitions
The interfaces described are referenced as centered or aligned interfaces. An aligned interface needs to adjust the
clock location to satisfy the capture flip-flop setup and hold times. A centered interface needs to balance the clock and
data delay to the first flip-flop to maintain the setup and hold already provided.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 11
3. High-Speed I/O Interface Building Blocks
ECP5 and ECP5-5G devices contain dedicated functions for building high-speed interfaces. This section describes when
and how to use these functions. A complete description of the library elements, including descriptions and attributes, is
provided at the end of this document.
Figure 3.1 shows a high-level diagram of the clocking resources available in the ECP5 and ECP5-5G devices for building
high-speed I/O interfaces.
Figure 3.1. ECP5 and ECP5-5G Device Clocking Diagram
A complete description of the ECP5 and ECP5-5G device family clocking resources and clock routing restrictions are
available in ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200).
Below is a brief description of each of the major elements used for building various high-speed interfaces. The DDR
Software Primitives and Attributes section of this document describes the library elements for these components.
3.1. Edge Clocks
Edge Clocks (ECLK) are high-speed, low-skew I/O dedicated clocks. They are arranged in groups of two per I/O bank on
the left and right sides of the device. Each of these Edge Clocks can be used to implement a high-speed interface. There
is an Edge Clock Bridge (ECLKBRIDGECS) that allows you to build large interfaces by bridging the Edge Clocks from one
bank to the other on the same side or from one side to the other side.
3.2. Primary Clocks
Primary Clocks (PCLK) refer to the system clock of the design. The SCLK ports of the DDR primitives are connected to
the system clock of the design.
3.3. DQS Lane
A DQS Lane uses the embedded circuit for memory interfaces. Each DQS Lane provides a clock pair (DQSP and DQSN)
for the DQS strobe and up to 12 to 16 ports for DQ data and DM data mask signals. The number of DQS Lanes on the
device is different for each device size. ECP5 and ECP5-5G devices support DQS lanes on the left and right sides of the
device.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-TN-02035-1.3
3.4. PLL
The PLL provides frequency synthesis, with additional static and dynamic phase adjustment, as well. Four output ports
are provided, CLKOP, CLKOS, CLKOS2, and CLKOS3. All four outputs have the same set of dividers. There is one PLL per
corner on the biggest device, totaling to four PLLs on each device.
3.5. DDRDLL
The DDRDLL is a dedicated DLL for creating the 90° clock delay. The DDRDLL outputs delay codes that are used in the
DQSBUF elements to delay the DQS input or in the DLLDEL module to delay the input clock. There is one DDRDLL at
each corner of the device, totaling to four DDRDLLs on each device. The DDRDLL on the top corners of the device can
drive delay codes to two adjacent edges of the device, providing a possible two DDRDLL codes for an edge.
DLLDEL
DLLDEL DLLDEL
DQSBUFDQSBUF
ULC_DDRDLL
LLC_DDRDLL LRC_DDRDLL
URC_DDRDLL
Figure 3.2. DDRDLL Connectivity
3.6. DQSBUF
There is one DQSBUF for each DQS lane (every 12 to 16 I/O depending on the selected device). The DQS input is used
when interfacing to DDR memories. It generates the delay on the DQS pin of the DQS lane, to provide a 90o phase shift
on DQS to clock the DDR data at the center. The delay is set by a delay code generated in the DDRDLL component. Each
DQSBUF can receive delay codes from two different DDRDLs hence two different DDR memory interfaces can be built
on one side of the device.
Each of the DQSBUF modes has an additional feature that allows you to adjust the delay from the delay set by the
DDRDLL code, by using the MOVE and DIRECTION inputs controlled by the user logic. The LOADN resets the delay back
to the DDRDLL code.

ECP5 and ECP5-5G High-Speed I/O Interface
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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-TN-02035-1.3 13
3.7. DLLDEL
DLLDEL provides phase shift on the receive side clocks to each ECLK. It functions similar to the DQSBUF, shifting the
clock input by delay set by the DDRDLL delay code, before the clock drives the clock tree. The DLLDEL element has the
ability to further adjust the delay from the delay set by the DDRDLL code, by using the MOVE and DIRECTION inputs
controlled by the user logic. The LOADN resets the delay back to the DDRDLL code.
3.8. Input DDR (IDDR)
The input DDR function can be used in either 1x (2:1), 2x (4:1), or 7:1 gearing modes. In the 1x mode, the IDDR module
inputs a single DDR data input and SCLK (primary clock) and provides a 2-bit wide data synchronized to the SCLK
(primary clock) to the FPGA fabric.
The 2x gearing is used for interfaces with data rate higher than 400Mbps which would require higher than 200 MHz
system clock. There the IDDR element inputs a single DDR data input and DQS clock (for DDR memory interface) or
ECLK (for all other high-speed interfaces) and provides a 4-bit wide parallel data synchronized to SCLK (primary clock) to
the FPGA fabric.
In the 7:1 mode, mostly used in video applications required 7:1 interface, the IDDR element inputs a single DDR data
input and ECLK and output a 7-bit wide parallel data synchronized to SCLK (primary clock) to the FPGA fabric.
3.9. Output DDR (ODDR)
The output DDR function can also be supported in 1x (2:1), 2x (4:1), or 7:1 gearing modes. In the 1x mode, the ODDR
element receives 2-bit wide data from the FPGA fabric and generates a single DDR data output and Clock output.
Similar to input interfaces the 2x gearing is used for data rate higher than 400 Mbps which would require higher than
200 MHz system clock. Here the ODDR element receives 4-bit wide data from the FPGA fabric and generates a single
DDR data output and clock output. The 2x element uses high-speed edge clock (ECLK) to clock the data out for generic
high-speed interfaces and DQS clock for DDR memory interfaces.
In 7:1 mode, the ODDR element receives 7-bit wide data from FPGA fabric and generates a single DDR data output and
Clock output. The 7:1 element sends out data using high-speed edge clock.
3.10. Edge Clock Dividers (CLKDIV)
Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK inputs
to the DDR) and drives to the Primary Clock routing to the fabric. There are two clock dividers on each side of the
device.
3.11. Input/Output DELAY
There are two different types of input/output data delay available. Both DELAYF and DELAYG provide a fixed value of
delay to compensate for clock injection delay. The DELAYF element also allows you to set the delay value using 128
steps of delay. Each delay step generates ~25 ps of delay. In DELAYF, you can overwrite the DELAY setting dynamically
using the MOVE and DIRECTION control inputs. The LOADN resets the delay back to the default value.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-TN-02035-1.3
4. Building Generic High Speed Interfaces
This section describes in detail on how the high-speed interfaces that can be built using the building blocks described in
the section above. The Clarity Designer tool in Lattice Diamond design software builds these interfaces based on
external interface requirements.
4.1. Types of High-Speed DDR Interfaces
This section describes the different types of high-speed DDR interfaces available in ECP5 and ECP5-5G devices.
Table 4.1 lists these interfaces. The naming conventions use for each interface are provided below the table.
Table 4.1. Generic High-Speed I/O DDR Interfaces
Mode
Interface Name
Description
Receive SDR
GIREG_RX.SCLK
SDR Input register using SCLK.
Receive DDRX1 Aligned
GDDRX1_RX.SCLK.Aligned
DDR 1x Input using SCLK. Data is edge-to-edge with incoming clock.
DLLDEL is be used to shift the incoming clock.
Receive DDRX1 Centered
GDDRX1_RX.SCLK.Centered
DDR x1 Input using SCLK. Clock is already centered in data window.
Receive DDRX2 Aligned
GDDRX2_RX.ECLK.Aligned
DDR x2 Input using ECLK. Data is edge-to-edge with incoming clock.
Generic DDR X2 using Edge Clock. DLLDEL is be used to shift the
incoming clock.
Receive DDRX2 Centered
GDDRX2_RX.ECLK.Centered
DDR x2 Input using ECLK. Clock is already centered in data window.
Receive DDRX2 MIPI
GDDRX2_RX.MIPI
DDRx2 Input using ECLK interfaces to MIPI interface. This uses
additional IMIPI module for the interface.
Receive DDRX71
GDDRX71_RX.ECLK
DDR 7:1 input using ECLK.
Transmit SDR
GOREG_TX.SCLK
SDR Output using SCLK. Clock is forwarded through ODDR.
TX DDRX1 Aligned
GDDRX1_TX.SCLK.Aligned
DDR x1 Output using SCLK. Data is edge-on-edge using same clock
through ODDR.
TX DDRX1 Centered
GDDRX1_TX.SCLK.Centered
DDR x1 Output using SCLK. Clock is centered using PLL with different
SCLK.
TX DDRX1 Centered
GDDRX2_TX.ECLK.Aligned
DDR x2 Output that is edge-on-edge using ECLK.
TX DDRX1 Centered
GDDRX2_TX.ECLK.Centered
DDR x2 Output that is pre-centered PLL generated 90o phase, and
output on ECLKs.
TX DDRX71
GDDRX71_TX.ECLK
DDR 7:1 output using ECLK. Data and CLK are aligned on first of 7 bits.
Note: The following describes the naming conventions used for each of the interfaces:
G –Generic
IREG –SDR Input I/O Register
OREG –SDR Output I/O Register
DDRX1 –DDR 1x gearing I/O Register
DDRX2 –DDR 2x gearing I/O Registers
_RX –Receive Interface
_TX –Transmit Interface
.ECLK –Uses ECLK (Edge Clock) clocking resource
.SCLK –Uses SCLK (Primary Clock) clocking resource
.Centered –Clock is centered to the data when coming into the device

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 15
5. High-Speed DDR Interface Details
This section describes each of the generic high-speed interfaces in detail, including the clocking to be used for each
interface. For detailed information about the ECP5 and ECP5-5G device clocking structure, refer to ECP5 and ECP5-5G
sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). The various interface rules listed under each interface
should be followed to build these interfaces successfully. Refer to the Timing Analysis for High Speed DDR Interfaces
section for more information about the timing analysis on these interfaces.
Some of these interfaces may require a soft IP in order utilize all the features available in the hardware. These soft IP
cores are available in Clarity Designer and are described in this section. Some of the soft IPs are optional and can be
selected in the Clarity Designer. Some of these are mandatory for the module to function as expected and are
automatically generated when building the interface through Clarity Designer.
5.1. GDDRX1_RX.SCLK.Centered
This a Generic 1x gearing Receive interface using SCLK. The clock is coming in centered to the data. This interface must
be used for speeds below 250 MHz.
This DDR interface uses the following modules:
IDDRX1F element to capture the data
The incoming clock is routed through the Primary (SCLK) clock tree
Static data delay element DELAYG is used to delay the incoming data enough to remove the clock injection time.
Optionally, you can choose to use Dynamic Data Delay adjustment using DELAYF element to control the delay on
the DATA dynamically. DELAYF also allows you to override the input delay set. The type of delay required can be
selected through Clarity Designer.
DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the correct
delay value can be set in the delay element.
The following figures show the static delay and dynamic delay options for this interface.
Figure 5.1. GDDRX1_RX.SCLK.Centered Interface (Static Delay)
Figure 5.2. GDDRX1_RX.SCLK.Centered Interface (Dynamic Data Delay)
Interface Requirements
The clock input must use a PCLK input so that it can be routed directly to the primary clock tree.
You must set the timing preferences as indicated in the Timing Analysis for High Speed DDR Interfaces section.

ECP5 and ECP5-5G High-Speed I/O Interface
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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-TN-02035-1.3
5.2. GDDRX1_RX.SCLK.Aligned
This a Generic 1x gearing Receive interface using SCLK. The clock is coming in edge aligned to the data. This interface
must be used for speeds below 250 MHz.
This DDR interface uses the following modules:
IDDRX1F element to capture the data
DDRDLLA/DLLDELD blocks are used to phase shift the incoming clock going to primary clock tree (SCLK).
Static data delay element DELAYG is used to delay the incoming data enough to remove the clock injection time.
Optionally, you can choose to use Dynamic Data Delay adjustment using DELAYF element to control the delay on
the DATA dynamically. DELAYF also allows you to override the input delay set. The type of delay required can be
selected through Clarity Designer.
DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the correct
delay value can be set in the delay element.
Dynamic Margin adjustment in the DDRDLLA module can be optionally used to adjust the DDRDLLA delay
dynamically.
The output of the DLLDELD module is also used as the clock input to the DDRDLLA which sends the delay values to the
DLLDELD module. The Receiver Synchronization (RX_SYNC) soft IP is required for the aligned interfaces to prevent
stability issues that may occur due to this loop at startup. The soft IP prevents any updates to the DLLDELD at start until
the DDRDLLA is locked. Once locked the DLLDELD is updated and FREEZE on the DDRDLL is removed. This soft IP is
automatically generated by Clarity Designer.
The following figures show the static delay and dynamic delay options for this interface.
ID DR X 1F
S C L K
DQ0
Q1
R S T
Datain Q[0]
Q[1]
C lkin
A
DE L A Y G
Z
DL L DE L D Z
A
DDR DE L
LO ADN
MOVE
DIR E C TION
C F L AG
C LK
R S T
UDDC NT LN
F R E E ZE
DDR DE L
LO C K
DDR DL L A
DC NT L[7:0]
“0”
“0”
(open)
P rimary
DE L _MODE =
S C L K _A L IG NE D
R eady
S TOP
DLL_LO C K
F R E E Z E
UDDC NT LN
DL L_R E S E T
DDR _R E S E T
S Y NC _C L K
R S T
UP D AT E
S ync_clk
S ync_reset
Update
R E AD Y
(open)
R X _S Y NC S clk
Dcntl[7:0]
Figure 5.3. GDDRX1_RX.SCLK.Aligned Interface (Static Delay)

ECP5 and ECP5-5G High-Speed I/O Interface
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 17
Data_LoadN
Data_Move
Data_Direction
A
DELAYF
LOADN
MOVE
DIRECTION
CFLAG
Datain
Q[0]
Q[1]
Clkin DLLDELD
Z
A
DDRDEL
LOADN
MOVE
DIRECTION
CFLAG
IDDRX1F
SCLK
DQ0
Q1
RST
CLK
RST
UDDCNTLN
FREEZE
DDRDEL
LOCK
DDRDLLA
DCNTL[7:0] Dcntl[7:0]
Clock_LoadN
Clock_Move
Clock_Direction
Clock_CFlag
Data_CFlag
7
Z
Primary
(optional)
DEL_MODE=SCLK_ALIGNED
STOP
DLL _LOCK
FREEZE
UDDCNTLN
DLL _RESET
DDR _RESET
SYNC_CLK
RST
UPDATE
Sync _clk
sync_reset
Update
READY
(open)
RX_SYNC (soft IP)
S clk
Figure 5.4. GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay)
Interface Requirements
The clock input must use a PCLK input so that it can be routed directly to the DLLDELD input
You must set the timing preferences as indicated in the Timing Analysis for High Speed DDR Interfaces section.
5.3. GDDRX2_RX.ECLK.Centered
Generic Receive DDR with the 2x gearing using Edge Clock Tree (ECLK). Input clock is centered to the input data. This
interface must be used for speeds above 400 MHz.
This DDR interface uses the following modules:
IDDRX2F element for X2 mode to capture the data
The incoming clock is routed to the Edge Clock (ECLK) clock tree through the ECLKSYNCB module.
CLKDIVF module is used to divide the incoming clock by 2 to generate the SCLK.
Static data delay element DELAYG to delay the incoming data enough to remove the clock injection time
Optionally, you can choose to use Dynamic Data Delay adjustment using DELAYF element to control the delay on
the DATA dynamically. DELAYF also allows you to override the input delay set. The type of delay required can be
selected through Clarity Designer.
DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the correct
delay value can be set in the delay element.
The ECLKBRIDGE can be optionally enabled if the data bus is crossing over between the left and right sides of the
device. If ECLKBRIDGE is enabled, then the ECLKBRIDGECS element should be used in the interface before the
ECLKSYNCB element. This element can be enabled through Clarity Designer.
The startup synchronization soft IP (GDDRX_SYNC) is required for this interface to tolerate the skew between the
ECLKSYNCB Stop input and the Reset to the DDR and CLKDIV modules.
The following figures show the static delay and dynamic delay options for this interface.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-TN-02035-1.3
ALIGNWD
Datain
Clkin
A
DELAYG Z
ECLKI
STOP ECLKO
SCLK
D
Q [3 :0 ]
RST
ALIGNWD
ECLK
IDDRX2F
Edge
Primary Sclk
CLKDIVF
CLKI
RST CDIVX
AlignWD
Q [3 :0 ]
ECLKSYNCB
DEL_MODE=
ECLK_CENTERED
sync_reset
GDDR _SYNC
Sync _ clk
Start
RST
START
SYNC _CLK
DDR _RESET
STOP
READY Ready
Figure 5.5. GDDRX2_RX.ECLK.Centered Interface (Static Delay)
Data _LoadN
Data _Move
Data _Direction
ADELAYF
LOADN
MOVE
DIRECTION
CFLAG
Datain
Data _CFlag
Z
ECLKI
STOP ECLKO
SCLK
D
RST
ALIGNWD
ECLK
Edge
Primary Sclk
CLKDIVF
CLKI
RST
ALIGNWD
CDIVX
AlignWD
Clkin
Q[3:0] Q[3:0]
IDDRX2F
ECLKSYNCB
sync_reset
GDDR _SYNC
Sync _clk
Start
RST
START
SYNC_CLK
DDR _RESET
STOP
READY Ready
DEL_MODE=ECLK_CENTERED
Figure 5.6. GDDRX2_RX.ECLK.Centered Interface (Dynamic Data Delay)
Interface Requirements
The clock input must use a PCLK input so that it can be routed directly to the Edge Clock tree.
ECLK must use the Edge Clock tree and the SCLK out of the CLKDIVF must use the Primary Clock tree, software
errors out if these dedicated clock routes are not used.
USE PRIMARY preference may be assigned to the SCLK net.
You must set the timing preferences as indicated in the Timing Analysis for High Speed DDR Interfaces section.
5.4. GDDRX2_RX.ECLK.Aligned
Generic Receive DDR with the 2x gearing with ECLK. Input Clock is coming in edge aligned to the data. This interface
must be used for speeds above 400 MHz.
This DDR interface uses the following modules:
IDDRX2F element for 2x mode to capture the data
DDRDLLA/DLLDELD blocks are used to phase shift the incoming clock routed to the Edge Clock (ECLK) clock tree
through the ECLKSYNCB module.
CLKDIVF module is used to divide the incoming clock by 2.
Static data delay element DELAYG to delay the incoming data enough to remove the clock injection time
Optionally, you can choose to use Dynamic Data Delay adjustment using DELAYF element to control the delay on
the DATA dynamically. DELAYF also allows you to override the input delay set. The type of delay required can be
selected through Clarity Designer.
DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the correct
delay value can be set in the delay element.
The ECLKBRIDGE can be optionally enabled if the data bus is crossing over between the left and right sides of the
device. If ECLKBRIDGE is enabled, then the ECLKBRIDGECS element should be used in the interface before the
ECLKSYNCB element. This element can be enabled through Clarity Designer.

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 19
Dynamic Margin adjustment in the DDRDLLA module can be optionally used to adjust the DDRDLLA delay
dynamically.
The output of the DLLDELD module is also used as the clock input to the DDRDLLA which sends the delay values to the
DLLDELD module. The Receiver Synchronization (RX_SYNC) soft IP is required for the aligned interfaces to prevent
stability issues that may occur due to this loop at startup. The soft IP prevents any updates to the DLLDELD at start until
the DDRDLLA is locked. Once locked the DLLDELD is updated and FREEZE on the DDRDLL is removed. This soft IP is
automatically generated by Clarity Designer.
The following figures show the static delay and dynamic delay options for this interface.
Datain
Clkin
A
DELAYG Z
DLLDELD Z
A
DDRDEL
LOADN
MOVE
DIRECTION
CFLAG
CLK
RST
UDDCNTLN
FREEZE
DDRDEL
LOCK
DDRDLLA
DCNTL[7:0]
“0”
“0”
(open )
ECLKI
STOP ECLKO
SCLK
D
RST
ALIGNWD
ECLK
Edge
Primary
CLKDIVF
CLKI
RST
ALIGNWD
CDIVX
alignwd
IDDRX2F
Q [3:0] Q[3:0]
ECLKSYNCB
dcntl[7:0]
STOP
DLL_LOCK
FREEZE
UDDCNTLN
DLL_RESET
DDR_RESET
SYNC_CLK
RST
UPDATE
Sync_clk
sync_reset
Update
READY Ready
RX_SYNC
DEL_MODE=
ECLK_CENTERED
Sclk
Figure 5.7. GDDRX2_RX.ECLK.Aligned Interface (Static Delay)
Data_LoadN
Data_Move
Data_Direction
A
DE L AY F
LOADN
MOVE
DIR E C TION
C F LAG
Datain
C lkin
DDR _reset
DL L DE L D Z
A
DDR DE L
LOADN
MOVE
DIR E C TION
C F LAG
C LK
R S T
UD DC NT LN
F R E E ZE
DDR DE L
LOC K
DDR DL L A
DCNTL[7:0] Dcntl[7:0]
C lock_L oadN
C lock_Move
C lock_Direction
C lock_C F lag
Data_C F lag
Z
E C L KI
S TOP
E C LK O
S C L K
D
R S T
ALIGNWD
E C LK
E dge
Primary S clk
C L K DIVF
C LK I
R S T
ALIGNWD
C DIVX
AlignWD
Q[3:0] Q[3:0]
IDDRX 2F
E C L K S Y NC B
(optional)
S TOP
DL L_L OC K
FR E E ZE
UD DC NT LN
DLL _R ES E T
DDR _R E S ET
S Y NC _C L K
R S T
UP DATE
S ync_clk
S ync_rst
Update
RE ADY
R X_S Y NC
Ready
DEL_MODE=ECLK_CENTERED
Figure 5.8. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay)

ECP5 and ECP5-5G High-Speed I/O Interface
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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-TN-02035-1.3
Interface Requirements
The clock input must use a dedicated PCLK input so that it can be routed directly to the DLLDEL module.
ECLK must use the Edge Clock tree and the SCLK out of the CLKDIVD must use the Primary Clock tree, software
errors out if these dedicated clock routes are not used.
USE PRIMARY preference may be assigned to the SCLK net.
You must set the timing preferences as indicated in the Timing Analysis for High Speed DDR Interfaces section.
5.5. GDDRX2_RX.MIPI
Generic Receive DDR for MIPI interfaces using the X2 gearing with ECLK. Clock is coming in centered to the data.
This interface must be used for speeds above 400 MHz.
This DDR interface uses the following modules:
IMIPI element use to receive the MIPI data and clock
The HSSEL of the IMIPI is used to switch between the High speed and Low Speed modes.
The HSSEL of IMIPI should be driven by a soft IP.
When in high-speed mode
The OHSOLS1 of the element is active.
The OHSOLS1 of the data IMIPI element is connected to the data input GDDRX2_RX.ECLK.Centered Interface.
The OHSOLS1 of the clock IMIPI is connected to the ECLK input GDDRX2_RX.ECLK.Centered Interface.
This is then treated similar to the GDDRX2_RX.ECLK.Centered Interface.
When in low speed mode:
Both the outputs of IMIPI are active since it is not a 2-bit interface.
The OHSLS1 is the bit 1 and OLS0 is the bit 0 of the interface.
Each of the data input and clock input is connected through a 20 ns filter soft IP to the core.
The ECLKBRIDGE can be optionally enabled if the data bus is crossing over between the left and right sides of
the device. If ECLKBRIDGE is enabled, then the ECLKBRIDGECS element should be used in the interface before
the ECLKSYNCB element. This element can be enabled through Clarity Designer.
Figure 5.9. GDDRX2_RX.MIPI
Interface Requirements
The clock input must use a PCLK input so that it can be routed directly to the Edge Clock tree.
ECLK must use the Edge Clock tree and the SCLK out of the CLKDIVF must use the Primary Clock tree, software
errors out if these dedicated clock routes are not used.
USE PRIMARY preference may be assigned to the SCLK net.
You must set the timing preferences as per section as indicated in the Timing Analysis for High Speed DDR
Interfaces section.