Lattice 7:1 LVDS User manual

www.latticesemi.com 1
tn1134_01.2
June 2007 Technical Note TN1134
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The Lattice 7:1 LVDS Video Demo Kit is a set of boards intended to bring RGB video data into the LatticeECP2™
FPGA where it can be processed and transmitted to an output display. It is intended to be used as a reference
design and to demonstrate the capabilities of the LatticeECP2 FPGA in video processing applications.
The complete kit consists of up to five boards. The heart of the kit is the LatticeECP2 Advanced Evaluation Board,
featuring a LatticeECP2-50 FPGA device. The kit is optionally available without this board.
The other four boards feature the required I/O interfaces to complete the demonstration. These are described in
more detail below.
About This Guide
This document includes descriptions of the design of the boards, the design of the IP for the LatticeECP2™ FPGA,
the items required to run the demonstration, and how to connect the boards and the cables for the demo.
Additional Resources
Additional resources related to the Lattice 7:1 LVDS Video Demo Kit, including updated documentation, HDL
source and bitstream programming files for the LatticeECP2 FPGA, a user’s guide for the LatticeECP2 Advanced
Evaluation Board, and other related materials can be downloaded from the Lattice web site at: www.lattices-
emi.com/boards. Navigate to the page for the Lattice 7:1 LVDS Video Demo Kit, and see the “documents and
downloads” link on the left side of the page.
7:1 Video Demonstration Setup and Design
Figure 1 is an overview of the connection between the boards, the required cables, and a block diagram of the
demo design implemented in LatticeECP2-50. The video signals are color-coded to indicate the different I/O stan-
dards including TMDS (pink), LVCMOS/LVTTL (orange), and LVDS (yellow).
Figure 1. Block Diagram of the Lattice 7:1 LVDS Video Demo Kit Setup
V
H
D
M
V
H
D
M
Gain
Control
Gain
Control
Gain
Control
RGB to YCbCr Converter
Contrast / Brightness / Hue /
Saturation Adjustments
LVDS 7:1 Rx
Deserializer
LVDS 7:1 Tx
Serializer
YCbCr to RGB Converter
Y CbCr
Y CbCr
R G B
R G B
Board #3
26-pin3MMDR
DS90CR287MTD
V
H
D
MTMDS
Receiver
(TI TFP401A )
Board #2
DVI
V
H
D
M
TMDS
Driver
(TI TFP410)
26-pin3MMDR
DS90CR288AMTD
60-pin
connection
Board #1 (or #4)
V
H
D
M
26-pin3MMDR
Desktop PC
DVD Player
ATSC Tuner
DVD
Board #1
V
H
D
M
26-pin 3M MDR
LCD Display
LatticeECP2 Advanced Evaluation Board
On-BoardSwitchs
Video
Adjustments
LatticeECP2-50 Device
MDR-26 Channel-Link Cable
DVI Cable
DVI Cable
OSD
MDR-26 Channel-Link Cable
60-pin
connection
DVI
TMDS signals
LVCMOS/LVTTL signals
LVDS signals
R G B
R G B
Lattice 7:1 LVDS Video Demo Kit
User’s Guide

2
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
In this setup, DVI-I video signals must first be generated by a PC or an equivalent source. On Video Demo board
#3, the TMDS signals of the DVI-I interface are first converted to LVCMOS/LVTTL using the TFP401A, then con-
verted again to LVDS using the DS90CR287MTD. These LVDS signals are then fed to the LatticeECP2-50 through
the MDR Channel Link cable and Video Demo Board #4. Video Demo Board #4 is connected to the LatticeECP2
Advanced Evaluation Board with a VHDM connector.
The demo design is implemented in the LatticeECP2-50 FPGA. This design is described in further detail later in
this guide, and is based on Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface. Source
code for this design is available in both the VHDL and Verilog languages. The LVDS video signal is de-serialized by
the LatticeECP2-50 for extracting the 8-bit R, 8-bit G, and 8-bit B pixel datum. Then the 8-bit R, G, B pixel datum
are adjusted by their own gain control block, and then the Contrast/Brightness/Hue/Saturation adjustment block,
before adding the OSD (On-Screen-Display). After the OSD is added to the video stream, the final R, G, B datum
are serialized and transmitted via the LatticeECP2-50 LVDS I/Os.
The remainder of the setup is similar to the video input side but reversed. The LVDS signals are fed via a VHDM
connector to the Video Demo board #1, then to the Video Demo board #2 via the MDR cable. The LVDS signals are
then converted to LVCMOS/LVTTL using the DS90CR288A on the Video Demo board #2. Finally the LVC-
MOS/LVTTL video signals are converted to the DVI / TMDS signals using the TFP410 and sent to the LCD display.
Figure 2 shows a complete Video Demo system setup, with an input source (laptop) and monitor. In this example,
power is supplied to Video Demo Boards 2 and 3 from an external source (not shown).
Figure 2. Video Demo System Setup
Prepare for the Video Demo
Before running the demo, you need the following video source and video sink.
• Video source: a desktop or a laptop PC with a DVI output port.
• Video sink: a LCD display with a DVI input port and a DVI cable.
Note: The display must be an actual DVI, digital display. Some DVI sources also include an RGB analog compo-
nent, which allow the use a simple VGA -> DVI converter to supply input to an analog VGA monitor. These con-
verters simply adapt the physical plugs to supply the RGB component signals contained in the DVI cable to a
VGA style plug. However, this video demo kit does not re-transmit any analog component signals; the output is
purely digital. As such, a simple converter will not work.

3
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
If your PC does not have a DVI output, you may purchase a VGA-to-DVI converter (such as the CP-261D) to con-
vert your PC’s video signal from VGA to DVI. The PC screen resolution needs to be set to any of the following to run
this demo.
• 640x480, 75Hz
•800x600, 60Hz or 75Hz
• 1024x768, 60Hz or 75Hz
• 1152x864, 75Hz
•1280x1024, 60Hz
The Lattice 7:1 Video Demo Kit includes the following items:
Table 1. Lattice 7:1 Video Demo Kit Contents
Item Description Quantity
1 LatticeECP2 672fpBGA Advanced Evaluation board
1
1
2 5V wall-mount power adapter
1
1
3 Video Demo board #1 1
4 Video Demo board #4
2
1
5 Video Demo board #2 1
6 Video Demo board #3 1
7 DVI cable 1
8MDR-26 Channel-Link cable 2
9 Black banana plug cable 2
10 Red banana plug cable 2
1. The Lattice 7:1 Video Demo Kit is available with or without the LatticeECP2 Advanced
Evaluation Board and 5V wall-mount power adapter.
2. Some early versions of this kit may include a modified version of “Video Demo Board #1”
as a substitute for the “Video Demo Board #4”. In these cases, Video Demo Board #4 can
be differentiated by two small wires connected to the MDR I/O. See the diagram below for
an example. In this document, this board will be referenced only as “Video Demo Board
#4”, as the function of either version is the same.

4
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 3. Lattice 7:1 Video Demo Kit Contents
After you verify you have the proper equipment for the video demo, make sure all the jumpers on the boards are set
correctly. The default jumper settings of Video Demo Boards #2 and #3 are shown below. The detailed functions of
these jumpers can be found in Appendix A and Appendix B at the end of this user’s guide.
• Video Demo Board #2 Default Jumper Settings:
– Install jumpers on pin1-pin2 of J3, J7, J8, J9, J11, J13 and J21.
– Install jumpers on pin2-pin3 of J10 and J12.
– Install jumpers on pin1-pin3 of J4 and J6.
– Install jumper on pin4-pin6 of J5.
RS-232
LatticeECP2-50
672 fpBGA
LCD
1
3.3V
VIN
GND
ADJ
PAC
1.2V
1.8V
2.5VDDR2 DIMM 0
sysCONFIG
DDR2 DIMM 1
Compact Flash
NS
LatticeECP2 Advanced Evaluation Board Video Demo Board #2Video Demo Board #3
Video Demo Board #1 Video Demo Board #4 or the reworked Video Demo Board #1
5V Wall-Mount Power Adapter DVI Cable MDR-26 Channel-Link Cable Black Banana PlugCable
Red Banana PlugCable
x 2
x 2
x 2
x 1
or
x 1 x 1
x 1 x 1
x 1 x 1
Video
Demo 2
NS
Video
Demo 3
TI
TI
USB
Type B
USB
Type A
G-PHY
OSC
Socket
Ethernet
RJ-45
RJ-45

5
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
• Video Demo Board #3 Default Jumper Settings:
– Install jumpers on pin1-pin2 of J4, J5, J10 and J11.
– Install jumpers on pin2-pin3 of J6, J7, J8and J9.
– Install jumper on pin3-pin4 of J3.
Figure 4. Block Diagram and Default Jumper Settings of Video Demo Boards #2 and #3
For the I/O bank voltage setting on the LatticeECP2 Advanced Evaluation Board, bank 2 and bank 3 must be to be
set to 2.5V. Bank 0, 1, 4, 7 should all be set to 3.3V. The following table shows the proper jumper settings for the
Lattice 7:1 Video Demo.
Table 2. Jumper Settings for the LatticeECP2 Advanced Board
sysIO Bank Jumper Jumper on Pins
0 J14
1-3 -> VCC_3.3V
2-4 -> VCC_2.5V
3-5 -> VCC_1.8V
4-6 -> VCC_ADJ
1 J39
2 J40
3 J41
4J28
7 J27
5NA Tied to 1.8V
(Cannot be changed)
6
DVI Molex
74320-1004
3M 10226-1210VE
NS
LED
TI
TFP410
J13
J7 J8 J9
J10 J11 J12
J4
J5
J6
LED
J3
J19
J18
J20
J2
J14
J15
J16
J17
TI
TFP401A
3M 10226-1210VE
NS
LED
LED
J1
J19
J13 J14 J15
J3
J4
J18J17
J16
J5
J11
J10
J9
J8
J7
J6
J12
J21
Video Demo 2
Video Demo 3
Board #2 Board #3
3.3V3.3VGND GND
DVI Molex
74320-1004
2.5V
Pin-2
3.3V
ADJ
1.8V
Pin-1
Pin-6
Pin-5

6
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Jumpers J34 and J55 are used for the JTAG chain connection setting. Please make sure they are at their default
settings (J34: short and J55: open), which makes the LatticeECP2-50 the only device in the JTAG chain.
The OSD of this demo is controlled by a LatticeMico8™ microprocessor that requires an external clock from the
on-board oscillator. If a full size oscillator is used, make sure the oscillator on Y2 is installed on pins 1, 7, 10 and 16,
as seen in Figure 5. If a half size oscillator is used, make sure the oscillator on Y2 is installed on pins 1, 4, 13 and
16. In addition, Jumper J18must be shorted to connect the oscillator clock output to the LatticeECP2-50 device.
The locations of these jumpers are shown below.
Figure 5. Jumper Settings on the LatticeECP2 Advanced Evaluation Board
If you are using the optional CP-261D VGA-to-DVI converter to convert your PC’s video signal from VGA to DVI, set
both the input switches and the output switches to “RGB”.
Boards and Cables Connections
Once you have everything needed for the demo and all the board settings are correct, you may start connecting the
boards and cables, step by step. If this is your first time to run this demo, it’s highly recommended to follow the
steps below.
• Step 1: Install Board #1 and Board #4
Boards #1 and #4 convert the LVDS signals on the MDR-26 Channel Link cable to the VHDM connector, so the
LVDS signals can be transmitted to the LatticeECP2-50 672 fpBGA device.
J34:Short
3.3V
2.5V J55:Open
OSC installed on
Y2 pin-1,7,10,16
J18:Short

7
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Board #4 is used for the LVDS input on the Rx side and should be installed onto J36 of the LatticeECP2
Advanced Evaluation Board.
Board #1 is used for the LVDS output on the Tx side and should be installed onto J35 of the LatticeECP2
Advanced Evaluation Board.
After installation of these two boards, the boards should be perpendicular to the LatticeECP2 Advanced Evalua-
tion Board. Figure 6 shows the proper installation of Board #1 (Tx side on the left) and Board #4 (Rx side on the
right) installed on the LatticeECP2 Advanced Evaluation Board. (Note: in this figure, the Board #4 shown is the
earlier, modified version of Board #1).
Figure 6. Proper Installation of Video Demo Boards #1 and #4 to the Lattice ECP2 Advanced Evaluation
Board
• Step 2: Connect the MDR-26 Cables
The two MDR-26 Channel Link cables are used for connecting the Rx and the Tx LVDS signals. They are used
between the following boards:
– Rx: Between Video Demo board #3 and #4
– Tx: Between Video Demo board #2 and #1
Figure 7 shows the connections between these boards.

8
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 7. Proper Connection of the MDR-26 Channel Link Cables
• Step 3: Connect the DVI Cables
This demo requires two DVI cables. The video demo kit contains only one DVI cable. Therefore, you must use the
original DVI cable that comes with the LCD display as well.
If you are using a VGA-to-DVI converter to supply the DVI input, please be sure to set the converter’s input and
output switches to “RGB”, then connect the converter’s power, the VGA and DVI cables.
Before you connect the two DVI cables to the Video Demo boards #2 and #3, set the screen resolution to any of
those listed in the “Prepare for the Video Demo” section earlier in this document and check if your LCD display
can display the image properly at this resolution. Note that the DVI interface includes pins to allow the video
source getting the EDID (Extended Display Identification Data) from the video sink. These pins are not imple-
mented on Video Demo boards #2 and #3. Some video source will not send out the video stream if it is not get-
ting a proper EDID from the video sink. To prevent this from happening, you should first set the screen resolution
and check if the video stream is transmitting properly to the LCD display before disconnecting the DVI cable, then
reconnecting the cable to the demo system.
The DVI port of your PC should be connected to the Video Demo board #3. Video Demo board #2 should be con-
nected to the LCD display.
• Step 4: Connect the JTAG Download Cable
The JTAG download cable is used for downloading the demo bitstream from a PC to the LatticeECP2 FPGA
device. Connect it to the J46 on the LatticeECP2 Advanced Evaluation Board. The functions of the pins of J46
are shown on the board. Be sure the cable wires are connected to the right J46 pins. You should also make sure
there is a jumper installed on J34 and no jumper installed on J55, so that the LatticeECP2-50 is the only device
in the JTAG chain. For further information, see the LatticeECP2 Advanced Evaluation Board User Manual , avail-
able from the Lattice website at www.latticesemi.com/boards.
• Step 5: Connect the Power Cables
Video Demo boards #2 and #3 require 3.3V power which can be obtained from the LatticeECP2 Advanced Eval-
uation Board using the red and black banana plug cables.

9
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 8. Power Cable Connections for Lattice 7:1 LVDS Video Demo Kit
After connecting the banana plug cables, you should connect the 5V wall-mount power adapter to the
LatticeECP2 Advanced Evaluation Board. After completion of this step, the video demo system should look like
Figure 8.
• Step 6: Download the Video Demo Bitstream and Run the Video Demo
The DIP switch SW5 on the LatticeECP2 Advanced Evaluation Board controls several functions of this demo
design. The functions of these controls and their default settings are listed in the flowing table. When the specific
controls are selected, the push-button SW4 needs to be toggled to activate the adjustment. Note that once the
Auto-Demo is enabled, the OSD will be moving its position and bounce back when it hits the edge of the display.
This is for demonstration purpose and cannot be turned off.
Table 3. Switch for Video Color Adjustments, Demo and OSD Controls
SW5 Pin
Number ON (Pushed Down) OFF (Pulled Up)
Pin-1 R-gain or Contrast deselected R-gain or Contrast selected
Pin-2 G-gain or Brightness deselected G-gain or Brightness selected
Pin-3 B-gain or Hue deselected B-gain or Hue selected
Pin-4 Opacity or Saturation deselected Opacity or Saturation selected
Pin-5 OSD enabled OSD disabled
Pin-6 Auto-Demo enabled Auto-Demo disabled
Pin-7 Select RGBO group Select CBHS group
Pin-8Decrease the selected controls when SW4 is toggled Increase the selected controls when SW4 is toggled

10
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Now you can apply power to the demo system by turning on the SW6 of the LatticeECP2 Advanced Evaluation
Board. Then, launch ispVM
®
to download the demo bitstream. For full details on how to download the bitstream to
the LatticeECP2 FPGA, please refer to the LatticeECP2 Advanced Evaluation Board User Guide.
The bitstream file for this demo, as well as other resources, can be downloaded from the Lattice web site at:
www.latticesemi.com/boards. Navigate to the page for the Lattice 7:1 Video Demo Kit, and see the “documents and
downloads” link at the left of the page.
Video Demo Design Modules
This video demo design uses the Rx and Tx modules of Lattice reference design RD1030, LatticeECP2/M 7:1
LVDS Video Interface . For more information on this reference design, see the Lattice web site. Search for
“RD1030”, or navigate to the web page for the Lattice 7:1 LVDS Video Demo Kit at www.latticesemi.com/boards.
Figure 9 is a representation of the top level VHDL file of this design. The gray color blocks shown below are imple-
mented in other VHDL files. The light green color blocks are modules generated using the IPexpress tool included
with the Lattice ispLEVER design software.
Figure 9. Video Processing Design Example
7:1 LVDS Receiver
(LVDS_7_to_1_RX)
Rx Signal Mapping
7777
Gain
Ctrl
7:1 LVDS Transmitter
(LVDS_7_to_1_TX)
rx_d rx_c rx_brx_a
8883
r_G
8883
cbhs_G
r_Vsync
r_Hsync
r_DE
8883
t_G t_Vsync
t_Hsync
t_DE
7777
tx_d tx_c tx_btx_a
r_R
cbhs_R
t_R
r_B
cbhs_B
t_B
reset_sync
From DIP
Switch
CBHS Adjustment Inputs RGBO Adjustment Inputs
CBHS Adjustment Outputs RGBO Adjustment Outputs
RCLK_in
RA_in
RB_in
RC_in
RD_in
Delay
RGB_adj
8883
rgb_Grgb_R rgb_B
Delay
CBHS_adj
rgb_Vsync
rgb_Hsync
rgb_DE
cbhs_Vsync
cbhs_Hsync
cbhs_DE
Delay
OSD
Mico8 uP
8
TCLK_out
TA_out
TB_out
TC_out
TD_out
From
Pushbotton
Switch
(Contrast/Brightness/Hue/Saturation
Adjustments)
(On-Screen-Display Controlled by Mico8 uP)
Adjustment
Signals
Generation
Logic
Gain
Ctrl
Gain
Ctrl
Tx Signal Mapping

11
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
In addition to the Rx and Tx modules, this design also contains the modules for the RGB gain control, the Con-
trast/Brightness/Hue/Saturation controls, the OSD module and the LatticeMico8microprocessor that automatically
demonstrates the adjustments. These modules are an example design. You may implement other video applica-
tions in the LatticeECP2-50 FPGA using the video demo kit.
The Gain Control modules are 9x9 (9-bit by 9-bit) multipliers implemented using the sysDSP™ blocks of the
LatticeECP2 FPGA. The 9-bit gain value defines a positive real number between 0 and 1.99609375 with 1 bit of
integer part and 8bits of fractional part as shown in Figure 10.
Figure 10. 18-Bit Data Value
The R, G, B in this design are colors with 8-bit color depth. Each color is represented by 8binary bits. Before feed-
ing them to the multiplier’s multiplicand port, they are expanded from 8bits to 9 bits with the most significant bit set
to “0”. The R, G, B gains are real numbers between 0 and 1 and are feeding to the multiplier port. After reset, these
gains are set to their default values 1.0. The real number 1.0 is represented by the 9-bit binary “100000000”. The
maximum value of the gains are limited to 1.0. The product of the 9x9 multiplier is an 18-bit value with 10 integer
part bits and 8fractional part bits. However, only 8integer part bits (bit-15 down to bit-8) are passed to the OSD
module.
Figure 11 shows the block diagram of the 7:1 LVDS receiver module. This is the same receiver module as in the
Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface . There is an auto-alignment logic in the
receiver module that utilizes the deserialized data of RCLK_in to select the proper outputs of the four data pairs.
This ensures the four data outputs are aligned at the pixel boundary. This logic will be reset whenever the PLL lock
is lost. The DDR software primitives IDDRX2B with x2 gearing ratio are used for receiving the high speed 7:1 LVDS
video stream. The 4-bit output of the IDDRX2B modules will then be sent to the 4-to-7 deserializers. Refer to refer-
ence design RD1030 for more detailed information. This can be found on the Lattice web site at: www.lattices-
emi.com by searching for “RD1030”.
87 6 5 4 3 2 1 0
Fractional Part (8 bits)
MSB LSB
Gain
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Integer Part (10 bits) Fractional Part (8 bits)
MSB LSB
Product
8 7 6 5 4 3 2 1 0
Integer Part (9 bits)
MSB LSB
R/G/B
Integer Part (1 bit)

12
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 11. 7:1 Receiver Side Block Diagram
The block diagram of the 7:1 LVDS transmitter is shown in Figure 12. Four 7-to-4 serializers are used for serializing
the parallel R, G, B, VSYNC, HSYNC and DE signals. There is another serializer used for generating the LVDS out-
put clock. The “1100011” value is feeding to this serializer so that the generated LVDS clock has a clock/data rela-
tionship that complies to the Channel Link 7:1 LVDS specification. The 4-bit outputs of the serializers are sent to
the 2x gearing ODDRX2B modules for pumping out of the LVDS I/Os. For more information about the transmitter,
please refer to Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface .
IDDRX2B*
RA_in
IO DDR Registers
(2x gearing)
IDDRX2B*
IDDRX2B*
IDDRX2B*
IDDRX2B*
4:7
Deserializer
4:7
Deserializer
4:7
Deserializer
4:7
Deserializer
4:7
Deserializer
RB_in
RC_in
RD_in
RCLK_in
Auto Alignment
Module
4
4
4
4
4
7
7
77
RA_out
CLKOS
(CLKI x3.5)/2, 0deg
sysclockPLL
CLKOK
CLKI
CLKI x3.5, phase-shifted
7
7
7
7
7
7
7
7
7
7
RB_out
7
RC_out
7
RD_out
7
OutputSelect
7
RCK_out
LOCKDPHASE
phase
4
RST
reset_sync_out
reset_sync
RESET
ECLK
SCLK
reset_sync
generation
logic

13
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 12. Block Diagram of 7:1 LVDS Transmitter Module
Troubleshooting
Camera Link video camera is not supported.
Please note this kit uses the Channel-Link MDR-26 standard, not Camera-Link. These two LVDS video standards
use the same MDR-26 connector, but have different pinouts and data packet standards, and are not compatible.
Please use a standard DVI source such as a laptop or desktop computer or a Channel Link source to the LVDS.
No video output when everything is connected.
There are a number of possible causes, some of the most common include:
RST
ODDRX2B*
IO DDR Registers
(2x gearing)
ODDRX2B*
ODDRX2B*
ODDRX2B*
TA_in 7:4
Serializer
7:4
Serializer
7:4
Serializer
7:4
Serializer
TB_in
TC_in
TD_in
CLK_Tx
4
4
4
4
TA_out
CLKOP
(CLKI x3.5)/2, 0deg
sysCLOCK PLL
CLKOK
CLKI
CLKI x3.5, 0deg
TB_out
TC_out
TD_out
LOCK
RESET
RST_Tx ECLK
SCLK
ODDRX2B*
7:4
Serializer
“1100011”
4
TCLK_out
7
7
7
7

14
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
1. Boards #1 and #4 are not installed properly. After these boards are installed on the LatticeECP2 Advanced
Evaluation Board, the metal pieces of the VHDM connectors of Boards #1 and #4 should be touching each
other.
2. If using a computer for the DVI source, it may need to identify the monitor for initialization. Refer to the
Boards and Cable Connections section of this document, Step #3.
3. Check switches and jumpers:
Make sure that DIP switch SW1, switches 1 and 2 on the LatticeECP2 Advanced Evaluation Board, are in
the up position to correctly set the power supply options.
There are a number of other jumper and switch settings which may affect the operation of the demo. Be
sure to check the jumpers and switches on all the video demo boards, as well as the LatticeECP2
Advanced Evaluation Board.
4. The red LEDs on Boards #2 and #3 are not turned on. These LEDs indicate the 3.3V powers on these
boards are properly supplied. All of the different power supplies on the LatticeECP2 Advanced Evaluation
Board are controlled by the Lattice Power Manager II POWR1220AT8. If SW1 Pin 1 is on (pushed down),
the POWR1220AT8device will be reset and all powers including the 3.3V will be disabled.
5. The monitor being used is a VGA monitor with a DVI -> VGA adapter. The monitor must be a DVI, digital
monitor. There is no analog component output from the Video Demo. See the Preparing for the Video
Demo section of this document for more information.
6. Make sure your monitor source is set to the supported resolutions and refresh rates listed in the “Prepare
for the Video Demo” section earlier in this document.
Testing for Board #2 and Board #3.
If you suspect that something may be wrong with Board #2 or #3, you may wish to test them independently as part
of the troubleshooting. To do this, disconnect Board #2 from the LatticeECP2 Advanced Evaluation Board and con-
nect its LVDS cable directly into the input of Board #3. This removes the FPGA from the circuit. The video path then
goes though the DVI - LVDS - DVI conversion and should be displayed. If it is not, refer to the Boards and Cable
Connections section of this document, step #3. Figure 13 shows this arrangement.
Figure 13. Setup to Test Boards #2 and #3
Note: Power connections are not shown in Figure 13, but power must be applied.
Desktop PC
LCD Display
Video
Demo 2
Video
Demo 3

15
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Ordering Information
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
[phone] (Outside North America)
e-mail: techsuppor[email protected]
Internet:www.latticesemi.com
Revision History
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Description
Ordering Part
Number
China RoHS Environment-
Friendly Use Period (EFUP)
LatticeECP2 7:1 Video Development Kit (Includes LatticeECP2
Advanced Evaluation Board) LFE2-50E-VID-EV
Lattice 7:1 Video Interface Kit HW-VID-KIT
Date Version Change Summary
December 2006 01.0 Initial release.
March 2007 01.1 Added Ordering Information section.
June 2007 01.2 Updated to match RD1030 version 01.2.
10

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Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Appendix A. Jumpers of the Video Demo Board #2
Table 4. Functions of the Jumpers on Video Demo Board #2
Jumper Function Description Default Setting
J3 /POWERDOWN
This is an active low control for forcing the DS90CR288A into the
powerdown mode. The DS90CR288A outputs stay low under the
powerdown mode.
Pin1 and Pin2 (high)
J4 CTL3 Multifunctional CTL3 input of TFP410. Pin1 and Pin3
J5 CTL2 Multifunctional CTL2 input of TFP410. Pin4 and Pin6
J6 CTL1 Multifunctional CTL1 input of TFP410. Pin1 and Pin3
J7 VREF
This is the input reference voltage used to select the swing range of
the TFP410 digital inputs. High-swing 3.3V input signal level is
selected by the default setting.
Pin1 and Pin2 (high)
J8EDGE Edge select or hot plug input of TFP410. Pin1 and Pin2 (high)
J9 DKEN Data de-skew enable control of TFP410. Pin1 and Pin2 (high)
J10 ISEL/RSTn
This is an active high I
2
C select signal of TFP410 used for enabling
the TFP410’s I
2
C interface. The I
2
C state machine can be reset by
bringing this signal low then back high. I
2
C is disable by the default
setting.
Pin2 and Pin3 (low)
J11 BSEL/SCL Input bus select or I
2
C clock input of TP410. Pin1 and Pin2 (high)
J12 DSEL/SDA DSEL or I
2
C bidirectional data line of TP410. Pin2 and Pin3 (low)
J13 PDN
This is an active low power down control of TP410. During power-
down mode, only the digital I/O buffers and I
2
C interface remain
active.
Pin1 and Pin2 (high)
J21 NS_VDD
The power of the DS90CR288A is supported through this jumper’s
default setting. This jumper is used for disconnecting the
DS90CR288A power and forcing its output to the high impedance
state. Note that the powerdown mode puts the DS90CR288A out-
puts into low state instead of high impedance state.
Pin1 and Pin2

17
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Appendix B. Jumpers of the Video Demo Board #3
Table 5. Functions of the Jumpers on Video Demo Board #3
Jumper Function Description Default Setting
J3 TxIN7
This jumper selects which multifunctional pins of the TFP401A
(CTL3, CTL2, or CTL1) is connected to the DS90CR287’s TxIN7
input. CTL2 is selected by default.
Pin3 and Pin4
J4 /POWERDOWN
This is an active low control for forcing the DS90CR287 into the
powerdown mode. The DS90CR287’s LVDS outputs stay in the
tri-state mode under powerdown mode.
Pin1 and Pin2 (high)
J5 OCK_INV
TFP401A’s ODCK Polarity - Selects ODCK edge on which pixel
data (QE[23:0] and QO[23:0]) and control signals (HSYNC,
VSYNC, DE, CTL1-3) are latched.
Pin1 and Pin2 (high)
J6 DFO TFP401A’s Output clock data format - Controls the output clock
(ODCK) format for either TFT or DSTN panel support. Pin2 and Pin3 (low)
J7 PIXS TFP401A’s Pixel select - Selects between one or two pixels per
clock output modes. Pin2 and Pin3 (low)
J8STAGN Staggered pixel select of TFP401A. Pin2 and Pin3 (low)
J9 ST Output strength select of TFP401A. The default setting set the
drive strength to low drive strength. Pin2 and Pin3 (low)
J10 PDN This is an active low power down control of TP401A. During pow-
erdown mode, all output buffers are in the high impedance state. Pin1 and Pin2 (high)
J11 PDON
This is an active low output drive power down control of TP401A.
During output drive powerdown mode, all output drivers except
SCDT and CTL1 are driven to a high impedance state.
Pin1 and Pin2 (high)

18
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Appendix C. Schematics of the Video Demo Boards #1, #2, #3 and #4
Video Demo Board #1
Figure 14. Video Demo Board #1 Schematic
5
5
4 4
3 3
2 2
1 1
D D C C BB A A
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #1
C
12
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #1
C
12
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #1
C
12
Lattice Semiconductor Corporation

19
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Figure 12. Video Demo Board #1 Schematic (Cont).
5
5
4 4
3 3
2 2
1 1
D D C C BB A A
TX_OUT1_N TX_OUT1_P TX_OUT2_N TX_OUT2_P TX_OUT3_N TX_OUT3_P TX_OUT0_N TX_OUT0_P TX_CLK OUT_ N TX_CLK OUT_ P
Title Size Document Number Rev Date: Sheet of
A
VHDM / MDR conversion
C
22
Title Size Document Number Rev Date: S heet of
A
VHDM / MDR conversion
C
22
Title Size Document Number Rev Date: S heet of
A
VHDM / MDR conversion
C
22
Back Side View
Lattice Semiconductor Corporation
Video Demo #1 Board
Back Side View
E6
F3
J5
E7
A3
E4
D7 A7
L10
J1
C5
K8
L1
A6
B10
E3E9
H8
B5
J7
K9
B4
C9
L3
A4
D2
C6
L9
K3
J4 G4 G2
B7B8
A1
C1
J9
B6
K6
E2
J8
F6
C2
L6
G8
J2
D8
F9
C10
E8 E1
F10 D10
A5
C8
A9A10
D3
K2
J3
K1
E5 F5
G7
L5
E10
D9
G1
K7
C3
B9
L4
A2
G5
A8
H10
L8
H7
G10
F4
L7
F7
D1
J6
F8 F1
K5
C4
H3
B1
H2
G3
H1
K10 K4
D5
F2
D4
H6
B3
H4
B2
G6
L2
C7
D6
G9
J10
H9 H5
1 2 3 4
5
6 7 8
9
10 11
12 13
14 15 16
17
18
19 20 21
22
23
24
25 26
J2
3M_Tx_10226-1210VE
J2
3M_Tx_10226-1210VE
DDC_Gnd_1
1
TxOut0-
14
TxOut0Gnd
2
TxOut0+
15
Sense
3
USB/DDC_Gnd
16
TxOut1-
4
TxOut1Gnd
17
TxOut1+
5
DDC/SDA
18
TxOut2-
6
TxOut2Gnd
19
TxOut2+
7
USB+
20
USB_Shield
8
USB-
21
DDC/SCL
9
TxClkOut-
22
TxClkOutGnd
10
TxClkOut+
23
USB_+5VDC
11
DDC_+5VDC
24
TxOut3-
12
TxOut3Gnd
25
TxOut3+
13
DDC_Gnd_26
26
Mounting_R
27
Mounting_L
28
J1
MOLEX VHDM 74031-0001
J1
MOLEX VHDM 74031-0001
A1 A1 A2 A2 A3 A3 A4 A4
A5 A5
A6 A6
A7 A7
A8 A8 A9 A9
A10 A10
B1 B1 B2 B2 B3 B3 B4 B4
B5 B5 B6 B6
B7 B7
B8 B8 B9 B9
B10 B10
C1 C1 C2 C2 C3 C3 C4 C4 C5 C5 C6 C6 C7 C7 C8 C8 C9 C9
C10 C10
D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9
D10 D10
E1 E1
E2 E2
E3 E3
E4 E4 E5 E5
E6 E6
E7 E7
E8 E8
E9 E9
E10 E10
F1 F1
F2 F2 F3 F3 F4 F4 F5 F5
F6 F6 F7 F7 F8 F8 F9 F9
F10 F10
GND_G1
G1
GND_G2
G2
GND_G3
G3
GND_G4
G4
GND_G5
G5
GND_G6
G6
GND_G7
G7
GND_G8
G8
GND_G9
G9
GND_G10
G10
GND_H1
H1
GND_H2
H2
GND_H3
H3
GND_H4
H4
GND_H5
H5
GND_H6
H6
GND_H7
H7
GND_H8
H8
GND_H9
H9
GND_H10
H10
GND_J1
J1
GND_J2
J2
GND_J3
J3
GND_J4
J4
GND_J5
J5
GND_J6
J6
GND_J7
J7
GND_J8
J8
GND_J9
J9
GND_J10
J10
GND_K1
K1
GND_K2
K2
GND_K3
K3
GND_K4
K4
GND_K5
K5
GND_K6
K6
GND_K7
K7
GND_K8
K8
GND_K9
K9
GND_K10
K10
GND_L1
L1
GND_L2
L2
GND_L3
L3
GND_L4
L4
GND_L5
L5
GND_L6
L6
GND_L7
L7
GND_L8
L8
GND_L9
L9
GND_L10
L10

20
Lattice 7:1 LVDS Video Demo Kit
Lattice Semiconductor User’s Guide
Video Demo Board #2
Figure 15. Video Demo Board #2 Schematic
5
5
4 4
3 3
2 2
1 1
D D C C BB A A
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #2
C
12
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #2
C
12
Title Size Document Number Rev Date: Sheet of
A
Video Demo Board #2
C
12
Lattice Semiconductor Corporation