Lattice LFE3-MEZZ-EVN User manual

September 2012
Revision: EB55_01.1

HDMI Mezzanine Card – Revision B 
User’s Guide

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HDMI Mezzanine Card – Revision B
User’s Guide
Introduction
LatticeECP3 Video Protocol Board includes a daughter card connection to support applications that can be imple-
mented using SERDES. This daughter card connection includes three connectors for the signals of a whole
SERDES quad, the control/status signals and the power/ground pins.
The HDMI Mezzanine Card is a LatticeECP3 Video Protocol Board daughter card designed for demonstrating the
Lattice HDMI/DVI solution using LatticeECP3 SERDES. The scope of this user’s guide covers only revision B of the
HDMI Mezzanine Card. Please refer to EB52, LatticeECP3 Video Protocol Board Revision C User’s Guide for more
information about the LatticeECP3 device connection to the daughter card.
As shown in Figure 1, this card uses Single-Link 19-pin HDMI Type-A connectors. If using passive HDMI-to-DVI
cables, this card can also be used to support DVI video.
Figure 1. HDMI Mezzanine Card
Features
• Supports two different HDMI/DVI input paths, with or without the cable equalizer
• Supports HDMI/DVI output with TMDS level shifter
• TOSLINK fiber optic receiving module for S/PDIF audio input
• Headers for HPD, CEC controls and the EDID signals
• ESD protection devices for both HDMI/DVI inputs and HDMI/DVI outputs
Functional Description
There are four transmit channels and four receive channels in each of the LatticeECP3 SERDES quads. For imple-
menting a Single Link HDMI or DVI interface, which includes three data channels and one clock channel, all four
transmit channels and three receive channels are used. The clock channel on the receive side is connected to the
dedicated SERDES differential reference clock pins. Since the common mode voltage of the HDMI/DVI TMDS sig-

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HDMI Mezzanine Card – Revision B
User’s Guide
nals is different from the SERDES CML signals, and the TMDS coding scheme maintains the DC balance of the
signal, the AC coupling capacitors are used to block the DC component of the driving signal.
Figure 2 shows the functional block diagram of the HDMI Mezzanine Card. For validation purposes, this card is
designed to include two HDMI/DVI input ports. One of these input paths has a TMDS cable equalizer and the other
does not. The signals of both paths will go into the 2-to-1 TMDS MUX, then the AC coupling capacitors to the
SERDES input pins. Depending on which pins a shunt is installed on a 3-pin header, one of the two inputs will be
selected and the signals will be fed to the SERDES.
For meeting the HDMI/DVI’s strict electrical compliance test specification, a TMDS level shifter is added to the out-
put path. This level shifter can be removed if the design does not have this requirement. The ESD protector is
added on both the input and output HDMI/DVI ports. Other than the HDMI/DVI, an S/PDIF input interface is also
included for bringing in a digital audio stream through the TOSLINK connector.
Figure 2. Functional Block Diagram
Regular
100-mil
Connector
10 Gbps Mezzanine Connector
AC Coupling
Data Pairs
Data Pairs
Clock
Data Pairs
Clock
Data Pairs
Clock
Data Pairs
Clock
Clock
2
2
2
2
6
2
6
6
6
2
6
6
AC Coupling
TMDS
2:1 Switch
(PI3HDMI1210-A)
4 Gbps
TMDS
Equalizer
(STDVE001)
3.4 Gbps
ESD
Protector
ESD
Protector
ESD
Protector
S/PDIF
TORX147
Output Input 2 Input 1
TMDS Clock
TMDS
Level Shifter
(STHDLS101T)
3.4 Gbps
Figure 3 shows the HDMI Mezzanine Card installed on the LatticeECP3 Video Protocol Board. The two cables are
the HDMI cables connecting to J1 (HDMI/DVI input) and J3 (HDMI/DVI output) of the daughter card. A 12 mm tall
standoff is recommended for securing the HDMI Mezzanine Card on the LatticeECP3 Video Protocol Board
through screws.

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 3. HDMI Mezzanine Card Installed on the LatticeECP3 Video Protocol Board
Header Settings
This section describes the header settings on the HDMI Mezzanine Card. However, since the card uses SERDES
quad C when plugging into the LatticeECP3 Video Protocol Board, the VCCOB and the VCCIB of SERDES quad C
need to be powered properly. Please make sure shuts are installed on J18 and J22 of the LatticeECP3 Video Pro-
tocol Board.
As mentioned previously, the selection of the two HDMI/DVI inputs is done by a 3-pin header. Ta b l e 1 shows the
locations of where the shunt should be installed.
Table 1. MUX Selection Control
HDMI/DVI
Input Mode MUX Select Shunt Installation on H13
J1 Equalized HDMI/DVI Input High Pin 1/Pin 2
J2 Non-Equalized HDMI/DVI Input Low Pin 2/Pin 3
Other than the TMDS clock and data pairs, the HDMI/DVI interface includes CEC, HPD and the DDC clock and
data signals. By installing shuts on different locations of the 12 headers, these signals can be selected to be
bypassed from the HDMI/DVI input to the HDMI/DVI output, or they can be selected to be connected to the
LatticeECP3 FPGA on the LatticeECP3 Video Protocol Board.
Figure 4 shows the locations of these 12 headers on the HDMI Mezzanine Card and the signals these headers
control. The 12 headers are divided into four groups as shown in Figure 4. Each group includes three headers for
controlling one of the four signals. The black square is used to indicate pin 1 of each header.

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 4. Headers for CEC, HDP, S Settings, LatticeECP3 Video Protocol Board
J3 (HDMI Out)
J1 (HDMI Input 1)
J2 (HDMI Input 2)
TOSLINK (S/PDIF)
H12, H11, H10, H9
H4, H3, H2, H1
H6, H5
H8, H7
J3 (HDMI Out)
J1 (HDMI Input 1)
J2 (HDMI Input 2)
TOSLINK (S/PDIF)
H10, H6, H2
are for SDA
control
H12, H8, H4 are for CEC control
J3 (HDMI Out)
J1 (HDMI Input 1)
J2 (HDMI Input 2)
TOSLINK (S/PDIF)
H9, H5, H1
are for SCL
control
H11, H7, H3 are for HPD control
J3 (HDMI Out)
J1 (HDMI Input 1)
J2 (HDMI Input 2)
TOSLINK (S/PDIF)
H12, H11, H10, H9
are associated with
HDMI Out
H4, H3, H2, H1
are associated with HDMI Input 1
H8, H7, H6, H5
are associated
with HDMI Input 2
Figure 5 is a conceptual connection of the header connections. This applies to all four signals. An example of the
connection is shown in Figure 6. In this example, the shunts are installed on pin1/pin 2 of H9 ~ H12 and pin2/pin3
of H1 ~ H4. This will bypass the four signals between J1 and J3.

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 5. Conceptual Connection for Headers H1 to H12
J3 (HDMI Out)
H12, H11,
H10, H9
H8, H7,
H6, H5
H4, H3,
H2, H1
LatticeECP3
FPGA
TMDS
Equalizer
J2 (HDMI Input 2)
J1 (HDMI Input 1)
Figure 6. Example for Bypassing CEC, HPD, SDA, SCL Between J1 and J3
H12, H11,
H10, H9
H8, H7,
H6, H5
H4, H3,
H2, H1
LatticeECP3
FPGA
TMDS
Equalizer
J3 (HDMI Out)
J2 (HDMI Input 2)
J1 (HDMI Input 1)
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
[phone] (Outside North America)
e-mail: techsuppor[email protected]
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
September 2010 01.0 Initial release.
September 2012 01.1 Added Appendix B. Hardware Variants.
Updated document with new corporate logo.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

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HDMI Mezzanine Card – Revision B
User’s Guide
Appendix A. Schematic

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 7. Cover Page
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COVER PAGE
Page Description
1 Cover Page
Block Diagram Power Scheme HDMI Input Ports HDMI Equalizer TMDS Switch
HDMI Output Port B To B Connectors and Audio Input Board Accessories
2 3 4 5 6 7 8 9
10
11
I2C, HPD, CEC Selection Revision History
HDMI MEZZANINE CARD - LATTICE SEMICONDUCTOR CORPORATION

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 8. Revision History
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Revision Verison Description
esaelerlaitinI10.0A
Release Date
18-May-2009
0.02 20-May-2009 Jumper options for DDC, HPD and CEC lines modified 0.03 27-May-2009 HDMI signals swapping done for layout feasibility 0.04 29-May-2009 Single Ended signals swapping done at control signal connector
for layout feasibility
0.05 02-Jun-2009 Pin Mapping table added for Mezzanine and control signal connectors 0.06 03-Jun-2009 Pin mapping table modified. Pullups added for output signals
from ECP3 board. SPDIF data assigned to MZ_CTRL13
0.07 09-Jun-2009 Customer Feedbacks implemented 0.08 0.09 0.10 0.11 0.12
10-Jun-2009 11-Jun-2009 15-Jun-2009 17-Jun-2009 24-Jun-2009
Customer Feedbacks implemented Version change after customer modification of schematics for HDMI Equivalizer Customer Feedbacks implemented Customer Feedbacks implemented Customer Feedbacks implemented on decoupling caps for U3, U8
B 0.01 11-Feb-2010 Clock cleaner is removed and eight 50ohms pullup resistors are added
for the HDMI output port as per customer requirement
0.02 2-Mar-2010 'GDA confidential' is removed from all pages as per customer feedback

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 9. Block Diagram
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BLOCK DIAGRAM

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 10. Power Scheme
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2
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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 11. HDMI Input Ports
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
HDMI1_DATA2+ HDMI1_DATA2+ HDMI1_DATA2- HDMI1_DATA2- HDMI1_DATA1+ HDMI1_DATA1- HDMI1_DATA0+ HDMI1_DATA0- HDMI1_CLK+ HDMI1_CLK-
HDMI1_DATA1+ HDMI1_DATA1-
HDMI1_DATA0+ HDMI1_DATA0-
HDMI1_CLK+ HDMI1_CLK-
HDMI1_ESDBYPASS
CEC_HDMI1 CEC_HDMI_IN1 SCL_HDMI1 SCL_HDMI_IN1 SDA_HDMI1 SDA_HDMI_IN1
HPD_HDMI_IN1
HDMI2_DATA2+ HDMI2_DATA2+ HDMI2_DATA2- HDMI2_DATA2- HDMI2_DATA1+ HDMI2_DATA1- HDMI2_DATA0+ HDMI2_DATA0- HDMI2_CLK+ HDMI2_CLK-
HDMI2_DATA1-
HDMI2_DATA1+
HDMI2_DATA0+
HDMI2_DATA0-
HDMI2_CLK- HDMI2_CLK+
CEC_HDMI2 CEC_HDMI_IN2
SCL_HDMI2 SCL_HDMI_IN2
SDA_HDMI2 SDA_HDMI_IN2
HPD_HDMI_IN2
HDMI2_ESDBYPASS
CEC2_PULL
HDMI2_DATA2+
HDMI2_DATA2- HDMI2_DATA1+ HDMI2_DATA1- HDMI2_DATA0+ HDMI2_DATA0- HDMI2_CLK+ HDMI2_CLK- CEC_HDMI2
SCL_HDMI2
SDA_HDMI2
HPD_HDMI2
HPD_HDMI1 HDMI1_DATA2+ HDMI1_DATA2- HDMI1_DATA1+ HDMI1_DATA1- HDMI1_DATA0+ HDMI1_DATA0- HDMI1_CLK+ HDMI1_CLK- CEC_HDMI1
SCL_HDMI1
SDA_HDMI1
CEC1_PULL
J1SC L J1SD A
J2SC L J2SD A
HPD_HDMI1
HPD_HDMI2
VDD_3V3
VDD_5V0
VDD_3V3VDD_5V0
VDD_5V0_HDMI2 VDD_5V0_HDMI1
HDMI1_DATA0+ [7] HDMI1_DATA0- [7] HDMI1_DATA1+ [7] HDMI1_DATA1- [7]
HDMI1_DATA2+ [7] HDMI1_DATA2- [7] HDMI1_CLK+ [7]
HDMI1_CLK- [7]
SCL_HDMI_IN1 [6] SDA_HDMI_IN1 [6]
HPD_HDMI_IN1 [6]
CEC_HDMI_IN1 [6]
HDMI2_DATA0- [8]
HDMI2_DATA1+ [8] HDMI2_DATA2+ [8]
HDMI2_DATA1- [8]
HDMI2_CLK+ [8]
HDMI2_DATA2- [8] HDMI2_CLK- [8] SCL_HDMI_IN2 [6] HPD_HDMI_IN2 [6] SDA_HDMI_IN2 [6]
HDMI2_DATA0+ [8]
CEC_HDMI_IN2 [6]
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HDMI INPUT PORTS
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HDMI INPUT PORTS
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HDMI INPUT PORTS
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HDMI INPUT PORTS
PIN NO
TMDS DATA2+ TMDS DATA2 SHIELD TMDS DATA2- TMDS DATA1+ TMDS DATA1 SHIELD TMDS DATA1- TMDS DATA0+ TMDS DATA0 SHIELD
1
TMDS DATA0- TMDS CLOCK+ TMDS CLOCK SHIELD TMDS CLOCK- CEC NC SCL SDA DDC/CEC GROUND +5V POWER HOT PLUG DETECT
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
NAME
HDMI Input -2
HDMI Input -1
Note ---------- The 5V Supply of the HDMI Input connectors are not used in the Mezz card since there is no EDID EEPROM available in the card
R7 2KR7 2K
C27
0.1uF
10V
C27
0.1uF
10V
R1 27KR1 27K
R8 1KR8 1K
C28
0.1uF
10V
C28
0.1uF
10V
R67 51ER67 51E
J2
500254_1927
J2
500254_1927
11
22
33 44 55
66
77 88
99
10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19
20
20
21
21
22
22
23
23
R6 2KR6 2K
U1
CM2021
U1
CM2021
5V_SUPPLY 1 LV_SUPPLY 2
NC
38
TMDS_D0-_2
27
TMDS_D1-_1 9
TMDS_D1-_2
30
TMDS_D1+_1 7
TMDS_D1+_2
32
TMDS_D2+_1 4
TMDS_D2+_2
35
TMDS_GND1 5 TMDS_GND3 11
TMDS_GND4 14
TMDS_GND5
25
TMDS_GND6
28
TMDS_GND7
31
TMDS_GND8
34
GND1 3
GND2
36
CE_REMOTE_OUT
23
DDC_CLK_OUT
22
DDC_DAT_OUT
21
ESD_BYP
37
HOTPLUG_DET_OUT
20
TMDS_D0-_1 12
TMDS_CK1+ 13
TMDS_CK2+
26
TMDS_CK2-
24 TMDS_CK1- 15
CE_REMOTE_IN 16
DDC_CLK_IN 17
DDC_DAT_IN 18
HOTPLUG_DET_IN 19
TMDS_D0+_1 10
TMDS_D2-_1 6
TMDS_D0+_2
29
TMDS_D2-_2
33
TMDS_GND2 8
R69 51ER69 51E
D2
B340LA-13-F
D2
B340LA-13-F
21
R5 27KR5 27K
R70 51ER70 51E
C1
0.1uF
10V
C1
0.1uF
10V
R2 2KR2 2K
R4 1KR4 1K
TP2
Test_Pad
TP2
Test_Pad
11
J1
500254_1927
J1
500254_1927
11
22
33 44 55
66
77 88 99
10 10 11 11 12 12
13 13 14 14 15 15
16 16
17 17 18 18 19 19
20
20
21
21
22
22
23
23
D1
B340LA-13-F
D1
B340LA-13-F
21
U2
CM2021
U2
CM2021
5V_SUPPLY 1 LV_SUPPLY 2
NC
38
TMDS_D0-_2
27
TMDS_D1-_1 9
TMDS_D1-_2
30
TMDS_D1+_1 7
TMDS_D1+_2
32
TMDS_D2+_1 4
TMDS_D2+_2
35
TMDS_GND1 5
TMDS_GND3 11 TMDS_GND4 14
TMDS_GND5
25
TMDS_GND6
28
TMDS_GND7
31
TMDS_GND8
34
GND1 3
GND2
36
CE_REMOTE_OUT
23
DDC_CLK_OUT
22
DDC_DAT_OUT
21
ESD_BYP
37
HOTPLUG_DET_OUT
20
TMDS_D0-_1 12
TMDS_CK1+ 13
TMDS_CK2+
26
TMDS_CK2-
24 TMDS_CK1- 15
CE_REMOTE_IN 16
DDC_CLK_IN 17
DDC_DAT_IN 18
HOTPLUG_DET_IN 19
TMDS_D0+_1 10
TMDS_D2-_1 6
TMDS_D0+_2
29
TMDS_D2-_2
33
TMDS_GND2 8
R3 2KR3 2K
R68 51ER68 51E
C2
0.1uF
10V
C2
0.1uF
10V
TP1
Test_Pad
TP1
Test_Pad
11

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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 12. I2C, HPD, CEC Selection
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
SDA_HDMI1_EQ_EXT SDA_HDMI_IN1
SDA_HDMI_IN2
SCL_HDMI1_EQ_EXT SCL_HDMI_IN1 SCL_HDMI_IN2 HPD_HDMI1_EQ_EXT
HPD_HDMI_IN1 HPD_HDMI_IN2 CEC_HDMI_IN1 CEC_HDMI1_EQ_EXT CEC_HDMI_IN2 SCL_HDMIOUT_CM2020INT
SCL_HDMIOUT_LEVSHIFT
SDA_HDMIOUT_CM2020INT SDA_HDMIOUT_LEVSHIFT
HPD_HDMIOUT_LEVSHIFT HPD_HDMIOUT_CM2020INT CEC_HDMIOUT_CM2020INT CEC_HDMIOUT_MEZZCONN
CEC_HDMIOUT_CM2020INT
CEC_HDMIOUT_MEZZCONN CEC_HDMI_IN1 CEC_HDMI_IN2 CEC_HDMI1_EQ_EXT
HPD_HDMIOUT_CM2020INT
HPD_HDMIOUT_LEVSHIFT
HPD_HDMI_IN1
HPD_HDMI_IN2 HPD_HDMI1_EQ_EXT
SDA_HDMIOUT_CM2020INT SDA_HDMIOUT_LEVSHIFT
SDA_HDMI_IN1
SDA_HDMI_IN2 SDA_HDMI1_EQ_EXT
SCL_HDMIOUT_CM2020INT
SCL_HDMIOUT_LEVSHIFT
SCL_HDMI_IN1
SCL_HDMI_IN2
SCL_HDMI1_EQ_EXT
JMP_HPDJMP_CEC JMP_SCLJMP_SDA
SCL_HDMI1_EQ_EXT [7]
SDA_HDMI1_EQ_EXT [7]
SCL_HDMI_IN1 [5] SCL_HDMI_IN2 [5]
SDA_HDMI_IN1 [5]
SDA_HDMI_IN2 [5]
HPD_HDMI1_EQ_EXT [7] HPD_HDMI_IN1 [5]
HPD_HDMI_IN2 [5]
CEC_HDMI1_EQ_EXT [7] CEC_HDMI_IN1 [5]
CEC_HDMI_IN2 [5]
SCL_HDMIOUT_CM2020INT [10]
SDA_HDMIOUT_CM2020INT [10]
SCL_HDMIOUT_LEVSHIFT [10]
SDA_HDMIOUT_LEVSHIFT [10] HPD_HDMIOUT_CM2020INT [10] HPD_HDMIOUT_LEVSHIFT [10]
CEC_HDMIOUT_CM2020INT [10] CEC_HDMIOUT_MEZZCONN [11]
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GDA09CB004B
I2C, HPD, CEC SELECTION
611
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
I2C, HPD, CEC SELECTION
611
Tuesday, March 02, 2010
0.02
B
HPD, CEC, I2C SELECTION
H4
1x3
H4
1x3
1
12 23 3
H1
1x3
H1
1x3
1
12
23
3
H12
1x3
H12
1x3
1
12 23 3
H11
1x3
H11
1x3
1
12 23
3
H10
1x3
H10
1x3
1
12 23 3
H7 1x3 H7 1x3
1
12
23
3
H9
1x3
H9
1x3
1
12 23 3
H6 1x3 H6 1x3
1
12
23
3
H3
1x3
H3
1x3
1
12
23
3
H8 1x3 H8 1x3
1
12 23 3
H5 1x3 H5 1x3
1
12 23 3
H2
1x3
H2
1x3
1
12
23
3

14
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 13. HDMI Equalizer
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
HDMI_EQ_BOOST1 CEC_HDMI1_EQ_EXT HPD_HDMI1_EQ_EXT OE#_HDMI_EQUALIZER HDMI_EQ_BOOST2
CEC_HDMI1_EQ_INT
DDC_EN_EQUALIZER
REXT_EQ
SCL_HDMI1_EQ_INTSCL_HDMI1_EQ_EXT
SDA_HDMI1_EQ_EXT SDA_HDMI1_EQ_INT
HPD_HDMI1_EQ_INT
HPD_HDMI1_EQ_EXT CEC_HDMI1_EQ_EXT
SCL_HDMI1_EQ_EXT
SDA_HDMI1_EQ_EXT
CEC_HDMI1_EQ_INT SCL_HDMI1_EQ_INT
SDA_HDMI1_EQ_INT HPD_HDMI1_EQ_INT
HDMI1_CLK+ HDMI1_CLK- HDMI1_DATA0+ HDMI1_DATA0-
HDMI_EQ_DATA0+ HDMI_EQ_DATA0- HDMI_EQ_CLK+ HDMI_EQ_CLK-
PRE_EQUALIZER
OE#_HDMI_EQUALIZER HDMI_EQ_BOOST1 HDMI_EQ_BOOST2 DDC_EN_EQUALIZER
HDMI_EQ_DATA2-
HDMI_EQ_DATA2+
HDMI_EQ_DATA1+ HDMI_EQ_DATA1-
HDMI1_DATA1+
HDMI1_DATA1-
HDMI1_DATA2+
HDMI1_DATA2-
VDD_3V3
AGND
VDD_3V3
VDD_3V3 VDD_3V3
VDD_3V3
AGND
PRE_EQUALIZER [11] CEC_HDMI1_EQ_INT [11]
HDMI_EQ_BOOST1[11]
HDMI_EQ_BOOST2[11]
SDA_HDMI1_EQ_INT [11]
DDC_EN_EQUALIZER[11]
OE#_HDMI_EQUALIZER[11]
SCL_HDMI1_EQ_INT [11]
CEC_HDMI1_EQ_EXT[6]
SCL_HDMI1_EQ_EXT[6]
HPD_HDMI1_EQ_EXT[6] HPD_HDMI1_EQ_INT [11]
SDA_HDMI1_EQ_EXT[6]
HDMI1_CLK+[5]
HDMI1_CLK-[5]
HDMI1_DATA0+[5] HDMI1_DATA0-[5] HDMI_EQ_DATA0+ [8]
HDMI_EQ_DATA0- [8]
HDMI_EQ_CLK+ [8] HDMI_EQ_CLK- [8] HDMI_EQ_DATA2+ [8] HDMI_EQ_DATA2- [8] HDMI_EQ_DATA1+ [8]
HDMI_EQ_DATA1- [8]
HDMI1_DATA1+[5]
HDMI1_DATA1-[5] HDMI1_DATA2+[5] HDMI1_DATA2-[5]
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI EQUALIZER
711
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI EQUALIZER
711
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI EQUALIZER
711
Tuesday, March 02, 2010
0.02
B
HDMI EQUALIZER
De-Caps for HDMI Equalizer
CD61 0.01uF CD61 0.01uF
R13 47KR13 47K
R11 47KR11 47K
R56 4.7KnmR56 4.7Knm
CD5
0.1uF
10V CD5
0.1uF
10V
CD66 0.01uF CD66 0.01uF
CD11
0.1uF
10V CD11
0.1uF
10V
R57 4.7KnmR57 4.7Knm
B1 3000mAB1 3000mA
CD2
1000pF
50V CD2
1000pF
50V
CD62 0.01uF CD62 0.01uF
CD7
0.1uF
10V CD7
0.1uF
10V
R12 47KR12 47K
R62 4.7KR62 4.7K
CD15
0.1uF
10V CD15
0.1uF
10V
CD16
1000pF
50V CD16
1000pF
50V
R64 47KR64 47K
STDVE001A
U3
STDVE001A
STDVE001A
U3
STDVE001A
IN_D1-
38 IN_D1+
39
IN_D2-
41 IN_D2+ 42
IN_D3-
44 IN_D3+ 45
IN_D4-
47 IN_D4+ 48
OE#
25
VDD_EXT 11
VDD_INT 26
VCC1 2
VCC2 15
VCC3 21
VCC4 33
VCC5 40
VCC6 46
GND1
1
GND2
5
GND3
12
GND4
18
GND5
24
GND6
27
GND7
31
GND8
36
GND9
37
GND10
43
PRE 10
REXT 6
OUT_D1+ 22
OUT_D1- 23
OUT_D2+ 19
OUT_D2- 20
OUT_D3+ 16
OUT_D3- 17
OUT_D4+ 13
OUT_D4- 14
SCL_EXT
9
SDA_EXT
8SCL_INT 28
SDA_INT 29
HPD_EXT
7HPD_INT 30
CEC_IO
3CEC_IO_INT 4
DDC_EN
32
EQ_BOOST1
34
EQ_BOOST2
35
E_PAD
49
CD9
0.1uF
10V CD9
0.1uF
10V
CD14
1000pF
50V CD14
1000pF
50V
CD3
0.1uF
10V
CD3
0.1uF
10V
CD4
1000pF
50V CD4
1000pF
50V
B3 3000mAB3 3000mA
R66 47KR66 47K
R15 4.7KR15 4.7K
CD12
1000pF
50V CD12
1000pF
50V
CD63 0.01uF CD63 0.01uF
R65 47KR65 47K
R63 47KR63 47K
CD10
1000pF
50V CD10
1000pF
50V
R14 4.7KR14 4.7K
CD13
0.1uF
10V CD13
0.1uF
10V
CD1
0.1uF
10V CD1
0.1uF
10V
R9
4.70K
1%
R9
4.70K
1%
CD64 0.01uF CD64 0.01uF
CD8
1000pF
50V CD8
1000pF
50V
CD60 0.01uF CD60 0.01uF
CD59 0.01uF CD59 0.01uF
CD6
1000pF
50V CD6
1000pF
50V
R10 47KR10 47K
CD65 0.01uF CD65 0.01uF

15
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 14. TMDS Switch
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
TMDSSWITCH_CHAN_SEL
HDMIIN_CLK+ HDMIIN_CLK-
TMDS_SW _EN#
TMDS_SW_CP3 TMDS_SW_CP2 TMDS_SW_CP1
TMDS_SW _IN
TMDS_SW _1B2
TMDS_SW _0B2
TMDS_SW _1B1
TMDS_SW _0B1
TMDS_SW _A0 TMDS_SW _A1
HDMIIN_DATA0+ HDMIIN_DATA0-
DATA0+ DATA0-
HDMI2_CLK-
HDMI2_CLK+
HDMI2_DATA0+ HDMI2_DATA0- HDMI_EQ_CLK+
HDMI_EQ_CLK- HDMI_EQ_DATA0+
HDMI_EQ_DATA0- HDMI_EQ_DATA1+ HDMI_EQ_DATA1-
HDMI_EQ_DATA2- HDMI_EQ_DATA2+
HDMI2_DATA1-
HDMI2_DATA1+
HDMI2_DATA2+ HDMI2_DATA2-
DATA2-
DATA2+
DATA1+
DATA1-
HDMIIN_DATA1+ HDMIIN_DATA1- HDMIIN_DATA2+ HDMIIN_DATA2-
DATA2+
DATA2-
DATA1+
DATA1-
DATA0+
DATA0- HDMIIN_CLK- HDMIIN_CLK+
HDMIIN_CLEANED_CLK- HDMIIN_CLEANED_CLK+
VDD_3V3 VDD_5V0
VDD_3V3
VDD_5V0
VDD_3V3
VDD_3V3
VDD_3V3
HDMIIN_DATA0+ [11] HDMIIN_DATA0- [11]
HDMI2_CLK+[5]
HDMI2_CLK-[5]
HDMI2_DATA0+[5] HDMI2_DATA0-[5] HDMI_EQ_CLK+[7] HDMI_EQ_CLK-[7] HDMI_EQ_DATA0+[7] HDMI_EQ_DATA0-[7] HDMI_EQ_DATA1+[7] HDMI_EQ_DATA1-[7] HDMI_EQ_DATA2+[7]
HDMI_EQ_DATA2-[7]
HDMI2_DATA1+[5] HDMI2_DATA1-[5] HDMI2_DATA2+[5] HDMI2_DATA2-[5]
HDMIIN_DATA1+ [11] HDMIIN_DATA1- [11] HDMIIN_DATA2+ [11] HDMIIN_DATA2- [11]
HDMIIN_CLEANED_CLK+ [11] HDMIIN_CLEANED_CLK- [11]
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B TMDS SWITCH
811
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B TMDS SWITCH
811
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B TMDS SWITCH
811
Tuesday, March 02, 2010
0.02
B
TMDS SWITCH
De-Caps for TMDS Switch
HDMI Input Channel Select
SEL Pin = Low SEL Pin = High
Equalized HDMI Channel ----> TMDS Switch Output
Un Equalized HDMI Channel ----> TMDS Switch Output
Note --------- Side Band Channel Disabled
NOTE: Place resistors closer to AC coupling caps
NOTE: Place capacitors nearer to J4 as close as possible
CD27
0.1uF
10V CD27
0.1uF
10V
51R78 51R78
51R72 51R72
PI3HDMI1210-A
HDMI
SWITCH
U4
PI3HDMI1210-A
PI3HDMI1210-A
HDMI
SWITCH
U4
PI3HDMI1210-A
D0- 4
D0+ 3
D1- 6
D1+ 5
VDD3V3_1 1
VDD3V3_2 7
VDD3V3_3 14
VDD3V3_4 31
VDD3V3_5 40
VDD5V 22
GND1
13
GND2
15
GND3
17
GND4
19
GND5
25
GND6
30
D0+A
48
D0+B
39
D0-A
47
D0-B
38
CLK+A
42
CLK-A
41
CLK+B
33
CLK-B
32
D1+A
46
D1-A
45
D2+A
44
D2-A
43
D1+B
37
D1-B
36
D2+ 9
D2- 10
D2+B
35
D2-B
34
0B1
29
0B2
28
1B1
27
1B2
26
A0 18
A1 20
EN#
23
IN
21
SEL
8
CLK+ 11
CLK- 12
CP1 2 CP2 16 CP3 24
R20 4.7KR20 4.7K C6 0.1uFC6 0.1uF
H13
1x3
H13
1x3
11 22 33
51R79 51R79
CD19
0.1uF
10V CD19
0.1uF
10V
CD22
1000pF
50V CD22
1000pF
50V
C3 0.1uFC3 0.1uF
CD28
1000pF
50V CD28
1000pF
50V
R16 4.7KR16 4.7K
51R73 51R73
51R75 51R75
CD21
0.1uF
10V CD21
0.1uF
10V
C10
0.1uF
10V
C10
0.1uF
10V
R17 4.7KR17 4.7K
CD20
1000pF
50V CD20
1000pF
50V
C7 0.1uFC7 0.1uF
CD23
0.1uF
10V CD23
0.1uF
10V
C15 0.1uFC15 0.1uF
R19 4.7KR19 4.7K
R18 4.7KR18 4.7K C4 0.1uFC4 0.1uF C8 0.1uFC8 0.1uF
CD26
1000pF
50V CD26
1000pF
50V
CD17
0.1uF
10V CD17
0.1uF
10V
R21 4.7KR21 4.7K
CD18
1000pF
50V CD18
1000pF
50V
C14 0.1uFC14 0.1uF
51R74 51R74 51R76 51R76
C5 0.1uFC5 0.1uF
51R77 51R77
C9
0.1uF
10V C9
0.1uF
10V
R22 4.7KR22 4.7K
C11
0.1uF
10V C11
0.1uF
10V
CD25
0.1uF
10V CD25
0.1uF
10V
CD24
1000pF
50V CD24
1000pF
50V
R23 4.7KR23 4.7K

16
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 15. HDMI Output Port
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
OE#_HDMI_LEV_SHIFT
HPD_HDMIOUT_MEZZCONN
SCL_HDMIOUT_MEZZCONN
SDA_HDMIOUT_MEZZCONN
HDMIOUT_DDC_EN
TMDSOUT_DATA2+ TMDSOUT_DATA2- TMDSOUT_DATA1+ TMDSOUT_DATA1- TMDSOUT_DATA0+ TMDSOUT_DATA0- TMDSOUT_DATACLK+ TMDSOUT_DATACLK-
TMDSOUT_DATA2+
TMDSOUT_DATA2-
TMDSOUT_DATA1+
TMDSOUT_DATA1-
TMDSOUT_DATA0+
TMDSOUT_DATA0-
TMDSOUT_DATACLK+ TMDSOUT_DATACLK-
CEC_HDMIOUT_CM2020INT CEC_OUT SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT
SCL_OUT SDA_OUT
HPD_HDMIOUT_CM2020INT HPD_OUT
CM2020_ESDBP
SCL_HDMIOUT_LEVSHIFT HPD_HDMIOUT_LEVSHIFT REXT_HDMI_LEVSHIFTREXT_HDMI_LEVSHIFT SDA_HDMIOUT_LEVSHIFT ANALOG2ANALOG2
TMDSOUT_DATA2+
TMDSOUT_DATA2-
TMDSOUT_DATA1+
TMDSOUT_DATA1-
TMDSOUT_DATA0+
TMDSOUT_DATA0- TMDSOUT_DATACLK+ TMDSOUT_DATACLK- CEC_OUT
SCL_OUT
SDA_OUT
HPD_OUT
SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT
HPD_HDMIOUT_CM2020INT CEC_HDMIOUT_CM2020INT
SCL_HDMIOUT_LEVSHIFT
HPD_HDMIOUT_LEVSHIFT
SDA_HDMIOUT_LEVSHIFT
SCL_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT HPD_HDMIOUT_CM2020INT CEC_HDMIOUT_CM2020INT
HPD_HDMIOUT_MEZZCONN SCL_HDMIOUT_MEZZCONN SDA_HDMIOUT_MEZZCONN
TMDSOUT_DATA2-TMDSOUT_DATA2- TMDSOUT_DATA2+TMDSOUT_DATA2+ TMDSOUT_DATA1+TMDSOUT_DATA1+
TMDSOUT_DATA1-TMDSOUT_DATA1- TMDSOUT_DATA0+TMDSOUT_DATA0+
TMDSOUT_DATA0-TMDSOUT_DATA0- TMDSOUT_DATACLK+TMDSOUT_DATACLK+ TMDSOUT_DATACLK-TMDSOUT_DATACLK-
HDMIOUT_CLK+ HDMIOUT_CLK-
ST_HDMIOUT_CLK+ ST_HDMIOUT_CLK-
HDMIOUT_DATA2-
ST_HDMIOUT_DATA2+HDMIOUT_DATA2+ ST_HDMIOUT_DATA2- ST_HDMIOUT_DATA0+ ST_HDMIOUT_DATA0-
HDMIOUT_DATA0+
HDMIOUT_DATA0-
ST_HDMIOUT_DATA1+
ST_HDMIOUT_DATA1-
HDMIOUT_DATA1+ HDMIOUT_DATA1-
OE#_HDMI_LEV_SHIFT
HDMIOUT_DDC_EN
VDD_3V3
VDD_5V0
VDD_3V3 VDD_5V0_HDMIOUT
VDD_3V3
VDD_5V0_HDMIOUT
VDD_3V3
VDD_3V3
VDD_3V3
VDD_5V0_HDMIOUT
VDD_3V3
VDD_3V3
OE#_HDMI_LEV_SHIFT[11]
SCL_HDMIOUT_MEZZCONN[11]
HDMIOUT_DDC_EN[11]
HPD_HDMIOUT_MEZZCONN[11] SDA_HDMIOUT_MEZZCONN[11]
HPD_HDMIOUT_LEVSHIFT [6]
SCL_HDMIOUT_LEVSHIFT [6]
HPD_HDMIOUT_CM2020INT [6]
SCL_HDMIOUT_CM2020INT [6]
CEC_HDMIOUT_CM2020INT [6] SDA_HDMIOUT_CM2020INT [6]
SDA_HDMIOUT_LEVSHIFT [6]
HDMIOUT_CLK+[11] HDMIOUT_CLK-[11] HDMIOUT_DATA2+[11] HDMIOUT_DATA2-[11] HDMIOUT_DATA0+[11] HDMIOUT_DATA0-[11] HDMIOUT_DATA1+[11] HDMIOUT_DATA1-[11]
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI OUTPUT PORT
911
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI OUTPUT PORT
911
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
HDMI OUTPUT PORT
911
Tuesday, March 02, 2010
0.02
B
HDMI OUTPUT PORT
PIN NO
TMDS DATA2+ TMDS DATA2 SHIELD
TMDS DATA2-
TMDS DATA1+ TMDS DATA1 SHIELD TMDS DATA1- TMDS DATA0+ TMDS DATA0 SHIELD
1
TMDS DATA0- TMDS CLOCK+ TMDS CLOCK SHIELD TMDS CLOCK- CEC NC SCL SDA DDC/CEC GROUND +5V POWER HOT PLUG DETECT
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
NAME
De-Caps for HDMI Level Shifter
HDMI Output
De-Caps for HDMI Level Shifter
De-Caps for HDMI Level Shifter
CD57
0.1uF
10V CD57
0.1uF
10V
CD52
1000pF
50V CD52
1000pF
50V
C26 0.1uF C26 0.1uF
R46 47KR46 47K
R49 4.7KR49 4.7K
CD49
1000pF
50V CD49
1000pF
50V
CD44
0.1uF
10V
CD44
0.1uF
10V
CD72 0.01uF CD72 0.01uF
R53 4.7KR53 4.7K
C20 3.3uFC20 3.3uF
CD67 0.01uF CD67 0.01uF
CD58
1000pF
50V CD58
1000pF
50V
CD53
0.1uF
10V
CD53
0.1uF
10V
R45 47KR45 47K
R50 4.7KR50 4.7K
CD73 0.01uF CD73 0.01uF
C23 3.3uFC23 3.3uF
R42 4.7K R42 4.7K
CD45
1000pF
50V CD45
1000pF
50V
CD68 0.01uF CD68 0.01uF
R43 15K R43 15K
CD54
1000pF
50V CD54
1000pF
50V
CD74 0.01uF CD74 0.01uF
C17 3.3uFC17 3.3uF
R47 47KR47 47K
CD42
0.1uF
10V CD42
0.1uF
10V
CD46
0.1uF
10V CD46
0.1uF
10V
R51 4.7KR51 4.7K
B4 3000mAB4 3000mA
R44 4.70K 1% R44 4.70K 1%
C21 3.3uFC21 3.3uF
C25 0.1uFC25 0.1uFU7
CM2020
U7
CM2020
5V_SUPPLY
1
LV_SUPPLY
2
GND1
3
TMDS_D2+_1
4
TMDS_GND1
5
TMDS_D2-_1
6
TMDS_D1+_1
7
TMDS_GND2
8
TMDS_D1-_1
9
TMDS_D0+_1
10
TMDS_GND3
11
TMDS_D0-_1
12
TMDS_CK1+
13
TMDS_GND4
14
TMDS_CK1-
15
CE_REMOTE_IN
16
DDC_CLK_IN
17
DDC_DAT_IN
18
HOTPLUG_DET_IN
19 HOTPLUG_DET_OUT 20
DDC_DAT_OUT 21
DDC_CLK_OUT 22
CE_REMOTE_OUT 23
TMDS_CK2- 24
TMDS_GND5 25
TMDS_CK2+ 26
TMDS_D0-_2 27
TMDS_GND6 28
TMDS_D0+_2 29
TMDS_D1-_2 30
TMDS_GND7 31
TMDS_D1+_2 32
TMDS_D2-_2 33
TMDS_GND8 34
TMDS_D2+_2 35
GND2 36
ESD_BYP 37
5V_OUT 38
CD69 0.01uF CD69 0.01uF
C16 3.3uFC16 3.3uF
CD55
0.1uF
10V CD55
0.1uF
10V
R48 47KR48 47K
J3
500254_1927
J3
500254_1927
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20 20 21 21 22 22
23 23
R58 4.70K 1%
nm
R58 4.70K 1%
nm
C24 3.3uFC24 3.3uF
C18 0.1uFC18 0.1uF
CD47
1000pF
50V CD47
1000pF
50V
CD43
1000pF
50V CD43
1000pF
50V
R60 4.7KR60 4.7K
CD70 0.01uF CD70 0.01uF
CD56
1000pF
50V CD56
1000pF
50V
CD51
0.1uF
10V CD51
0.1uF
10V
C19 3.3uFC19 3.3uF
R54 27KR54 27K
STHDLS101T
U8
STHDLS101T
STHDLS101T
U8
STHDLS101T
ANALOG2 10
DDC_EN
32
HPD_SINK 30
HPD_SOURCE
7
OUT_D1- 23
OUT_D1+ 22
OUT_D2- 20
OUT_D2+ 19
OUT_D3- 17
OUT_D3+ 16
OUT_D4- 14
OUT_D4+ 13
REXT 6
SCL_SINK 28
SCL_SOURCE
9
SDA_SINK 29
SDA_SOURCE
8
VCC3V3_1 2
VCC3V3_2 11
VCC3V3_3 15
VCC3V3_4 21
VCC3V3_5 26
VCC3V3_6 33
VCC3V3_7 40
VCC3V3_8 46
GND1
1
GND2
5
GND3
12
GND4
18
GND5
24
GND6
27
GND7
31
GND8
36
GND9
37
GND10
43
IN_D1-
38 IN_D1+ 39
IN_D2-
41 IN_D2+
42
IN_D3-
44 IN_D3+ 45
IN_D4-
47 IN_D4+ 48
FUNCTION1
3
FUNCTION2
4
FUNCTION3
34
FUNCTION4
35
EPAD
49
OE#
25
R71 4.7KnmR71 4.7Knm
CD48
0.1uF
10V CD48
0.1uF
10V
R61 4.7KR61 4.7K
C22 3.3uFC22 3.3uF
CD71 0.01uF CD71 0.01uF
R52 4.7KR52 4.7K

17
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 16. B to B Connectors and Audio In
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
ST_S/PDIF_DATA S/PDIF_DATA
S/PDIF_DATA
VDD_3V3_TOSLINK
VDD_3V3
VDD_5V0 VDD_3V3
HDMIOUT_DATA0+ [10]
HDMIOUT_DATA0- [10]
HDMIIN_CLEANED_CLK-[9]
HDMIIN_CLEANED_CLK+[9]
HDMIOUT_DATA1- [10] HDMIOUT_DATA1+ [10]
HDMIOUT_DATA2- [10] HDMIOUT_DATA2+ [10]
HDMIOUT_CLK- [10]
HDMIOUT_CLK+ [10]
OE#_HDMI_LEV_SHIFT [10]
SDA_HDMIOUT_MEZZCONN[10]
HDMIOUT_DDC_EN[10] PRE_EQUALIZER [7]
OE#_HDMI_EQUALIZER[7] SCL_HDMI1_EQ_INT [7]
SDA_HDMI1_EQ_INT[7] HDMI_EQ_BOOST2 [7]
HDMI_EQ_BOOST1[7] DDC_EN_EQUALIZER [7]
SCL_HDMIOUT_MEZZCONN [10]
HPD_HDMI1_EQ_INT[7]
HPD_HDMIOUT_MEZZCONN[10]
CEC_HDMIOUT_MEZZCONN [6]
CEC_HDMI1_EQ_INT [7]
HDMIIN_DATA0+[8] HDMIIN_DATA0-[8]
HDMIIN_DATA1+[8] HDMIIN_DATA1-[8]
HDMIIN_DATA2-[8]
HDMIIN_DATA2+[8]
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
B TO B CONNECTORS AND AUDIO IN
10 11
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
B TO B CONNECTORS AND AUDIO IN
10 11
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
B TO B CONNECTORS AND AUDIO IN
10 11
Tuesday, March 02, 2010
0.02
B
B TO B CONNECTORS AND AUDIO IN
Mezzanine Card Connector
Power Connector
Control Signal Connector
S/P DIF CONNECTOR
Ground Post
+
-
CB7 47uF 20V
+
-
CB7 47uF 20V
CD50
0.1uF
10V CD50
0.1uF
10V
H16
2x10
H16
2x10
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
22 44 66 88
10 10 12 12
14 14
16 16 18 18
20 20
R55 0ER55 0E
L1 47uHL1 47uH
+
-
CB6 47uF 20V
+
-
CB6 47uF 20V
J4
0750030005
J4
0750030005
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13 13 14 14
15 15
16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24
25
25
26
26
27
27
R59 4.7KR59 4.7K
H17
2x5
H17
2x5
1
1
3
3
5
5
7
7
9
9
22 44 66 88
10 10
M1
TORX147PL(F,T)
M1
TORX147PL(F,T)
OUT 1
GND
2VCC 3
NC1
4
NC2
5
H14 1x1 H14 1x1
1
1

18
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 17. Board Accessories
5 5
4
4
3 3
2
2
1
1
DD C C B B A A
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
BOARD ACCESSORIES
11 11
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
BOARD ACCESSORIES
11 11
Tuesday, March 02, 2010
0.02
B
Title Size Document Number Rev
Date: Sheet of
GDA Technologies Ltd, L & T Infotech Park, Mount Poonamallee Road, Manapakkam, Ch 89
Tel: [phone] Fax: [phone] www.gdatech.com
B
Internal Version
GDA09CB004B
BOARD ACCESSORIES
11 11
Tuesday, March 02, 2010
0.02
B
BOARD ACCESSORIES
Fiducials Mounting Hole
Tooling Holes
Z1 165 mil Pad Size Z1 165 mil Pad Size
1
1
Z5 40mil Pad Z5 40mil Pad
1
1
Z4 40mil Pad Z4 40mil Pad
1
1
Z8 100mil Drill Size Z8 100mil Drill Size
1
1
Z7 100mil Drill Size Z7 100mil Drill Size
1
1
Z3 40mil Pad Z3 40mil Pad
1
1
Z6
40mil Pad
Z6
40mil Pad
1
1

19
HDMI Mezzanine Card – Revision B
User’s Guide
Appendix B. Hardware Variants
Early versions of the HDMI Mezzanine Card Revision B were produced with U3 (STMicroelectronics STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer) populated. On the current version of the HDMI Mezzanine
Card Revision B, U3 is not populated.
To receive HDMI/DVI input when U3 is unpopulated:
• Connect the HDMI/DVI source using J2.
• Install a shunt between pin 2 and pin 3 of header H13 to route J2 HDMI/DVI signals to the FPGA via the Mezza-
nine connector.
On the current version of the board, the following additional changes were made:
• To support the Extended Display Identification Data (EDID) via the I2C interface of the FPGA, two modification
wires are installed in the following locations on the new HDMI Mezzanine Card Revision B:
– R15 (pad nearest U3) to R12 (pad nearest U3)
– R14 (pad nearest U3) to R11 (pad nearest U3)
These wires bridge the I2C bus around vacant U3.
• The resistors R2, R3, R6 and R7 are not populated (to reduce I2C bus pull-up strength).
• The resistors R71 and R58 are not populated (to correct a pull-down contention).

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