Cypress Semiconductor STK22C48 User manual

STK22C48
16 Kbit (2K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-51000 Rev. ** Revised January 30, 2009
Features
■25 ns and 45 ns access times
■Hands off automatic STORE on power down with external 68
µF capacitor
■STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■RECALL to SRAM initiated by software or power up
■Unlimited Read, Write, and Recall cycles
■1,000,000 STORE cycles to QuantumTrap
■100 year data retention to QuantumTrap
■Single 5V+10% operation
■Commercial and industrial temperatures
■28-pin 300 mil and (330 mil) SOIC package
■RoHS compliance
Functional Description
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
fromthe nonvolatile memory.AhardwareSTOREisinitiatedwith
the HSB pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
STATIC RAM
ARRAY
32 X 512
Quantum Trap
32 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC V
CAP
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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STK22C48
Document Number: 001-51000 Rev. ** Page 2 of 14
Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions
Pin Name Alt IO Type Description
A0–A10 Input Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
DQ0-DQ7Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. WhenHIGH,deselectsthechip.
OE GInput Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS Ground Ground for the Device.The device is connected to ground of the system.
VCC Power Supply Power Supply Inputs to the Device.
HSB Input or Output HardwareStoreBusy(HSB).WhenLOW,thisoutputindicatesaHardwareStoreisinprogress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC No Connect No Connect. This pin is not connected to the die.
V
CAP
A
7
A
6
A
5
A
4
V
CC
HSB
WE
A
8
A
9
OE
A
10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
SS
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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STK22C48
Document Number: 001-51000 Rev. ** Page 3 of 14
Device Operation
The STK22C48 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
TheSTK22C48 performsa Read cyclewheneverCE and OEare
LOW while WE and HSB are HIGH. The address specified on
pins A0–10 determines the 2,048 data bytes accessed. When the
Read is initiated by an address transition, the outputs are valid
after a delay of tAA (Read cycle 1). If the Read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(Read cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for transi-
tions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSBis HIGH.Theaddressinputsmustbe stable priortoentering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ0–7 are written into the memory if it has valid tSD, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6V should be
In system power mode, both VCC and VCAP are connected to the
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the 10 ms
STORE cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one WRITE operation takes place since the most
recent STORE or RECALL cycle. An optional pull up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STOREon power loss is not required, then VCC
is tied to ground and +5V is applied to VCAP (Figure 3). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled.Ifthe STK22C48isoperatedin this configuration,refer-
ences to VCC are changed to VCAP throughout this data sheet.
In this mode, STOREoperations are triggered with the HSB pin.
It is not permissible to change between these three options “on
the fly”.
Figure 2. AutoStore Mode
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STK22C48
Document Number: 001-51000 Rev. ** Page 4 of 14
Figure 3. AutoStore Inhibit Mode
Hardware STORE (HSB) Operation
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK22C48 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a Write to the
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull up this pin with an external 10K
ohm resistor to VCAP if HSB is used as a driver.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK22C48 continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM Read operations take place. If a Write is
in progress when HSB is pulled LOW, it allows a time, tDELAY to
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Data Protection
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when VCC is
less than VSWITCH. If the STK22C48 is in a Write mode (both CE
and WE are low) at power up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during power
up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi-
tions. When VCAP<VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current whenitis cycledattimes longer
than 50 ns. Figure 4 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK22C48 depends on the
following items:
■The duty cycle of chip enable
■The overall cycle rate for accesses
■The ratio of Reads to Writes
■CMOS versus TTL input levels
■The operating temperature
■The VCC level
■IO loading
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STK22C48
Document Number: 001-51000 Rev. ** Page 5 of 14
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a VOH of at least 2.2V,
because it must overpower the internal pull down device. This
device drives HSB LOW for 20 ns at the onset of a STORE.
When the STK22C48 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on VCAP)
and VCC crosses VSWITCH on the way down, the STK22C48
attempts to pull HSB LOW. If HSB does not actually get below
VIL, the part stops trying to pull HSB LOW and abort the STORE
attempt.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sitessometimesreprogramthesevalues.FinalNVpatternsare
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume that an NV array is
in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E649 53 hex ormorerandom bytes) aspartof the finalsystem
manufacturing test to ensure these system routines work
consistently.
■Power up boot firmware routines should rewrite the nvSRAM
intothedesiredstate.Whilethe nvSRAMisshipped inapreset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■TheVCAPvaluespecifiedinthisdatasheetincludesaminimum
and a maximum value size. The best practice is to meet this
requirementandnotexceedthemaximumVCAPvaluebecause
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
VCAP value to make sure there is extra store charge should
discuss their VCAP size selection with Cypress.
Figure 4. Current Versus Cycle Time (Read)
Figure 5. Current Versus Cycle Time (Write)
Table 2. Hardware Mode Selection
CE WE HSB A10–A0 Mode IO Power
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active[1]
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z ICC2[2]
Notes
1. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE.
2. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode,
inhibiting all operations until HSB rises.
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STK22C48
Document Number: 001-51000 Rev. ** Page 6 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Temperature under bias.............................. –55°C to +125°C
Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to VCC + 0.5V
Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V
Power Dissipation .........................................................1.0W
DC Output Current (1 output at a time, 1s duration)....15 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V) [3]
Parameter Description Test Conditions Min Max Unit
ICC1 Average VCC Current tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
IOUT = 0 mA.
Commercial 85
65 mA mA
Industrial 90
65 mA mA
ICC2 Average VCC Current during
STORE All Inputs Do Not Care, VCC = Max Average current for duration tSTORE 3mA
ICC3 Average VCC Current at tRC=
200 ns, 5V, 25°C Typical WE > (VCC – 0.2V). All other inputs cycling. Dependent on output loading and cycle rate. Values
obtained without output loads.
10 mA
ICC4 Average VCAP Current during
AutoStore Cycle All Inputs Do Not Care, VCC = Max Average current for duration tSTORE 2mA
ISB1[4] Average Vcc Current
(Standby, Cycling TTL Input
Levels)
tRC = 25 ns, CE > VIH
tRC = 45 ns, CE > VIH Commercial 25
18 mA mA
Industrial 26
19 mA mA
ISB2[4] VCC Standby Current CE > (VCC – 0.2V). All others VIN <0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
1.5 mA
IILK Input Leakage Current VCC = Max, VSS < VIN <VCC -1 +1 μA
IOLK Off State Output Leakage
Current VCC = Max, VSS < VIN <VCC, CE or OE > VIH or WE < VIL -5 +5 μA
VIH Input HIGH Voltage 2.2 VCC +
0.5 V
VIL Input LOW Voltage VSS – 0.5 0.8 V
VOH Output HIGH Voltage IOUT = –4 mA except HSB 2.4 V
VOL Output LOW Voltage IOUT = 8 mA except HSB 0.4 V
VBL Logic ‘0’ Voltage on HSB Output IOUT = 3 mA 0.4 V
VCAP Storage Capacitor Between VCAP pin and Vss, 6V rated. 68 uF -10%, +20%
nom. 61 220 µF
Data Retention and Endurance
Parameter Description Min Unit
DATARData Retention 100 Years
NVCNonvolatile STORE Operations 1,000 K
Notes
3. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
4. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK22C48
Document Number: 001-51000 Rev. ** Page 7 of 14
Capacitance
In the following table, the capacitance parameters are listed.[5]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 0 to 3.0V 8pF
COUT Output Capacitance 7pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[5]
Parameter Description Test Conditions 28-SOIC
(300 mil) 28-SOIC (330 mil) Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal
impedance, per EIA / JESD51.
TBD TBD °C/W
ΘJC Thermal Resistance
(Junction to Case) TBD TBD °C/W
Figure 6. AC Test Loads
AC Test Conditions
5.0V
Output
30 pF
R1 963Ω
R2
512Ω
5.0V
Output
5 pF
R1 963
Ω
R2
512
Ω
For Tri-state Specs
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <5 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
5. These parameters are guaranteed by design and are not tested.
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STK22C48
Document Number: 001-51000 Rev. ** Page 8 of 14
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tACE tELQV Chip Enable Access Time 25 45 ns
tRC [6] tAVAV, tELEH Read Cycle Time 25 45 ns
tAA [7] tAVQV Address Access Time 25 45 ns
tDOE tGLQV Output Enable to Data Valid 10 20 ns
tOHA [7] tAXQX Output Hold After Address Change 5 5 ns
tLZCE [8] tELQX Chip Enable to Output Active 5 5 ns
tHZCE [8] tEHQZ Chip Disable to Output Inactive 10 15 ns
tLZOE [8] tGLQX Output Enable to Output Active 0 0 ns
tHZOE [8] tGHQZ Output Disable to Output Inactive 10 15 ns
tPU [5] tELICCH Chip Enable to Power Active 0 0 ns
tPD [5] tEHICCL Chip Disable to Power Standby 25 45 ns
Switching Waveforms Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7]
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6]
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Notes
6. WE and HSB must be High during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
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STK22C48
Document Number: 001-51000 Rev. ** Page 9 of 14
SRAM Write Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tWC tAVAV Write Cycle Time 25 45 ns
tPWE tWLWH, tWLEH Write Pulse Width 20 30 ns
tSCE tELWH, tELEH Chip Enable To End of Write 20 30 ns
tSD tDVWH, tDVEH Data Setup to End of Write 10 15 ns
tHD tWHDX, tEHDX Data Hold After End of Write 0 0 ns
tAW tAVWH, tAVEH Address Setup to End of Write 20 30 ns
tSA tAVWL, tAVEL Address Setup to Start of Write 0 0 ns
tHA tWHAX, tEHAX Address Hold After End of Write 0 0 ns
tHZWE [8,9] tWLQZ Write Enable to Output Disable 10 14 ns
tLZWE [8] tWHQX Output Active After End of Write 5 5 ns
Switching Waveforms Figure 9. SRAM Write Cycle 1: WE Controlled [10, 11]
Figure 10. SRAM Write Cycle 2: CE Controlled [10, 11]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT HIGH IMPEDANCE
DATA VALID
Notes
9. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
10.HSB must be high during SRAM Write cycles.
11. CE or WE must be greater than VIH during address transitions.
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STK22C48
Document Number: 001-51000 Rev. ** Page 10 of 14
AutoStore or Power Up RECALL
Parameter Alt Description STK22C48 Unit
Min Max
tHRECALL [12] tRESTORE Power up RECALL Duration 550 μs
tSTORE [14, 15] tHLHZ STORE Cycle Duration 10 ms
tDELAY [13] tHLQZ , tBLQZ Time Allowed to Complete SRAM Cycle 1 μs
VSWITCH Low Voltage Trigger Level 4.0 4.5 V
VRESET Low Voltage Reset Level 3.6 V
tVSBL[10] Low Voltage Trigger (VSWITCH) to HSB Low 300 ns
Switching Waveform Figure 11. AutoStore/Power Up RECALL
WE
Notes
12.tHRECALL starts from the time VCC rises above VSWITCH.
13.CE and OE low for output behavior.
14.CE and OE low and WE high for output behavior.
15.HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store
takes place.
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