Lattice Semiconductor LatticeMico8 User manual

LatticeMico8 Processor
Reference Manual
October 2014

ii LatticeMico8 Processor Reference Manual
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LatticeMico8 Processor Reference Manual iii
Type Conventions Used in This Document
Convention Meaning or Use
Bold Items in the user interface that you select or click. Text that you type
into the user interface.
<Italic> Variables in commands, code syntax, and path names.
Ctrl+L Press the two keys at the same time.
Courier Code examples. Messages, reports, and prompts from the software.
... Omitted material in a line of code.
.
.
.
Omitted lines in code and report examples.
[ ] Optional items in syntax descriptions. In bus specifications, the
brackets are required.
( ) Grouped items in syntax descriptions.
{ } Repeatable items in syntax descriptions.
|A choice between items in syntax descriptions.

iv LatticeMico8 Processor Reference Manual

LatticeMico8 Processor Reference Manual v
Contents
Introduction 1
Architecture 3
Register Architecture 3
General-Purpose Registers 3
Control and Status Registers 4
Memory Architecture 5
Memory Regions 5
Memory Modes 9
Interrupt Architecture 10
Call Stack 10
Configuration Options 11
Instruction Set 13
Instruction Formats 13
Instruction Set Lookup Table 14
Instruction Descriptions 16
Programming Model 37
Data Representation 37
Procedure Caller-Callee Convention 38
Register Usage 38
Stack Frame 39
Parameter Passing 40
Interrupt Convention 41
Acessing LatticeMico8 Memory Regions 42
Scratchpad 42
Peripheral 42
PROM 43

CONTENTS
vi LatticeMico8 Processor Reference Manual
Index 45

LatticeMico8 Processor Reference Manual 1
Chapter 1
Introduction
The LatticeMico8™ is an 8-bit microcontroller optimized for Field
Programmable Gate Arrays (FPGAs) and Programmable Logic Device
architectures from Lattice Semiconductor. It combines a full 18-bit wide
instruction set with 16 or 32 general-purpose registers. It is suitable for a wide
variety of markets, including communications, consumer, computer, medical,
industrial and automotive. The core consumes minimal device resources—
fewer than 250 Look-Up Tables (LUTs) in the smallest configuration—while
maintaining a broad feature set.
LatticeMico8 Features
8-Bit Data Path
18-Bit Instructions
Configurable Instruction Memory (PROM)
Internal, or external through the WISHBONE Interface
Configurable to accommodate 256, 512, 1K, 1.5K, 2K, 2.5K, 3K, 3.5K
or 4K instructions
Scratchpad Memory
Internal, or external through the WISHBONE Interface
Configurable up to 4Gbytes using paged bytes (256 bytes/page)
Input/Output Peripheral Space through the WISHBONE Interface
Configurable up to 4Gbytes using paged ports (256 ports/page)
Minimum Two Cycles per Instruction
Configurable 16 or 32 General-purpose Registers
Configurable Call Stack size
Figure 1 on page 2 shows the LatticeMico8 Microcontroller block diagram.

INTRODUCTION :
2LatticeMico8 Processor Reference Manual
Figure 1: LatticeMico8 Microcontroller Core

LatticeMico8 Processor Reference Manual 3
Chapter 2
Architecture
This chapter describes the LatticeMico8 register and memory architecture
and explains the interrupt architecture and call stack.
Register Architecture
This section describes the general-purpose and control and status registers of
the LatticeMico8 architecture.
General-Purpose Registers
The LatticeMico8 microcontroller can be configured to have either 16 or 32
general-purpose registers. Each register is 8 bits wide. The registers are
implemented using a dual-port distributed memory. The LatticeMico8 opcode
set permits the microcontroller to access 32 registers. When LatticeMico8 is
configured with 16 registers, any opcode reference to R16 to R31 maps to R0
to R15 respectively.
General-purpose registers R13, R14, and R15 can also be used by the
LatticeMico8 microcontroller as page-pointer registers, depending on the
current memory mode. Page pointers (PP) are used when the scratchpad and
peripheral memory spaces are larger than 256 bytes (see “Memory Modes”
on page 9). The memory address is formed by concatenating the values in
registers R13, R14, and R15 with an 8-bit value derived from the LatticeMico8
memory instruction. Table 1 on page 4 highlights the three LatticeMico8
memory modes and corresponding designation of registers R13, R14, and
R15.
In the large memory mode, registers R13, R14, and R15 indicate which of
the 16M pages is currently active. R13 provides the least-significant byte
of page address and R15 provides most-significant byte.

ARCHITECTURE :Register Architecture
4LatticeMico8 Processor Reference Manual
In the medium memory mode, register R13 indicates which of the 256
pages is currently active.
Control and Status Registers
Table 2 shows all the names of the control and status registers (CSR), the
read and write access, and the index used when the register is accessed. All
signal levels are active high.
IP – Interrupt Pending The IP CSR contains a pending bit for each of the 8
external interrupts. A pending bit is set when the corresponding interrupt
request line is asserted low. Bit 0 corresponds to interrupt 0. Bits in the IP
CSR can be cleared by writing a 1 with the wcsr instruction. Writing a 0 has no
effect. After reset, the value of the IP CSR is 0.
IM – Interrupt Mask The IM CSR contains an enable bit for each of the 8
external interrupts. Bit 0 corresponds to interrupt 0. In order for an interrupt to
be raised, both an enable bit in this register and the IE flag in the IE CSR must
be set to 1. After reset, the value of the IM CSR is 0.
IE – Global Interrupt Enable The IE CSR contains a single-bit (bit position
0) flag, IE, which determines whether interrupts are enabled. This flag has
priority over the IM CSR. After reset, the value of the IE CSR is 0.
Table 1: Designation of LatticeMico8 Registers Based on LatticeMico8 Memory Mode
Register Number
LatticeMico8 Memory Mode
Small Medium Large
0 through 12 general-purpose general-purpose general-purpose
13 general-purpose PP PP (LSB)
14 general-purpose general-purpose PP
15 general-purpose general-purpose PP (MSB)
16 through 31 general-purpose general-purpose general-purpose
Table 2: Control and Status Registers
Name Access Index Description
IP R/W 0 Interrupt Pending
IM R/W 1 Interrupt Mask
IE R/W 2 Global Interrupt Enable/Disable

ARCHITECTURE :Memory Architecture
LatticeMico8 Processor Reference Manual 5
Memory Architecture
This section describes the memory architecture of the LatticeMico8
microcontroller.
Memory Regions
The LatticeMico8 microcontroller recognizes three independent memory
regions. Each memory region has its own independent input/output interface
and its own instruction set support. These three memory regions are called
the PROM, the Scratchpad, and the Peripheral memory regions respectively.
The size and location of each of these memory regions is configurable as long
as all these three memory regions are located entirely within the 4GB address
space. These memory regions can also be configured to overlap within
LatticeMico System Builder. Figure 2 shows the three memory regions and
the address space to which they are confined by LatticeMico System Builder.
See “Acessing LatticeMico8 Memory Regions” on page 42 for details on how
to access each of the three memory regions from a software programmer's
perspective.
Figure 2: Memory Organization
Peripherals
PROM
Scratchpad
0xFFFFFFFF
0x80000000
0x00000000
Peripherals
PROM and
Scratchpad
Memory

ARCHITECTURE :Memory Architecture
6LatticeMico8 Processor Reference Manual
PROM Space
The PROM memory region contains the program code that will be executed
by the LatticeMico8 microcontroller core and is accessible via its instruction
fetch engine. The size of the PROM memory region can be configured to
accommodate 256, 512, 1024, 2048, or 4096 instruction opcodes. By default
the memory region is located within the LatticeMico8 microcontroller. The
memory regions can also be configured to be external to the LatticeMico8
microcontroller.
When the PROM memory region is internal to the microcontroller, it is
connected to the LatticeMico8 instruction fetch engine via a dedicated high-
speed bus that fetches one instruction opcode per clock cycle. There is no
instruction set support to write to internal PROM. When the PROM memory
region is external to the microcontroller, it is accessed by the master
WISHBONE interface within the LatticeMico8 instruction fetch engine. This
WISHBONE interface has a 8-bit data bus and it takes three 8-bit WISHBONE
accesses to fetch one LatticeMico8 instruction opcode. The instruction fetch
latency is now dictated by the system WISHBONE latency and the latency of
the PROM memory. The minimum instruction fetch latency is 12 clock cycles.
Table 3 shows the WISHBONE interface signals. For more information about
the WISHBONE System-On-Chip (SoC) Interconnection Architecture for
Portable IP Cores, as it is formally known, refer to the OPENCORES.ORG
Web site at www.opencores.org/projects.cgi/web/wishbone.
Table 3: PROM WISHBONE Interface Signals
Name Width Direction Description
I_CYC_O 1 Output A new LatticeMico8 instruction fetch request is initiated by asserting this
signal. This signal remains asserted until I_ACK_I is asserted, which
indicates the completion of the request.
I_STB_O 1 Output A new LatticeMico8 instruction fetch request is initiated by asserting this
signal. This signal may be valid only for the first cycle.
I_CTI_O 2 Output Always has a value 2’b00
I_BTE_O 3 Output Always has a value 3’b000
I_ADR_O 32 Output The address output array I_ADR_O( ) is used to pass a binary address.
I_WE_O 1 Output Always has a value 1’b0
I_SEL_O 4 Output Always has a value 4’b1111
I_DAT_O 8 Output Unused
I_LOCK_O 1 Output Unused (signal exists, but it is not implemented)
I_ACK_I 1 Input When asserted, the signal indicates the normal termination of a bus cycle
and that an instruction is available on I_DAT_I bus.
I_ERR_I 1 Input Unused (signal exists, but it is not implemented)
I_RTY_I 1 Input Unused (signal exists, but it is not implemented)
I_DAT_I 8 Input One byte of the LatticeMico8 18-bit instruction opcode is available on this
bus when I_ACK_I is asserted. It takes three WISHBONE transactions to
complete one LatticeMico8 instruction fetch.

ARCHITECTURE :Memory Architecture
LatticeMico8 Processor Reference Manual 7
The advantage of configuring the PROM memory region as external to the
LatticeMico8 microcontroller is that the PROM memory region can now be
configured to overlap with other LatticeMico8 memory regions within Lattice
Mico System Builder and, therefore, be directly written to by LatticeMico8
opcodes. This configuration also offers the ability to store and execute
LatticeMico8 instructions from non-volatile memory such as Flash. As shown
in Figure 2 on page 5, the external PROM memory region can be placed at
any location within a 4GB address range. When the LatticeMico8
microcontroller is instantiated using Lattice Mico System Builder, it will restrict
the placement of external PROM between 0x00000000 and 0x80000000.
Scratchpad Space
LatticeMico8 provides an independent memory space that is designed to be
used for program read/write and read-only data as well as other user-defined
data. The size of this scratchpad memory can be configured from 32 bytes to
4G bytes, in power-of-two increments. Figure 3 shows the structure of this
scratchpad space and how data is located within this space. The scratchpad
memory space can be placed at any location within a 4GB address range.
The first 4 bytes are reserved for LatticeMico8 interrupt handling. Program
data is situated above this reserved space. The designer can configure the
size of scratchpad memory that is used for program data. User-defined data is
optional and is always located after program data.
The scratchpad memory can be configured to be entirely internal to the
LatticeMico8 microcontroller, entirely external to LatticeMico8 microcontroller,
or a combination of both.
The internal scratchpad is implemented using single-port EBRs and is
hooked up to the LatticeMico8 core through a dedicated bus. Reads or
writes to the internal scratchpad take a single clock cycle.
The external scratchpad is accessed through the Peripheral WISHONE
interface of the LatticeMico8 microcontroller (see “Interrupt Architecture”
on page 10). Each read or write will take a minimum of 2 clock cycles.
Figure 3: Scratchpad Space Structure

ARCHITECTURE :Memory Architecture
8LatticeMico8 Processor Reference Manual
Peripheral (Input/Output) Space
LatticeMico8 provides an independent memory space that is designed to be
used for peripherals and other memory-mapped hardware. The size of this
peripheral memory space can be configured from 0 bytes to 4G bytes in
power-of-two increments. While the peripheral memory space can be placed
at any location within a 4GB address range, Lattice Mico System Builder
restricts the peripheral memory space to the addresses between 0x80000000
and 0xFFFFFFFF.
This memory space is always external to the LatticeMico8 microcontroller and
is primarily used to enable LatticeMico8 to communicate with memory-
mapped hardware and peripherals. The LatticeMico8 microcontroller can
communicate with any hardware or peripheral within the peripheral memory
space, through the peripheral WISHBONE interface within LatticeMico8 core,
using LatticeMico8 instruction opcodes. This WISHBONE interface has 8-bit
input and output data busses and a 32-bit address bus. Table 4 shows the
Peripheral WISHBONE interface signals.
Table 4: Peripheral WISHBONE Interface Signals
Name Width Direction Description
D_CYC_O 1 Output A new LatticeMico8 data request is initiated by asserting this signal.
This signal remains asserted until D_ACK_I is asserted, which
indicates completion of the request.
D_STB_O 1 Output A new LatticeMico8 data request is initiated by asserting this signal.
This signal may be valid only for first cycle.
D_CTI_O 2 Output This bus will always have a value 2'b00
D_BTE_O 3 Output This bus will always have a value 3'b000
D_ADR_O 32 Output The address output array D_ADR_O( ) is used to pass a binary
address. D_ADR_O( ) actually has a full 32 bits.
D_WE_O 1 Output This signal indicates whether a new data request is a read (0) or a
write (1). This signal must hold its value as long as D_CYC_O is
asserted.
D_SEL_O 1 Output Always has a value 1'b1
D_DAT_O 8 Output Has valid data when D_WE_O is 1'b1.
D_LOCK_O 1 Output Unused (signal exists, but it is not implemented)
D_ACK_I 1 Input When asserted, the signal indicates the normal termination of a bus
cycle.
D_ERR_I 1 Input Unused (signal exists, but it is not implemented)
D_RTY_I 1 Input Unused (signal exists, but it is not implemented)
D_DAT_I 8 Input Data is available on this bus when D_ACK_I and D_WEO are
asserted.

ARCHITECTURE :Memory Architecture
LatticeMico8 Processor Reference Manual 9
Memory Modes
The LatticeMico8 microcontroller can be configured for different sizes for the
scratchpad and peripheral memory regions. The size of scratchpad and
peripheral memory regions can be as small as 32 bytes and as large as 4G
bytes. A 32-byte memory region requires only 5 address bits, while a 4GB
memory region requires 32 address bits.
The LatticeMico8 instruction set can directly access only 256 memory
locations, since all general-purpose registers are 8 bits wide. (See “Instruction
Set” on page 13.) To access memory regions that are larger than 256 bytes,
LatticeMico8 relies on a concept called “paging,” in which the memory is
logically divided into 256-byte pages. The memory address is composed of
two parts, as shown in Figure 4: the page index and the page pointer. The
page index is 8 bits wide and addresses a byte in the currently active page,
while the page pointer provides the address of the currently active page.
The page pointers are essentially general-purpose registers that have been
retargeted to provide a memory address. (See “Memory Regions” on page 5.)
Table 5 shows the memory modes of the LatticeMico8 microcontroller, the
size of addressable memory space in each mode, and the general-purpose
registers used as page pointers.
Figure 4: Memory Modes
Table 5: LatticeMico8 Memory Modes
Memory Mode Maximum Memory Size Address Bits Page Pointer Registers
Small 256 bytes 8 N/A
Medium 16K bytes 16 R13
Large 4G bytes 32 R13, R14, R15

ARCHITECTURE :Interrupt Architecture
10 LatticeMico8 Processor Reference Manual
Interrupt Architecture
The LatticeMico8 microcontroller supports up to 8 maskable, active-low, level-
sensitive interrupts. Each interrupt line has a corresponding mask bit in the IM
CSR. The mask enable is active high. A global interrupt-enable flag is
implemented in the IE CSR. The software can query the status of the
interrupts and acknowledge them through the IP CSR. If more interrupt
sources or more sophisticated interrupt detection methods are required,
external interrupt controllers can be cascaded onto the microcontroller’s
interrupt pins to provide the needed functionality.
When an interrupt is received, the address of the next instruction is pushed
into the call stack (see “Call Stack” on page 10), and the microcontroller
continues execution from the interrupt vector (address 0). The flags (carry and
zero) are pushed onto the call stack along with the return address. An iret
instruction will pop the call stack and transfer control to the address on top of
the stack. The flags (carry and zero) are also popped from the call stack.
See “Interrupt Convention” on page 41 for details on the programming model
for interrupts.
Call Stack
The LatticeMico8 microcontroller implements a hardware call stack to handle
procedure calls (call instruction) and procedure/interrupt return (ret and iret
instructions). The depth of this call stack determines the number of nested
procedure calls that can be handled by the LatticeMico8 microcontroller, and
designers can choose the depth to be 8, 16, or 32. When a call instruction is
executed, the address of the next instruction is pushed on to the call stack. A
ret or iret instruction will pop the stack and continue execution from the
location at the top of the stack.
Note
The LatticeMico8 microcontroller does not support nested interrupts. Locations 0
through 3 in the scratchpad are reserved for interrupt handling and should not used for
any other purpose.
Note
There is no mechanism in hardware to detect whether the number of nested procedure
calls has exceeded the depth of the call stack. It is up to the software developer to
ensure that the call stack does not overflow.

LatticeMico8 Processor Reference Manual 11
Chapter 3
Configuration Options
The LatticeMico8 microcontroller is reconfigurable. Table 6 outlines the
various configuration options that are available to a designer.
Table 6: LatticeMico8 Configuration Options
Parameter Name Description
LATTICE_FAMILY The target Lattice FPGA family.
CFG_PROM_INIT_FILE Provides the file that contains the initialization data (program code) for an
internal PROM.
CFG_PROM_INIT_FILE_FORMAT Indicates whether CFG_PROM_INIT_FILE is in hex (default) or binary.
CFG_PROM_SIZE Indicates the number of instructions that can be accommodated in the
PROM.
CFG_SP_INIT_FILE Provides the file that contains the initialization data (program data) for an
internal scratchpad.
CFG_SP_INIT_FILE_FORMAT Indicates whether CFG_SP_INIT_FILE_FORMAT is hex (default) or binary.
SP_PORT_ENABLE Indicates whether the scratchpad is internal (value 1) or external (value 0).
The default is 1.
SP_SIZE Indicates the number of bytes in the scratchpad.
SP_BASE_ADDRESS Provides the base address of the scratchpad, regardless of whether it is
internal or external.
CFG_IO_BASE_ADDRESS Provides the base address of the peripheral memory region.
CFG_EXT_SIZE_[8|16|32] Indicates the size of address bus for the scratchpad and peripheral memory
regions and, therefore, identifies the LatticeMico8 memory mode. The
default is 16 (medium memory mode).
CFG_REGISTER_[16|32] Indicates the number of general-purpose registers in LatticeMico8. The
default is 8.

CONFIGURATION OPTIONS :
12 LatticeMico8 Processor Reference Manual
CFG_EBR Indicates whether the internal storage files are using EBR (value 1) or
Distributed RAM (value 0). The default is 0.
CFG_CALL_STACK_[8|16|32] Indicates the depth of the call stack. The default is 16.
CFG_ROM_EN Indicates whether the PROM and Scratchpad memories need to be
initialized from non-volatile storage such as flash at power-up. The default
is 0, i.e., no copying is required.
CFG_ROM_BASE_ADDRESS Provides the base address of the memory which contains the PROM and
Scratchpad images. The PROM image starts at this base address. The
Scratchpad image starts at location (CFG_PROM_SIZE*3).
CFG_XIP Indicates whether the PROM memory is the same as the non-volatile
storage that contains the PROM image. The default is 0, i.e., both
memories are different. 1 indicates that both memories are the same (i.e.,
no copying needs to be done) and the PROM is external to LatticeMico8.
INTERRUPTS Indicates the number of external interrupts. The default is 8.
Table 6: LatticeMico8 Configuration Options (Continued)
Parameter Name Description

LatticeMico8 Processor Reference Manual 13
Chapter 4
Instruction Set
This chapter includes descriptions of all the instruction opcodes of the
LatticeMico8 microcontroller.
Instruction Formats
All LatticeMico8 instructions are 18 bits wide. They are in three basic formats,
as shown in Figure 5, Figure 6, and Figure 7.
Figure 5: Register-Register Format
Figure 6: Register-Immediate Format
Figure 7: Immediate Format

INSTRUCTION SET :Instruction Set Lookup Table
14 LatticeMico8 Processor Reference Manual
Instruction Set Lookup Table
Table 7: Instruction Set Reference Card
Operation Action Flags
ADD Rd, Rb Rd = Rd + Rb Carry, Zero
ADDC Rd, Rb Rd = Rd + Rb + Carry Carry, Zero
ADDI Rd, C Rd = Rd + C Carry, Zero
ADDIC Rd, C Rd = Rd + C + Carry Carry, Zero
AND Rd, Rb Rd = Rd & Rb Zero
ANDI Rd, C Rd = Rd & C Zero
B Label PC = PC + Label
BC Label If Carry = 1, PC = PC + Label
BNC Label If Carry = 0, PC = PC + Label
BNZ Label If Zero = 0, PC = PC + Label
BZ Label If Zero = 1, PC = PC + Label
CALL Label Stack = PC + 1, PC = PC + Label
CALLC Label If Carry = 1, Stack = PC + 1, PC = PC + Label
CALLNC Label If Carry = 0, Stack = PC + 1, PC = PC + Label
CALLNZ Label If Zero = 0, Stack = PC + 1, PC = PC + Label
CALLZ Label If Zero = 1, Stack = PC + 1, PC = PC + Label
CLRC Carry = 0 Carry
CLRI IE = 0
CLRZ Zero = 0 Zero
CMP Rd, Rb Rd – Rb Carry, Zero
CMPI Rd, C Rd – C Carry, Zero
EXPORT Rd, Port# Peripheral (Port #) = Rd
EXPORTI Rd, Rb Peripheral (Page Pointer, Rb) = Rd
IMPORT Rd, Port# Rd = Peripheral (Port #)
IMPORTI Rd, Rb Rd = Peripheral (Page Pointer, Rb)
IRET PC, Carry, Zero = Stack Carry, Zero
LSP RD, SS Rd = Scratchpad (SS)
LSPI Rd, Rb Rd = Scratchpad (Page Pointer, Rb)
MOV Rd, Rb Rd = Rb
MOVI Rd, C Rd = Const