Lauterbach TRACE32-ICD User manual

MANUAL
Release 02.2022
PPC600 Family Debugger

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PPC600 Family Debugger
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ...................................................................................................................... 
ICD In-Circuit Debugger ................................................................................................................ 
Processor Architecture Manuals .............................................................................................. 
PQII, MPC5200, MPC603/7xx, MPC74xx ................................................................................ 
PPC600 Family Debugger .................................................................................................... 1
Introduction ....................................................................................................................... 6
Brief Overview of Documents for New Users 6
Warning .............................................................................................................................. 7
Signal Level 7
ESD Protection 7
Target Design Requirement/Recommendations ............................................................ 8
General 8
Quick Start ......................................................................................................................... 9
Troubleshooting ................................................................................................................ 11
Problems with Memory Access 12
FAQ ..................................................................................................................................... 12
Configuration ..................................................................................................................... 13
System Overview 13
PowerPC 600 Family Specific Implementations ............................................................. 14
Breakpoints 14
Software Breakpoints 14
Software Breakpoint Handling 15
On-chip Breakpoints 17
Software Breakpoints in Interrupt Handlers 18
Breakpoints in FLASH/ROM 18
Breakpoints on Physical or Virtual Addresses 18
Examples for Breakpoints 19
Software Breakpoints 19
On-chip Program Address Breakpoints 19
On-chip Data Address Breakpoints 19
Access Classes 20
Access Classes to Memory and Memory Mapped Resources 20

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Access Classes to Other Addressable Core and Peripheral Resources 21
Cache 21
Memory Coherency 21
MESI States 22
Little Endian Operation 23
CPU specific SYStem Commands ...................................................................................24
SYStem.BdmClock Set JTAG frequency 24
SYStem.CPU Select the CPU type 24
SYStem.LOCK Lock and tristate the debug port 25
SYStem.MemAccess Real-time memory access (non-intrusive) 25
SYStem.Mode Select operation mode 26
SYStem.CONFIG.state Display target configuration 27
SYStem.CONFIG Configure debugger according to target topology 28
Daisy-Chain Example 31
TapStates 32
SYStem.CONFIG.CHKSTPIN Control pin 8 of debug connector 32
SYStem.CONFIG.CORE Assign core to TRACE32 instance 33
SYStem.CONFIG.DriverStrength Configure driver strength of TCK pin 34
SYStem.CONFIG.QACK Control QACK pin 34
CPU specific System Commands .................................................................................... 35
SYStem.Option.BASE Set base address for on-chip peripherals 35
SYStem.Option.BUS32 Use 32-Bit data-bus mode 36
SYStem.Option.CONFIG Select RCW configuration 36
SYStem.Option.DCREAD Read from data cache 37
SYStem.Option.DUALPORT Implicitly use run-time memory access 37
SYStem.Option.FREEZE Freeze timebase when core halted 38
SYStem.Option.HoldReset Set reset hold time 39
SYStem.Option.HOOK Compare PC to hook address 39
SYStem.Option.HRCWOVerRide Override HRCW on SYStem.Up 40
SYStem.Option.ICFLUSH Invalidate instruction cache before go/step 40
SYStem.Option.ICREAD Read from instruction cache 41
SYStem.Option.IMASKASM Disable interrupts while single stepping 41
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 41
SYStem.Option.IP Set MSR_IP value for breakpoints / SYStem.Up 42
SYStem.Option.LittleEnd True little endian mode 42
SYStem.Option.MemProtect Enable memory access safeguard 42
SYStem.Option.MemSpeed Configure memory access timing 43
SYStem.Option.MMUSPACES Separate address spaces by space IDs 43
SYStem.Option.NoDebugStop Disable JTAG stop on debug events 44
SYStem.Option.NOTRAP Use alternative software breakpoint instruction 45
SYStem.Option.OVERLAY Enable overlay support 46
SYStem.Option.PARITY Generate parity on memory access 46
SYStem.Option.PINTDebug Program interrupt debugging 47

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SYStem.Option.PPCLittleEnd PPC little endian mode 47
SYStem.Option.PTE Evaluate PTE table for address translation 48
SYStem.Option.RESetBehavior Set behavior when target reset detected 48
SYStem.Option.ResetMode Select reset mode for SYStem.Up 49
SYStem.Option.SLOWRESET Relaxed reset timing 49
SYStem.Option.STEPSOFT Use alternative method for ASM single step 50
SYStem.Option.WaitReset Set reset wait time 51
SYStem.Option.WATCHDOG Leave software watchdog enabled 52
CPU specific MMU Commands ........................................................................................ 53
MMU.DUMP Page wise display of MMU translation table 53
MMU.List Compact display of MMU translation table 55
MMU.SCAN Load MMU table from CPU 57
MMU.Set Write MMU TLB entries to CPU 58
CPU specific BenchMarkCounter Commands ................................................................ 59
BMC.<counter>.FREEZE Freeze counter in certain core states 59
BMC.FREEZE Freeze counters while core halted 60
CPU specific TrOnchip Commands .................................................................................61
TrOnchip.DISable Disable debug register control 61
TrOnchip.ENable Enable debug register control 61
TrOnchip.CONVert Adjust range breakpoint in on-chip resource 61
TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource 62
TrOnchip.RESet Reset on-chip trigger settings 62
TrOnchip.state Display on-chip trigger window 62
TrOnchip.TEnable Set filter for the trace 62
TrOnchip.TOFF Switch the sampling to the trace to OFF 63
TrOnchip.TON Switch the sampling to the trace to “ON” 63
TrOnchip.TTrigger Set a trigger for the trace 63
Mechanical Description .................................................................................................... 64
JTAG/COP Connector PPC603e/700/MPC8200 64
Technical Data ................................................................................................................... 65

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PPC600 Family Debugger
Version 09-Mar-2022

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©1989-2022 Lauterbach
Introduction
This document describes the processor specific settings and features of TRACE32-ICD for the following
CPU families:
• MPC603x
• MPC51xx, MPC5200, MPC5200B
• MPC7xx, MPC74xx
• MPC82xx, MPC83xx
•MPC86xx
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
If some of the described functions, options, signals or connections in this Processor Architecture Manual are
only valid for a single CPU or for specific families, the name(s) of the family(ies) is added in brackets.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Training - Debugger Basics” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.

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Warning
Signal Level
ESD Protection
All The debugger drives the output pins of the BDM/JTAG/COP connector with the
same level as detected on the VCCS pin. If the I/O pins of the processor are 3.3 V
compatible then the VCCS should be connected to 3.3 V.
See also System.up errors.
Supported debug voltage:
Debug cable with blue ribbon cable 2.5 … 5.0 V.
Debug cable with gray ribbon cable 1.8 … 5.0 V (Available since 03/2004).
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.

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Target Design Requirement/Recommendations
General
• Locate the JTAG / COP connector as close as possible to the processor to minimize the
capacitive influence of the trace length and cross coupling of noise onto the JTAG signals. Don’t
put any capacitors (or RC combinations) on the JTAG lines.
• Connect TDI, TDO, TMS and TCK directly to the CPU. Buffers on the JTAG lines will add delays
and will reduce the maximum possible JTAG frequency. If you need to use buffers, select ones
with little delay. Most CPUs will support JTAG above 50 MHz, and you might want to use high
frequencies for optimized download and upload performance.
• Ensure that JTAG HRESET is connected directly to the HRESET of the processor. This will
provide the ability for the debugger to drive and sense the status of HRESET
. The target design
should only drive HRESET with open collector/open drain.
• For optimal operation, the debugger should be able to reset the target board completely
(processor external peripherals, e.g. memory controllers) with HRESET
.
• In order to start debugging right from reset, the debugger must be able to control CPU HRESET
and CPU TRST independently. There are board design recommendations to tie CPU TRST to
CPU HRESET, but this recommendation is not suitable for JTAG debuggers.
• If the processor does not have QACK/QREQ pins, leave the corresponding pins on the debug
connector N/C.
• If the processor has QACK/QREQ pins, QACK must be LOW in order to halt the core for
debugging. If QACK is connected to the debug connector, the debugger can drive it LOW by
command. If QACK is not connected to any system controller, it is recommended to tie it to GND.
• The debug cable uses VCCS on the JTAG-VREF pin to generate the power supply for the JTAG
output buffers. The load on the JTAG-VREF pin caused by the debug cable depends on the
debug cable version:
Gray ribbon
cable
The VCCS pin is used as reference voltage for the internal power supply
in the debug cable. This causes a load of about 50 k. It is
recommended to use a resistor with max. 5 kto VCC, and max 1 kfor
systems with VCCS = 1. 8V
Blue ribbon
cable
The VCCS pin should be connected to VCC through a resistor with max.
10 , as the output buffers are directly supplied by the VCCS pin.

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Quick Start
Starting up the Debugger is done as follows:
1. Select the device prompt B: for the ICD Debugger, if the device prompt is not active after the
TRACE32 software was started.
2. Select the CPU type to load the CPU specific settings.
3. Tell the debugger where’s FLASH/ROM on the target.
This command is necessary for the use of on-chip breakpoints.
4. Enter debug mode.
This command resets the CPU (HRESET) and enters debug mode. After this command is executed,
it is possible to access the registers.
5. Show registers of on-chip peripherals.
6. Set the chip selects to get access to the target memory.
7. Load the program and debug symbols.
8. If the program was compiled on a different computer / environment, the source file path might
have to be adopted.
B:
SYStem.CPU MPC8323
MAP.BOnchip 0xFF000000++0xFFFFFFFF
SYStem.Up
PER.view
Data.Set ANC:(IOBASE()|0x00010100) %Long 0xFF801801
Data.Set ANC:(IOBASE()|0x00010104) %Long 0xFF800EF4
;.....
Data.LOAD.Elf diabc.x
Data.LOAD.Elf diabc.x /StripPART 5. /SOURCEPATH "L:\prj\src"

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The option of the Data.LOAD command depends on the file format generated by the compiler. A
detailed description of the Data.LOAD command is given in the “General Commands Reference”.
9. Set a breakpoint to the function to be debugged.
10. Start application. The core will halt when the breakpoint is reached.
11. Open windows to show source code, core registers and local variables. The window position can
be specified with the WinPOS command.
Break.Set main
Go
Data.List
Register.view /SpotLight
Frame.view /Locals /Caller

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Troubleshooting
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
Error Message Reason
target power fail Target has no power or debug cable is not connected. Check if the
JTAG VCC pin is driven by the target.
debugger configuration
error
The debugger was not able to determine the connected processor.
There are two possible reasons for this error: The CPU you are using
is not supported by the used software, or a communication error pre-
vented a correct determination. Check the AREA window for more
information.
target processor in reset The reset line is/was asserted by the target while the debugger per-
formed a power-on reset. Try SYStem.Option.SLOWRESET, and
check signal level of the JTAG HRESET pin.
emulation debug port fail The debugger was unable to perform a power-on reset with the pro-
cessor. Check all JTAG port signals.
emulation debug port fail
target reset fail
emulator debug port reset
error
If the target reset is asserted for >500ms, or the target reset state is
not reflected on the JTAG_HReset pin, SYStem.Option.SLOWRESET
might be necessary.

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Problems with Memory Access
For processors of some device families (esp. MPC82XX/MPC83XX), it is important that no unimplemented
memory addresses are accessed by the debugger. Unimplemented memory means address ranges which
would cause a data access exception when accessed by the target application in the current target state.
Memory that is only available after target initialization, like SDRAM is unimplemented memory until initialized
(e.g. a Data.dump window (or the stack view in the Register window) to SDRAM directly after reset). Also,
virtual addresses are unimplemented if the memory management unit is currently disabled or the address
unmapped (e.g. a Data.List window to Linux code at 0xC0000000 directly after reset).
The effects of accessing unimplemented memory are temporarily flickering memory windows up to
permanently hanging memory buses, which can only be recovered by a reset. The debugger can rarely
detect if a memory bus is hanging or not. Typical values displayed in dump/list windows are 0x00000000,
0xDEADBEE0, 0xDEADBEE1 or “????????” (bus error).
Hints for safe memory accesses:
• directly after reset, set R1 to zero before opening the register window (which includes the stack
view)
• directly after reset, close all windows that display data from SDRAM etc. which is not accessible
directly after reset
• MPC82XX: close the peripheral view window before SYStem.UP. Usually the IMMR base
address is different after reset and after target initialization. Always set the right base address
with SYStem.Option.BASE before opening the peripheral view.
• Protect the debugger from accessing unimplemented memory using MAP.DENYACCESS.
FAQ
Please refer to our Frequently Asked Questions page on the Lauterbach website.

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Configuration
System Overview
POWER DEBUG PRO

POWER DEBUG PRO
SWITCH PC or
Workstation
1 GBit Ethernet
Ethernet
Cable
Target
Debug
Connector
Debug Cable

POWER DEBUG USB INTERFACE / USB 3
POWER DEBUG INTERFACE / USB 3
PC or
Workstation
USB
Cable
Target
Debug
Connector
Debug Cable

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PowerPC 600 Family Specific Implementations
Breakpoints
There are two types of breakpoints available: Software breakpoints (SW-BP) and on-chip breakpoints.
Software Breakpoints
Software breakpoints are the default breakpoints. They can only be used in RAM areas. There is no
restriction in the number of software breakpoints. Please consider that setting a large number of software
breakpoints will reduce the debug speed.
For software breakpoint functionality, the debugger must set an on-chip breakpoint to the program interrupt
address. In some applications, especially during the target initialization stage, some applications have
interrupts disabled and use the interrupt address range for non-interrupt code. In this situation, there are two
possible workarounds:
• Configure CPU and debugger to use the interrupt addresses that are not used at this stage. This
can be done by setting MSR_IP. Please note that the target application can modify this value any
time.
• Force on-chip breakpoints to a different address until target initialization is finished. E.g. set the
on-chip breakpoint to the address where the code at the interrupt addresses is not executed
anymore. If this point is reached, clear the on-chip breakpoint and continue debugging. If the
used CPU has more than one on-chip breakpoint, set the second breakpoint to an unused
address
All Since this CPU can only be stopped by an on-chip breakpoint,
TRACE32-ICD sets an on-chip breakpoint to the Trap exception
handler, whenever a software breakpoint is used. Because of that,
software breakpoints can not be used if all on-chip breakpoints are
directly used.
MPC60X, MPC7XX,
MPC824X/6X, MPC74XX,
MPC5100, MPC86XX
The current exception position must be known by the debugger at
that time the SW-BP take place. See also SYStem.Option.IP.
MPC512X,
MPC5200,MPC8280,
MPC827X,MPC8247,
MPC8248, MPX83XX
CPUs with at least two on-chip breakpoints can use
SYStem.Option.IP BOTH. The debugger will set on-chip
breakpoints to both interrupt addresses.

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Software Breakpoint Handling
For software breakpoint functionality, the debugger must set an on-chip breakpoint to the program interrupt
address. As PPC603-based cores have two possible interrupt addresses based on MSR[IP].
In situations where there are less than two on-chip breakpoints available there is a resource conflict. The
unavailability can be caused by CPU design, or if the user makes direct use of on-chip breakpoints.
If the source code modifies MSR[IP], then a manual correction is necessary to use the correct exception
handler.
Following some logic structure examples to explain this special situations.
Source code structure for all modes:
AUTO-Mode:
Manual-Mode 0/1
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
…
code
code
1. SW-BP
code
code
code change MSR[IP] bit to 0
code
2. SW-BP
code
…
Command Sequence / CPU Status MSR[IP] Exception Pos Comment
CPU is stopped, PC at 0x00
go
CPU stop at 0x08
go
CPU is still running
1
1
1
1/0
0
1
1
1
1
1
Break OK.
Break error!
Command Sequence / CPU Status MSR[IP] Exception Pos Comment
CPU is stopped, PC at 0x00
go
CPU stop at 0x08
set sys.option.ip 0
go
CPU stop at 0x1C
1
1
1
1
1/0
0
1
1
1
0
0
0
Break OK.
Break OK.

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Conclusion:
This means, if you know, that your source code will change the MSR[IP] bit and your first SW-BP will take
affect after this alteration, so use the SYStem.Option.IP to select the right exception handler.
NOTE: If the target application uses page tables, software breakpoints can only be set to page tables which
are already available. If it is necessary to set breakpoints in pages not yet mapped, only on-chip breakpoints
can be used.
Software breakpoints can be overwritten by the target application, e.g. if a breakpoint is set in an area which
will be loaded by a boot loader. Use on-chip breakpoints in this case.

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On-chip Breakpoints
The following list gives an overview of the usage of the on-chip breakpoints by TRACE32-ICD:
•CPUfamily
•Instruction breakpoints: Number of on-chip breakpoints that can be used for program and spot
breakpoints
•Read/Write breakpoints: Number of on-chip breakpoints that can be used as read or write
breakpoints. Can be only set on 8 byte boundaries
•Data breakpoints: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
NOTE: On-chip breakpoints can be cleared by the target application or by a target reset. If an on-chip
breakpoint is not hit, first check (with the peripheral view), if the on-chip breakpoint is set or not.
CPU Family Instruction
Breakpoints
Read/Write
Breakpoints
Data Value
Breakpoints
Notes
PPC603
RHPPC
MPC8240
MPC8245
MPC8255
MPC8260
MPC8265
MPC8266
1 single
address
— — Instruction
breakpoint is not
available if software
breakpoints are used
MGT5100
PPC7XX
MPC74XX
MPC86XX
1 single
address
1 single
address
— Instruction
breakpoint is not
available if software
breakpoints are used
MPC512X
MPC5200
MPC8247
MPC8248
MPC8270
MPC8275
MPC8280
MPC83XX
2 single
addresses
or
1 range
2 single
addresses
or
1 range
If software
breakpoints are
used, instruction
breakpoints are
reduced to one
single address

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Software Breakpoints in Interrupt Handlers
If software breakpoints are used in interrupt handlers, the registers SRR0 and SRR1 will be overwritten,
because software breakpoints also use SRR0/1. There are several ways to debug interrupt handlers without
corrupting SRR0/1:
• If MPC82XX, MPC5200 or RHPPC (G2_LE cores) is under debug, set SYStem.Option.NOTRAP
ILL.
• Use on-chip breakpoints. On-chip breakpoints will not corrupt SRR0/1. Please note that if only a
single on-chip instruction address breakpoint is available, using the on-chip breakpoint will
prevent using any further software breakpoints.
• Patch the interrupt handler, so that SRR0/1 are saved upon interrupt entry and restored before
interrupt exit. If the interrupt handler it patched that way, it is safe to use software breakpoints
after SRR0/1 have been saved.
Breakpoints in FLASH/ROM
If an instruction breakpoint is set, per default, the debugger tried to set a software breakpoint. If writing to the
breakpoint address failed, the debugger will set an on-chip breakpoint.
With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH, EPROM) on the target. If a breakpoint is set within the specified address range, the debugger uses
automatically the available on-chip breakpoints. Use this command, if write accesses to a read-only memory
space are forbidden, e.g. because it could cause a reset etc.
Example:
Breakpoints on Physical or Virtual Addresses
On-chip breakpoints of almost all PPC603 based processors have a TE bit to configure if the breakpoint
matches, if the access was performed on physical addresses (MSR_IR / MSR_DR off) of on virtual
addresses (MSR_IR / MSR_DR on). In order to match, the processor compares IABR_TE / DABR_TE with
MSR_IR for instruction and with MSR_DR for data accesses.
Per default, the debugger configures the breakpoints to match on physical addresses. In order to set the on-
chip breakpoints to virtual addresses, use the command TRANSlation.ON (Activate MMU translation).
This command will enable MMU support, including breakpoint configuration.
Software breakpoints hit on virtual addresses if MSR_IR is set, and on physical addresses if MSR_IR is not
set, regardless of any other configuration.
MAP.BOnchip 0xFF800000--0xFFFFFFFF

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Examples for Breakpoints
Software Breakpoints
Software breakpoints on ranges not possible.
On-chip Program Address Breakpoints
NOTE: Address ranges are only possible with CPUs that have at least two on-chip program address
breakpoints. The option /program is optional.
On-chip Data Address Breakpoints
Data address breakpoints of all PPC603e based cores will operate on 8 byte boundaries.
Break.Set 0x101000 ; single address
Break.Set FooBar ; function name
Break.Set 0xFFF00244 /onchip /program ; single address
Break.Set 0xFFF00244 /onchip ; single address
Break.Set MyFlashFunction /onchip ; function name
Break.Set 0x2000--0x2fff /onchip ; address range
Break.Set 0xFFF00244 /read ; single address read
Break.Set 0xFFF00244 /write ; single address write
Break.Set 0xFFF00244 /readwrite ; single address any
Break.Set nMyValue /write ; variable name
Break.Set 0x2000--0x2fff /readwrite ; address range

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Access Classes
Access classes are used to specify how TRACE32 PowerView accesses memory, registers of
peripheral modules, addressable core resources, coprocessor registers and the TRACE32 Virtual
Memory.
Addresses in TRACE32 PowerView consist of:
• An access class, which consists of one or more letters/numbers followed by a colon (:)
• A number that determines the actual address
Here are some examples:
Access Classes to Memory and Memory Mapped Resources
The following memory access classes are available:
In addition to the access classes, there are access class attributes: Examples:
Command: Effect:
Data.List P:0x1000 Opens a List window displaying program memory
Data.dump D:0xFF800000 /LONG Opens a DUMP window at data address 0xFF800000
Data.Set SPR:415. %Long 0x00003300 Write value 0x00003300 to the SPR IVOR15
PRINT Data.Long(ANC:0xFFF00100) Print data value at physical address 0xFFF00100
Access Class Description
P Program (memory as seen by core’s instruction fetch)
D Data (memory as seen by core’s data access)
IC L1 Instruction Cache (or L1 Unified cache)
DC L1 Data Cache
L2 L2 Cache
NC No Cache (access with caching inhibited)
Command: Effect:
Data.List SP:0x1000 Opens a List window displaying supervisor program memory
Data.Set ED:0x3330 0x4F Write 0x4F to address 0x3330 using real-time memory access