Lauterbach M32R User manual

MANUAL
Release 02.2023
M32R Debugger and Trace

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M32R Debugger and Trace
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ...................................................................................................................... 
ICD In-Circuit Debugger ................................................................................................................ 
Processor Architecture Manuals .............................................................................................. 
M32R ......................................................................................................................................... 
M32R Debugger and Trace .................................................................................................. 1
Introduction ....................................................................................................................... 5
Brief Overview of Documents for New Users 5
Demo and Start-up Scripts 5
Warning .............................................................................................................................. 7
Quick Start ......................................................................................................................... 8
Troubleshooting ................................................................................................................ 11
SYStem.Up Errors 11
Memory Access Errors 11
FAQ ..................................................................................................................................... 11
CPU specific SYStem Settings and Restrictions ........................................................... 12
SYStem.CONFIG Configure debugger according to target topology 12
SYStem.CPU Select target CPU 12
SYStem.JtagClock Define JTAG clock 13
SYStem.LOCK Lock and tristate the debug port 13
SYStem.MemAccess Select memory access mode 14
SYStem.Mode Establish the communication with the target 15
SYStem.Option Display SYStem window 15
SYStem.Option.DBI Enables program break via debug interrupt 15
SYStem.Option.IMASKASM Disable interrupts while single stepping 16
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 16
SYStem.Option.KEYCODE Code protection 17
SYStem.Option.TriState Allow debugger to drive JTAG and reset 18
SYStem.state Display SYStem.state window 18
Trace specific Commands ................................................................................................ 19
SYStem.Option.BTM Enables program trace messages 19
SYStem.Option.DTM Enables data trace messages 19
SYStem.Option.STALL Trace message overrun control 19

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SYStem.Option.TRCLK Trace output clock ratio 20
SYStem.Option.TRDATA Trace port width 20
TrOnchip ............................................................................................................................ 21
TrOnchip.RESet Resets all TO settings 21
TrOnchip.state Opens configuration panel 22
Security Levels of the M32R Family ................................................................................ 23
Security Level 23
Flash Erase if Device is secured 24
General Restrictions and Hints 25
Floating Point Formats 26
Integer Access Keywords 26
JTAG Connection .............................................................................................................. 27
Mechanical Description of the 10-pin Debug Cable 27
Electrical Description of the 10-pin Debug Cable 27
Mechanical Description of the 20-pin Trace Connector 28
Memory Classes ................................................................................................................ 30

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M32R Debugger and Trace
Version 10-Feb-2023

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©1989-2023 Lauterbach
Introduction
This document describes the processor specific settings and features of the TRACE32 debugger for the
following Renesas M32R CPU families:
• (SDI-3) M32192, M32195, M32196, M32185, M32186
• (SDI-2) M32176, M32180
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
If some of the described functions, options, signals or connections in this Processor Architecture Manual are
only valid for a single CPU or for specific families, the names of the families are added in brackets.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Training Basic Debugging” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
Demo and Start-up Scripts
Lauterbach provides ready-to-run start-up scripts for known M32R based hardware.

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To search for PRACTICE scripts, do one of the following in TRACE32 PowerView:
• Type at the command line: WELCOME.SCRIPTS
• or choose File menu > Search for Script.
You can now search the demo folder and its subdirectories for PRACTICE start-up scripts
(*.cmm) and other demo software.
You can also manually navigate in the ~~/demo/m32r/ subfolder of the system directory of TRACE32.

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Warning
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.

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Quick Start
Starting up the debugger is done as follows:
1. Select the device prompt for the ICD Debugger and reset the system.
The device prompt B:: is normally already selected in the TRACE32 command line. If this is not the
case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do
not start directly after booting the TRACE32 development tool.
2. Specify the CPU specific settings.
The default values of all other options are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
3. Set up data for electrical interface.
Normally the default value is 10.0 MHz, but the it can be increased up to 25 MHz.
4. Inform the debugger about read only and none-readable address ranges (ROM, FLASH).
The BreakOnchip information is necessary to decide where on-chip breakpoints must be used. On-
chip breakpoints are necessary to set program breakpoints to FLASH/ROM. The sections of FLASH
and ROM depend on the specific CPU and its chip selects. Accesses to invalid addresses can cause
unrecoverable bus errors. To avoid bus errors from the debugger side use the subcommands of MAP
to define inaccessible memory areas. Bus errors can be removed by executing SYStem.Up. Make
sure that there isn’t any TRACE32 window open which accesses to a inaccessible memory that is not
masked out, otherwise the bus error can occur again.
B::
RESet
SYStem.CPU <cpu_type>
SYStem.JtagClock <frequency>
MAP.DenyAccess
MAP.NoDenyAccess <range>
MAP.BOnchip <range>

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5. Enter debug mode.
This command resets the CPU and enters debug mode. After this command is executed, it is possible
to access memory and registers.
6. Configure chip according application.
Before loading binary data into the processor memory, the memory should be made writable for the
debugger. Therefore processor configuration registers have to be set e.g. chip select register.
7. Load the program.
The format of the Data.LOAD command depends on the file format generated by the compiler. It is
recommended to use the option /Verify that verifies all written data. This test discovers a problem with
the electrical connection, wrong chip configurations or linker command file settings.
For a detailed description of the Data.LOAD command and all available options, see “Data” in
“General Commands Reference Guide D” (general_ref_d.pdf).
SYStem.Up
Data.LOAD.SR program.abs /Verify ; SR specifies the format,
; program.abs is the file name

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A typical start sequence for the MSC8101 is shown below. This sequence can be written to a PRACTICE
script file (*.cmm, ASCII format) and executed with the command DO <file>. Other sequences can be found
in the directory ~~/demo/m32r.
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
B:: ; Select the ICD device prompt
WinClear ; Clear all windows
SYS.CPU M32196 ; Select CPU
SYS.JC 15000000. ; Choose JTAG frequency
SYStem.Up ; Reset the target and enter debug
; mode
MAP.DENYACCESS ; Forbid any access to the memory in
; general
MAP.BONCHIP 0x0000--0x007FFF
; ROM
; Specifies the program memory where
; on-chip breakpoints must be used
Data.LOAD.SR Sieve.abs /Verify ; Load the application, verify the
; process
Go main ; Run and break at main()
List.Mix ; Open source window *)
Register.view /SpotLight ; Open register window *)
Var.Local ; Open window with local variables *)

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Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
• The JTAG lines are not connected correctly.
• The target has no power.
• The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
• The target is in reset:
The debugger controls the processor reset and use the RESET line to reset the CPU on every
SYStem.Up. Therefore no external R-C combination or external reset controller is allowed.
• There is logic added to the JTAG state machine:
By default the debugger supports only one processor in one JTAG chain. If the processor is only
one member of a JTAG chain the debugger has to be informed about the target JTAG chain
configuration. Use the SYStem.CONFIG command to specify the position of the device in the
JTAG-chain.
• There are additional loads or capacities on the JTAG lines.
Memory Access Errors
After system up is completed successfully, data can be written to or read from memory. Trying to access
memory not belonging to the memory map of the processor will be refused with the error message
and When a unrecoverable bus error occurs the target processor has to be reset.
FAQ
Please refer to https://support.lauterbach.com/kb.
no memory mapped at address D:XXXXXXXX
bus error generated by CPU

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CPU specific SYStem Settings and Restrictions
Trace features can only be used, if a special device and /or a special adapter board (Pitch-Converter) is
used. Both products are provided by Renesas.
SYStem.CONFIG Configure debugger according to target topology
The SYSTem.CONFIG command group is not supported for the M32R.
SYStem.CPU Select target CPU
Selects the processor type.
The processor type must be selected by the SYStem.CPU command before issuing any other target related
commands.
NOTE: All trace related settings described here are only relevant, if the device provides
trace capabilities!
Format: SYStem.CPU <cpu>
<cpu>:M32192 | M32192FPU | M32176 | M32180

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SYStem.JtagClock Define JTAG clock
Default frequency: 10 MHz.
Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. The
frequency affects e.g. the download speed. It could be required to reduce the JTAG frequency if there are
buffers, additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency
will not work on all systems and will result in an erroneous data transfer. Therefore we recommend to use
the default setting if possible.
When the debugger is not working correctly (e.g. memory is flickering) decrease the JtagClock.
SYStem.LOCK Lock and tristate the debug port
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give
debug access to another tool.
Format: SYStem.JtagClock [<frequency>]
SYStem.BdmClock (deprecated)
<frequency>:6kHz…25 MHz
1250000. | 2500000. | 5000000. | 10000000.
<frequency> The debugger cannot select all frequencies accurately. It chooses the next
possible frequency and displays the real value in the SYStem.state window.
Besides a decimal number like “100000.’ short forms like”10kHz” or “15MHz”
can also be used. The short forms imply a decimal value, although no “.” is
used.
Format: SYStem.LOCK [ON | OFF]

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SYStem.MemAccess Select memory access mode
Default: Enable.
Format: SYStem.MemAccess <mode>
<mode>: CPU
StopAndGo
Denied
Enable
CPU (deprecated)
Provides access to memory while the core is running.
StopAndGo Temporarily halts the core(s) to perform the memory access. Each stop
takes some time depending on the speed of the JTAG port, the number of
the assigned cores, and the operations that should be performed. For
more information, see below.
Denied No access to memory while the core is running.

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SYStem.Mode Establish the communication with the target
SYStem.Option Display SYStem window
It has the same effect as SYStem.state
SYStem.Option.DBI Enables program break via debug interrupt
Default: OFF.
When DBI is ON, the chip will stop faster rather than via SW control, provided the CPU offers DBI capability.
Format: SYStem.Mode <mode>
SYStem.Down (alias for SYStem.Mode Down)
SYStem.Up (alias for SYStem.Mode Up)
<mode>: Down
Up
Down Disables the debugger (default). The state of the CPU remains
unchanged. The JTAG port is tristated if SYStem.Option.TriState is
checked.In other case the debugger drives JTAG signals and Reset.
Up Resets the target, sets the CPU to debug mode and stops the CPU. After
the execution of this command the CPU is stopped and all register are
set to the default level.
Attach
Go
StandBy
Not available.
Format: SYStem.Option.DBI [ON | OFF]

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SYStem.Option.IMASKASM Disable interrupts while single stepping
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
Format: SYStem.Option.IMASKASM [ON | OFF]
Format: SYStem.Option.IMASKHLL [ON | OFF]

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SYStem.Option.KEYCODE Code protection
Default: 12 times 0xFF.
Some of the devices support Code Protection ID feature. Without a valid ID code, there is no access to the
device by the debugger.
Use the AREA window to get further information about the Security status after startup.
Use the following sequence in all your startup scripts or enter it in the command line one time in order to get
access to the device:
By default use:
If the device is blank, the debugger automatically uses 12 time 0xFF per default. Then no SYS.OPTION
KEYCODE command is needed. The number and location of bytes depends on the use MCU. It is normally
hard coded!
Format: SYStem.Option.Keycode [1…32 Byte keycode]
SYStem.Option.KEYCODE up to 32 byte representing your keycode
SYS.OPTION KEYCODE 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF\
0xFF 0xFF
; Source code example for Renesas Compiler (CPU 32192, code location
; 0x00084)
.SECTION PROTECTID, DATA, ALIGN=1
; H'0000 0084 Protect ID
.DATA.B H'FF
.DATA.B H'FF,H'FF,H'FF,H'FF,H'FF,H'FF,H'FF
.DATA.B H'FF,H'FF,H'FF,H'FF

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SYStem.Option.TriState Allow debugger to drive JTAG and reset
Default: OFF.
If this option is OFF the JTAG signals and nRST line are never driven by the debugger.
SYStem.state Display SYStem.state window
Displays the SYStem.state window.
Format: SYStem.Option.TriState [ON | OFF]
Format: SYStem.state

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Trace specific Commands
SYStem.Option.BTM Enables program trace messages
Default: ON.
The option can be switched when the chip has trace support. When BTM is ON, the chip delivers program
trace messages.
SYStem.Option.DTM Enables data trace messages
Default: OFF.
The option can be used if the chip has trace support. When the option is set to READ|WRITE|READWRITE,
the CPU generates data trace messages, according to the selected access type.
SYStem.Option.STALL Trace message overrun control
Default: OFF.
The option can be set when the chip has trace support and defines the behavior that becomes active when
the chip intern trace message FIFO buffer gets full. Stall OFF will cause losing of messages when the buffer
overruns.
Format: SYStem.Option.BTM [ON | OFF]
Format: SYStem.Option.DTM [OFF |Read |Write |ReadWrite]
Format: SYStem.Option.STALL [ON | OFF]

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SYStem.Option.TRCLK Trace output clock ratio
Default: 1/2.
The option can be set when the chip has trace support and defines the frequency of the trace output clock
based on the processor frequency. High frequencies can cause electrical connection problems during the
record of trace messages.
SYStem.Option.TRDATA Trace port width
Default: 8.
The option can be set when the chip has trace support and defines port width of the trace data. The
maximum is defined by the derivatives maximum trace pin count.
Format: SYStem.Option.TRCLK [1/8 |1/4 |1/3 |1/2 |*1|*2 |*3 |*4]
Format: SYStem.Option.TRDATA [4|8]