Lauterbach C2000 User manual

MANUAL
Release 02.2023
C2000 Debugger

C2000 Debugger | 2
©1989-2023 Lauterbach
C2000 Debugger
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ...................................................................................................................... 
ICD In-Circuit Debugger ................................................................................................................ 
Processor Architecture Manuals .............................................................................................. 
TI DSPs ..................................................................................................................................... 
C2000 Debugger ................................................................................................................... 1
History ................................................................................................................................ 4
Introduction ....................................................................................................................... 5
Brief Overview of Documents for New Users 5
Demo and Start-up Scripts 5
Converter from GEL to PRACTICE .................................................................................. 6
Warning .............................................................................................................................. 7
DSP specific Implementations ......................................................................................... 8
Trigger 8
Breakpoints 8
Software Breakpoints 8
On-chip Breakpoints for Instructions 8
On-chip Breakpoints for Data 8
Memory Classes 9
DSP specific SYStem Commands ...................................................................................10
SYStem.CONFIG.state Display target configuration 10
SYStem.CONFIG Configure debugger according to target topology 11
<parameters> describing the “DebugPort” 17
<parameters> describing the “JTAG” scan chain and signal behavior 20
<parameters> describing a system level TAP “MultiTap” 24
<parameters> configuring a CoreSight Debug Access Port “AP” 26
<parameters> describing debug and trace “Components” 32
<parameters> which are “Deprecated” 41
SYStem.CONFIG.ERAD Embedded real-time analysis and diagnostic module 45
SYStem.CPU Select the used CPU 45
SYStem.JtagClock Define JTAG frequency 46
SYStem.LOCK Tristate the JTAG port 47
SYStem.MemAccess Real-time memory access (non-intrusive) 48

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SYStem.Mode Establish the communication with the target 48
SYStem.Option.AHBHPROT Select AHB-AP HPROT bits 49
SYStem.Option.AXIACEEnable ACE enable flag of the AXI-AP 49
SYStem.Option.AXICACHEFLAGS Configure AXI-AP cache bits 50
SYStem.Option.AXIHPROT Select AXI-AP HPROT bits 50
SYStem.Option.DAPDBGPWRUPREQ Force debug power in DAP 51
SYStem.Option.DAPNOIRCHECK No DAP instruction register check 51
SYStem.Option.DAPREMAP Rearrange DAP memory map 52
SYStem.Option.DAPSYSPWRUPREQ Force system power in DAP 52
SYStem.Option.DEBUGPORTOptions Options for debug port handling 53
SYStem.Option.ExecutionMode Sets the CPU execution mode 54
SYStem.Option.IMASKASM Disable interrupts while single stepping 54
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 54
SYStem.Option.TargetServer Use target server from Texas Instruments 55
SYStem.RESetOut Reset target without reset of debug port 55
TrOnchip Commands ........................................................................................................ 56
TrOnchip.state Display on-chip trigger window 56
TrOnchip.RESet Set on-chip trigger to default state 56
ERAD Commands .............................................................................................................. 57
ERAD Embedded real-time analysis and diagnostic module 57
ERAD.OFF Turn ERAD features off 57
ERAD.ON Turn ERAD features on 57
JTAG Connection .............................................................................................................. 58
Mechanical Description of the 20-pin Debug Cable 58
Electrical Description of the 20-pin Debug Cable 59
Mechanical Description of the TI Connector 60
FAQ ..................................................................................................................................... 60
Operation Voltage ............................................................................................................. 61

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C2000 Debugger
Version 10-Feb-2023
History
23-Nov-22 New command SYStem.Option.ExecutionMode.

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Introduction
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Training Basic Debugging” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
Demo and Start-up Scripts
Lauterbach provides ready-to-run start-up scripts for known C2000 based hardware.
To search for PRACTICE scripts, do one of the following in TRACE32 PowerView:
• Type at the command line: WELCOME.SCRIPTS
• or choose File menu > Search for Script.
You can now search the demo folder and its subdirectories for PRACTICE start-up scripts
(*.cmm) and other demo software.
You can also manually navigate in the ~~/demo/c2000/ subfolder of the system directory of TRACE32.

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Converter from GEL to PRACTICE
The General Extension Language (GEL) is an interpretive language similar to C that lets you create
functions to extend Code Composer Studio’s usefulness. The converter allows you to convert GEL language
into PRACTICE scripts (*.cmm), which can be used directly in TRACE32.
For more detailed information on that converter please refer to “Converter from GEL to PRACTICE”
(converter_gel.pdf).

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Warning
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.

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DSP specific Implementations
Trigger
A bidirectional trigger system allows the following two events:
• Trigger an external system (e.g. logic analyzer) if the program execution is stopped.
• Stop the program execution if an external trigger is asserted.
For more information refer to the TrBus command.
If a DEBUG INTERFACE (LA-7701) is used the trigger system has the following restrictions:
• After starting the application there is a delay until the trigger system is working. The delay
depends on the host system and the JTAG frequency. It will be typically between 25 and 100 s.
• If a terminal window is open the response time of the trigger system is undefined. It is
recommended not to use the trigger system and terminal window at the same time.
Breakpoints
Software Breakpoints
If a software breakpoint is used, the original code at the breakpoint location is temporarily patched by a
breakpoint code. There is no restriction in the number of software breakpoints.
On-chip Breakpoints for Instructions
If on-chip breakpoints are used, the resources to set the breakpoints are provided by the CPU. Those CPU
resources only allow to set single address instruction breakpoints.
On-chip Breakpoints for Data
To stop the CPU after a read or write access to a memory location on-chip breakpoints are required. In the
DSP notation these breakpoints are called watch points (WP).

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Overview
•On-chip breakpoints: Total amount of available on-chip breakpoints.
•Instruction breakpoints: Number of on-chip breakpoints that can be used to set program
breakpoints into ROM/FLASH/EPROM.
•Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
•Data Value breakpoint: Number of on-chip data breakpoints that can be used to stop the
program when a specific data value is written to an address or when a specific data value is read
from an address.
Memory Classes
The following DSP specific memory classes are available.
To access a memory class, write the class in front of the address. Prepending an E as attribute to the
memory class will make memory accesses possible, even when the target CPU is running. See
SYStem.MemAccess and SYStem.CpuAccess for more information.
Examples:
Core
On-chip
breakpoints
Instruction
breakpoints
Read/Write
breakpoint
Data Value
breakpoints
C28x 2 or 10 (with
ERAD module)
2 single addresses 2 (only with
ERAD module)
1 (only with
ERAD module)
Memory Class Description
PProgramMemory
D Data Memory
VM Virtual Memory (memory on the debug system)
E Emulation Memory, Pseudo Dualport Access to Memory.
Data.dump D:0--0xff
Data.Dump ED:0x8000
Data.List EP:main

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DSP specific SYStem Commands
SYStem.CONFIG.state Display target configuration
Opens the SYStem.CONFIG.state window, where you can view and modify most of the target
configuration settings. The configuration settings tell the debugger how to communicate with the chip on
the target board and how to access the on-chip debug and trace facilities in order to accomplish the
debugger’s operations.
Alternatively, you can modify the target configuration settings via the TRACE32 command line with the
SYStem.CONFIG commands. Note that the command line provides additional SYStem.CONFIG
commands for settings that are not included in the SYStem.CONFIG.state window.
Format: SYStem.CONFIG.state [/<tab>]
<tab>:DebugPort | Jtag | MultiTap | AccessPorts | COmponents
<tab> Opens the SYStem.CONFIG.state window on the specified tab. For tab
descriptions, see below.
DebugPort
(default)
The DebugPort tab informs the debugger about the debug connector
type and the communication protocol it shall use.
For descriptions of the commands on the DebugPort tab, see
DebugPort.
Jtag The Jtag tab informs the debugger about the position of the Test Access
Ports (TAP) in the JTAG chain which the debugger needs to talk to in
order to access the debug and trace facilities on the chip.
For descriptions of the commands on the Jtag tab, see Jtag.
MultiTap Informs the debugger about the existence and type of a System/Chip
Level Test Access Port. The debugger might need to control it in order to
reconfigure the JTAG chain or to control power, clock, reset, and security
of different chip components.
For descriptions of the commands on the MultiTap tab, see MultiTap.

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SYStem.CONFIG Configure debugger according to target topology
AccessPorts This tab informs the debugger about an Arm CoreSight Access Port (AP)
and about how to control the AP to access chip-internal memory busses
(AHB, APB, AXI) or chip-internal JTAG interfaces.
For a descriptions of a corresponding commands, refer to AP.
COmponents The COmponents tab informs the debugger (a) about the existence and
interconnection of on-chip CoreSight debug and trace modules and (b)
informs the debugger on which memory bus and at which base address
the debugger can find the control registers of the modules.
For descriptions of the commands on the COmponents tab, see
COmponents.
Format: SYStem.CONFIG <parameter>
SYStem.MultiCore <parameter> (deprecated)
<parameter>:
(DebugPort)
CJTAGFLAGS <flags> (C7000 only)
CONNECTOR [MIPI34 | MIPI20T] (C7000 only)
CORE <core> <chip>
CoreNumber <number>
DEBUGPORT [DebugCable0 | DebugCableA | DebugCableB]
DEBUGPORTTYPE [JTAG | SWD | CJTAG]
Slave [ON | OFF]
SWDP [ON | OFF] (C7000 only)
SWDPIdleHigh [ON | OFF]
SWDPTargetSel <value>
TriState [ON | OFF]
<parameter>:
(JTAG cont.)
DAPDRPOST <bits>
DAPDRPRE <bits>
DAPIRPOST <bits>
DAPIRPRE <bits>
DRPOST <bits>
DRPRE <bits>
ETBDRPOST <bits> (C5000 only)
ETBDRPRE <bits> (C5000 only)
ETBIRPOST<bits> (C5000 only)
ETBIRPRE <bits> (C5000 only)

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<parameter>:
(JTAG cont.)
IRPOST<bits>
IRPRE <bits>
Slave [ON | OFF]
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
<parameter>:
(MultiTap)
DAPTAP <tap>
DEBUGTAP <tap>
ETBTAP <tap> (C5000 only)
MULTITAP [NONE |IcepickA |IcepickB |IcepickC |IcepickD |IcepickBB |
IcepickBC |IcepickCC |IcepickDD |
JtagSEQuence <sub_cmd>]
NJCR <tap>
SLAVETAP <tap>
<parameter>:
(AccessPorts
)
AHBAPn.Base <address>
AHBAPn.HPROT [<value> | <name>]
AHBAPn.Port <port>
AHBAPn.RESet
AHBAPn.view
AHBAPn.XtorName <name>
APBAPn.Base <address>
APBAPn.Port <port>
APBAPn.RESet
APBAPn.view
APBAPn.XtorName <name>
AXIAPn.ACEEnable [ON |OFF]
AXIAPn.Base <address>
AXIAPn.CacheFlags <value>
AXIAPn.HPROT [<value> | <name>]
AXIAPn.Port <port>
AXIAPn.RESet
AXIAPn.view
AXIAPn.XtorName <name>
DEBUGAPn.Port <port>
DEBUGAPn.RESet
DEBUGAPn.view
DEBUGAPn.XtorName <name>
JTAGAPn.Base <address>
JTAGAPn.Port <port>
JTAGAPn.CorePort <port>
JTAGAPn.RESet
JTAGAPn.view
JTAGAPn.XtorName <name>

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<parameter>:
(AccessPorts
cont.)
MEMORYAPn.HPROT [<value> | <name>]
MEMORYAPn.Port <port>
MEMORYAPn.RESet
MEMORYAPn.view
MEMORYAPn.XtorName <name>
<parameter>:
(COmponents)
ADTF.Base <address>
ADTF.RESet
ADTF.Type [NONE |ADTF |ADTF2 |GEM]
ADTF.view
AET.Base <address> (C5000, C6000, C7000 only)
AET.RESet (C5000, C6000, C7000 only)
AET.view (C5000, C6000, C7000 only)
<parameter>:
(COmponents
cont.)
CMI.Base <address>
CMI.RESet
CMI.TraceID <id>
CMI.view
COREDEBUG.Base <address> (C7000 only)
COREDEBUG.RESet (C7000 only)
COREDEBUG.view (C7000 only)
CTI.Base <address>
CTI.Config [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 |
QV1]
CTI.RESet
CTI.view
DRM.Base <address>
DRM.RESet
DRM.view
EPM.Base <address>
EPM.RESet
EPM.view
ETB.ATBSource <source>
ETB.Base <address>
ETB.Name <string>
ETB.NoFlush [ON | OFF]
ETB.RESet
ETB.Size <size>
ETB.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL-
STOP | FULLCTI]
ETB.view

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<parameter>:
(COmponents
cont.)
FUNNEL.ATBSource <sourcelist>
FUNNEL.Base <address>
FUNNEL.Name <string>
FUNNEL.PROGrammable [ON | OFF]
FUNNEL.RESet
FUNNEL.view
OCP.Base <address>
OCP.RESet
OCP.TraceID <id>
OCP.view
PMI.Base <address>
PMI.RESet
PMI.TraceID <id>
PMI.view
<parameter>:
(Components
cont.)
REP.ATBSource <source>
REP.Base <address>
REP.Name <string>
REP.RESet
REP.view
SC.Base <address>
SC.RESet
SC.TraceID <id>
SC.view
STM.Base <address>
STM.Mode [None | SDTI | STP | STP64 | STPv2 | STPv2LE]
STM.Name <string>
STM.RESet
STM.Type [None | GenericARM | SDTI | TI]
STM.view
TBR.ATBSource <source>
TBR.Base <address>
TBR.Name <string>
TBR.NoFlush [ON | OFF]
TBR.RESet
TBR.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL-
STOP | FULLCTI]
TBR.view
TPIU.ATBSource <source>
TPIU.Base <address>
TPIU.Name <string>
TPIU.RESet
TPIU.Type [CoreSight | Generic]
TPIU.view

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The SYStem.CONFIG commands inform the debugger about the available on-chip debug and trace
components and how to access them.
<parameter>:
(Components
cont.)
TRACEPORT.Name
TRACEPORT.RESet
TRACEPORT.TraceSource
TRACEPORT.Type
TRACEPORT.view
TRC.Base <address> (C7000 only)
TRC.RESet (C7000 only)
TRC.view (C7000 only)
<parameter>:
(Deprecated)
COREBASE <address>
CTIBASE <address>
DEBUGBASE <address>
ETBBASE <address>
ETBFUNNELBASE <address>
ETFBASE <address>
ETMBASE <address>
<parameter>:
(Deprecated cont.)
FUNNEL2BASE <address>
FUNNELBASE <address>
HTMBASE <address>
ITMBASE <address>
RTPBASE <address>
SDTIBASE <address>
STMBASE <address>
TIADTFBASE <address>
TIDRMBASE <address>
TIEPMBASE <address>
TIOCPBASE <address>
TIOCPTYPE <type>
TIPMIBASE <address>
TISCBASE <address>
TISTMBASE <address>
TPIUBASE <address>
TPIUFUNNELBASE <address>
TRACEETBFUNNELPORT <port>
TRACEFUNNELPORT<port>
TRACETPIUFUNNELPORT <port>
view
AHBACCESSPORT <port>
APBACCESSPORT <port>
AXIACCESSPORT <port>
COREJTAGPORT <port>
DEBUGACCESSPORT <port>
JTAGACCESSPORT <port>
MEMORYACCESSPORT <port>

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This is a common description of the SYStem.CONFIG command group for the TI C2000, C5000, C6000
and C7000 DSPs. Each debugger will provide only a subset of these commands. Some commands need a
certain CPU type selection (SYStem.CPU <type>) to become active and it might additionally depend on
further settings.
Ideally you can select with SYStem.CPU the chip you are using which causes all setup you need and you do
not need any further SYStem.CONFIG command.
The SYStem.CONFIG command information shall be provided after the SYStem.CPU command, which
might be a precondition to enter certain SYStem.CONFIG commands, and before you start up the debug
session e.g. by SYStem.Up.

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<parameters> describing the “DebugPort”
CJTAGFLAGS <flags> Activates bug fixes for “cJTAG” implementations.
Bit 0: Disable scanning of cJTAG ID.
Bit 1: Target has no “keeper”.
Bit 2: Inverted meaning of SREDGE register.
Bit 3: Old command opcodes.
Bit 4: Unlock cJTAG via APFC register.
Default: 0
CONNECTOR
[MIPI34 | MIPI20T]
Specifies the connector “MIPI34” or “MIPI20T” on the target. This
is mainly needed in order to notify the trace pin location.
Default: MIPI34 if CombiProbe is used, MIPI20T if µTrace
(MicroTrace) is used.
CORE <core> <chip> The command helps to identify debug and trace resources which
are commonly used by different cores. The command might be
required in a multicore environment if you use multiple debugger
instances (multiple TRACE32 PowerView GUIs) to simultaneously
debug different cores on the same target system.
Because of the default setting of this command
debugger#1: <core>=1 <chip>=1
debugger#2: <core>=1 <chip>=2
...
each debugger instance assumes that all notified debug and trace
resources can exclusively be used.
But some target systems have shared resources for different
cores, for example a common trace port. The default setting
causes that each debugger instance controls the same trace port.
Sometimes it does not hurt if such a module is controlled twice.
But sometimes it is a must to tell the debugger that these cores
share resources on the same <chip>. Whereby the “chip” does not
need to be identical with the device on your target board:
debugger#1: <core>=1 <chip>=1
debugger#2: <core>=2 <chip>=1

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CORE <core> <chip>
(cont.)
For cores on the same <chip>, the debugger assumes that the
cores share the same resource if the control registers of the
resource have the same address.
Default:
<core> depends on CPU selection, usually 1.
<chip> derived from CORE= parameter in the configuration file
(config.t32), usually 1. If you start multiple debugger instances with
the help of t32start.exe, you will get ascending values (1, 2, 3,...).
CoreNumber <number> Number of cores to be considered in an SMP (symmetric
multiprocessing) debug session. There are core types which can
be used as a single core processor or as a scalable multicore
processor of the same type. If you intend to debug more than one
such core in an SMP debug session you need to specify the
number of cores you intend to debug.
Default: 1.
DEBUGPORT
[DebugCable0 | DebugCa-
bleA | DebugCableB]
It specifies which probe cable shall be used e.g. “DebugCableA” or
“DebugCableB”. At the moment only the CombiProbe allows to
connect more than one probe cable.
Default: depends on detection.
DEBUGPORTTYPE
[JTAG | SWD | CJTAG]
It specifies the used debug port type “JTAG”, “SWD”, “CJTAG”,
“CJTAG-SWD”. It assumes the selected type is supported by the
target.
Default: JTAG.
What is NIDnT?
NIDnT is an acronym for “Narrow Interface for Debug and Test”.
NIDnT is a standard from the MIPI Alliance, which defines how to
reuse the pins of an existing interface (like for example a microSD
card interface) as a debug and test interface.
To support the NIDnT standard in different implementations,
TRACE32 has several special options:
Slave [ON | OFF] If several debuggers share the same debug port, all except one
must have this option active.
JTAG: Only one debugger - the “master” - is allowed to control the
signals nTRST and nSRST (nRESET). The other debuggers need
to have the setting Slave ON.
Default: OFF.
Default: ON if CORE=... >1 in the configuration file (e.g. config.t32).

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SWDP [ON | OFF] With this command you can change from the normal JTAG
interface to the serial wire debug mode. SWDP (Serial Wire Debug
Port) uses just two signals instead of five. It is required that the
target and the debugger hard- and software supports this
interface.
Default: OFF.
SWDPIdleHigh
[ON | OFF]
Keep SWDIO line high when idle. Only for Serialwire Debug mode.
Usually the debugger will pull the SWDIO data line low, when no
operation is in progress, so while the clock on the SWCLK line is
stopped (kept low).
You can configure the debugger to pull the SWDIO data line
high, when no operation is in progress by using
SYStem.CONFIG SWDPIdleHigh ON
Default: OFF.
SWDPTargetSel <value> Device address in case of a multidrop serial wire debug port.
Default: none set (any address accepted).
TriState [ON | OFF] TriState has to be used if several debug cables are connected to a
common JTAG port. TAPState and TCKLevel define the TAP state
and TCK level which is selected when the debugger switches to
tristate mode.
Please note:
• nTRST must have a pull-up resistor on the target.
• TCK can have a pull-up or pull-down resistor.
• Other trigger inputs need to be kept in inactive state.
Default: OFF.

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<parameters> describing the “JTAG” scan chain and signal behavior
With the JTAG interface you can access a Test Access Port controller (TAP) which has implemented a state
machine to provide a mechanism to read and write data to an Instruction Register (IR) and a Data Register
(DR) in the TAP. The JTAG interface will be controlled by 5 signals:
• nTRST (reset)
• TCK (clock)
• TMS (state machine control)
• TDI (data input)
• TDO (data output)
Multiple TAPs can be controlled by one JTAG interface by daisy-chaining the TAPs (serial connection). If you
want to talk to one TAP in the chain, you need to send a BYPASS pattern (all ones) to all other TAPs. For this
case the debugger needs to know the position of the TAP it wants to talk to. The TAP position can be defined
with the first four commands in the table below.
…DRPOST <bits> Defines the TAP position in a JTAG scan chain. Number of TAPs in the
JTAG chain between the TDI signal and the TAP you are describing. In
BYPASS mode, each TAP contributes one data register bit. See possible
TAP types and example below.
Default: 0.
…DRPRE <bits> Defines the TAP position in a JTAG scan chain. Number of TAPs in the
JTAG chain between the TAP you are describing and the TDO signal. In
BYPASS mode, each TAP contributes one data register bit. See possible
TAP types and example below.
Default: 0.
…IRPOST <bits> Defines the TAP position in a JTAG scan chain. Number of Instruction
Register (IR) bits of all TAPs in the JTAG chain between TDI signal and
the TAP you are describing. See possible TAP types and example below.
Default: 0.
…IRPRE <bits> Defines the TAP position in a JTAG scan chain. Number of Instruction
Register (IR) bits of all TAPs in the JTAG chain between the TAP you are
describing and the TDO signal. See possible TAP types and example
below.
Default: 0.
NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE,
and DRPOST, you can try to detect the settings automatically with the
SYStem.DETECT.DaisyChain command.