Intel CHIPS DKHiQV-AGP User manual

DKHiQV-AGP
(Fab. Rev. A)
HiQVideo69000 AGP Demo
Kit Documentation
User’s Guide
Revision 1.0
July 1998

&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
Copyright Notice
Copyri
g
ht1998 Chips and Technolo
g
ies, Inc., a subsidiary of Intel Corporation. ALL RIGHTS RESERVED.
This manual is copyri
g
hted byChips andTechnolo
g
ies, Inc., asubsidiary of IntelCorporation. You may not reproduce, transmit,
transcribe, store in a retrieval system, or translate into any lan
g
ua
g
e or computer lan
g
ua
g
e, in any form or by any means - elec-
tronic, mechanical, ma
g
netic, optical, chemical, manual, or otherwise - any part of this publication without the express written
permission of Chips and Technolo
g
ies, Inc., a subsidiary of Intel Corporation.
Restricted Rights Legend
Use, duplication, or disclosure by the Government is subject to restrictions set forth in subpara
g
raph (c)(1)(ii) of the Ri
g
hts in
Technical Data and Computer Software clause at 252.277-7013.
Trademark Acknowledgment
CHIPS Lo
g
o is a re
g
istered trademark of Chips and Technolo
g
ies, Inc., a subsidiary of Intel Corporation.
HiQVideo, is a trademark of Chips and Technolo
g
ies, Inc., a subsidiary of Intel Corporation.
All other trademarks are the property of their respective holders.
3DQHO/LQN technology is licensed by Chips and Technologies, Inc., a subsidiary of Intel Corporation from Silicon Image, Inc. of
Palo Alto, CA. 3DQHO/LQN is a trademark of Silicon Image, Inc.
Disclaimer
This document provides general information for the customer. Chips and Technologies, Inc., a subsidiary of Intel Corporation,
reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most
recent revision ofthe document. CHIPS makes no warranty for theuse of its products and bears no responsibility for any errors
which may appear in this document. The customer should be on notice that many different parties hold patents on products,
components, and processes within the personal computer industry. Customers should ensure that their use of the products
does notinfringe uponanypatents. CHIPS respects thepatentrights of thirdparties and shall notparticipate in director indirect
patent infringement.

Revision History
Revision Date By Comment
1.0 7/1/98 JW/lnc/bjb Initial release for Fab. Rev. A Boards.

&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
Table of Contents
1.0 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.0 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 14MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 32KHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Accelerated Graphics Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.1 AGP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.2 AGP Initialization/Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.3 AGP BIOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.1 CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.2 Flat Panel Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.3 STN-DD Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.4 Simultaneous Display Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.5 Activity Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 DKHiQV-AGP Multimedia Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1 NTSC/PAL Composite Video Output (TV out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.2 Multimedia Card/TV Tuner Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.3 MPEG and ZV Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Mixed Voltage Generation and Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Power Sequencing and Backlight Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 VEESAFE for Panel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7.1 Low Voltage for Panel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7.2 High Voltage Operation for VEESAFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 3DQHO/LQN and LVDS Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8.1 PCLK for 3DQHO/LQN STNDD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8.2 Clean 3.3V Power for 3DQHO/LQN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.0 DKHiQV-AGP Installation Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 HiQVideo Utilities and Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.0 DKHiQV-AGP Board Configuration Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 DKHiQV-AGP Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 DKHiQV-AGP Demo Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 DKHiQV-AGP Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 DKHiQV-AGP Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.1 Default Settings with TV Out and Multimedia Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.2 Default Settings with TV Out Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4.3 Default Settings with Multimedia Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 DKHiQV-AGP Troubleshooting Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
List of Figures
Figure 1: 24 Bit Flat Panel Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2: 36 Bit Flat Panel Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3: Media Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4: MPEG Video In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5: DKHiQV-AGP Board Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Tables
Table 1: PCI Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2: Flat Panel Connection Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3: Video Sub-System Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4: DKHiQV-AGP Board Connector Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: DKHiQV-AGP Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6: DKHiQV-AGP (Rev. A) Board Configuration Settings for 69000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7: DKHiQV-AGP Jumper Configuration Settings for TV Out Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8: DKHiQV-AGP Jumper Configuration Settings for Multimedia Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
DKHiQV-AGP (Fab. Rev. A)
HiQVideo 69000 AGP Demo
Kit Documentation
1.0 Introduction/Product Description
The 69000 series graphics accelerators are very high performance LCD/CRT controllers that provide a com-
plete video subsystem solution with low power consumption, hardware acceleration for GUI applications
and a minimalcomponent count. The high level ofintegration permits a direct interface to the PCI Bus, thus
making the HiQVideocontroller a low-cost, high-performance graphics solution.
The demo kits for the 69000 in the Accelerated GraphicsPort (AGP) environment usesa base board known
as the DKHiQV-AGP DK Board. A daughtercard containing the graphics controller is installed onto the main
DK board to complete the design kit. This User’s Guide describes the main DK board. The use of a 69000
graphics accelerator on an ABHiQV daughtercard is also described in the ABHiQV User’s Guide.
The DKHiQV-AGP board is a full-size AT add-in card. It has bus connectors to interface with the AGP at
speeds up to 66MHz. The multiple jumper configurations and connectors allow the DK board to test perfor-
mance benchmarks, demonstrate various multimedia features supported by the HiQVideofamily, mea-
sure power consumption and connect to panels and monitors. This demo kit is intended for demonstration
purposes only and is not for use as a reference design. The designer should do the appropriate analysis
and simulation to verify the design meets the AGP design specifications (see AGP specification 2.1). The
69000 supports FRAME-based AGP or PCI-66MHz (see the PCIspecification 2.1 for fulldetails). Plug-and-
Play is possible on the AGP Bus, thus making AGP easy to use. The AGP uses the PCI-66MHz PCI (rev
2.1) specifications as an operational baseline. AGP does not replace the PCI bus in the system, but pro-
vides performance enhancements by way of sideband signals. The PCI autoconfiguration feature deter-
mines interrupt setting and software defaults. The 69000 HiQVideoVGA controller is mounted on a
daughtercard which plugs into a connector on the DKHiQV-AGP board to make a complete design kit. This
allows theuserto exchange silicon simply byreplacing the daughtercard without having toreplace the entire
kit.
This document describes the revision "A" of the DKHiQV-AGP printed circuit board.

DKHiQV-AGP (Fab. Rev. A) User’s Guide 2
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
2.0 Features
The DKHiQV-AGP has the following features when running a 69000 HiQVideocontroller:
• FRAME-based AGP (formally PCI-66)
• High Performance Flat Panel/CRT GUI Accelerator running on PCI Bus
• 50-pin flat panel connector for interfacing to most types of flat panels (up to 24 data bits).
• 26-pin flat panel connector for 12 additional data bits for panels having up to a 36-bit data word
width
• 15-pin standard VGA connector
• 40-pin MPEG connector for interfacing to an MPEG video card
• Two 25-pin and one 12-pin connector for interfacing to the multimedia daughtercard.
(A multimedia daughtercard can be purchased separately by ordering part number MM6555x Mul-
timedia Daughter Card).
• PCI BIOS ROM support, located on the daughtercard
• Flexible power supplies individually configurable to 3.3V and 5V for different blocks of the video
subsystem
• Onboard power sequencing
• VGA to NTSC/PAL conversion to provide S-VHS video and composite video outputs
• TV out and CRT enable/disable under software control
Note: Limited solution, CRT HSYNC/VSYNC only, not RGB
• ACT125 buffer for CSYNC to TV out encoder (AD722) to meet Vih spec
• 32 KHz improvement for better rise/fall times
• +5V removed from VCC jumpers; 3.3V-only for VGA controller VCC pins
Note: +5V can be reconnected with only one wire if needed for older products.
• RAMVCC separated from MVCC55X so that +5V can be used for DRAM while using 3.3V for VGA
controller VCC
• On daughtercard header, GVCC can be 3.3V instead of 5V to allow 3V EPROM to be used on the
daughtercard if desired
• Four new GND test points have been added and two existing GND points have been moved out
from under the daughtercard to be more accessible
• Low voltage option for VEESAFE (1K pot, fed by VDDSAFE)

3 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.0 Installation
The DKHiQV-AGP board is very flexible and can be configured for a variety options such as multimedia in-
terfaces supported by the HiQVideo69000 controller. The DK boardsupport a variety of direct panel and
CRT interfaces. The DK board also provides a simple and accurate way to measure the power dissipation
of various blocks of the subsystem such as the bus interface, the video memory interface and the display
logic.
The DK boards have bus connectors with gold fingers which connect to the AGP bus port. The board pro-
vides the capability to evaluate all the following interfaces: bus, flat panel, CRT, memory, MPEG, multime-
dia card and composite video. The boards also provide a mixed voltage capability with the ability to
measure power for different blocks of the video subsystem.
Refer to the 69000 Data Book for the available resolution modes.
The user may check the power-down operation of the HiQVideocontroller using a jumper (W1) on the DK
board.
The DKHiQV-AGP board also provides such features as:
z DC-to-DC Conversion
z Mixed Voltage Interface
z Power Sequencing
z Backlight Control
3.1 Reference Clocks
3.1.1 14MHz Reference Clock
The 69000 controller uses a TTL 14MHz signal connected to pin C3 as the reference clock. This clock pro-
vide a timing reference to all the internal logic blocks such as sequencer, CRT controller and graphics con-
troller.
3.1.2 32KHz Reference Clock
Panel power sequencing also requires a reference clock. Pin T4 supplies the 69000 with a 32 KHz signal
for this purpose. This clock also refreshes the DRAM. If the system uses non-self-refresh DRAMs, do not
apply this external 32 KHz clock to the chip (Y2 is not stuffed). This configuration generates a 37.3 KHz
signal from the internal 14 MHz power sequencing clock. Please refer to the XRCF[3] definition in the data
sheet for details.

DKHiQV-AGP (Fab. Rev. A) User’s Guide 4
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.2 Accelerated Graphics Port
3.2.1 AGP Bus Interface
The DK board interfaces directly with the AGP and supports PCI burst mode operation. The Accelerated
Graphics Port (AGP) is a high performance bus and is based on enhancements to the PCI bus. The AGP
uses the 66MHz PCI 2.1 specification as an operational baseline. The DKHiQV-AGP card does not support
the sideband signals.
3.2.2 AGP Initialization/Configuration
Initialization of an AGPdevice is done via the configuration mechanism defined by thePCI 2.1 specification.
This requires the device to respond to a PCI configuration transaction when a configuration command is
decoded. The PCI definition provides for complete software driven initialization and configuration using a
separate configuration address space. PCI devices may use 256 bytes of configuration address space for
this purpose. Forthe PCI Bus configuration, the HiQVideocontrollers use ten registers to identify the chip,
examine the various internal states, configure the video memory and BIOS ROM base addresses and con-
trolthesettingsforthevariousoperatingmodes. These registersare locatedinthePCIconfigurationspace.
The HiQVideocontrollers support both I/O mapped memory and memory mapped I/O.
3.2.3 AGP BIOS Interface
The DKHiQV-AGP incorporates a PCI Video BIOS in a27C512 EPROM (U2 on theABHiQV daughtercard).
The code size is 32KB (or 40KB) resident at address 0C0000. The HiQVideocontroller generates the
ROMCS# signal for the BIOS ROM. The PCI BIOS is developed for use with the PCI local bus configuration
as defined in the PCI Local Bus Specification Rev. 2.1. Each BIOS uses word pointers to the PCI Data
Structure at offset C000:18/E000:18. Table 1 defines the PCI data structure.
Table 1: PCI Data Structure
Note: The PCI BIOS is usually included in and merged with the system BIOS. For more detailed informa-
tion, please refer to the 69000 VGA BIOS OEM Reference Guides.
Register Mnemonic Register Name Offset
VENDID Vendor ID 00h
DEVID Device ID 02h
DEVCTL Device Control 04h
DEVSTAT Device Status 06h
REV Revision ID 08h
PRG Pro
g
rammin
g
Interface 09h
SUB Sub Class Code 0Ah
BASE Base Class Code 0Bh
MBASE Memory Base Address 10h
RBASE ROM Base Address 30h

5 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.3 Display Interface
3.3.1 CRT Display Interface
The DK Board provides direct interface to analog CRTs through an industry standard 15-pin connector(J4).
3.3.2 Flat Panel Display Interface
The DKHiQV-AGP board has a 50-pin connector(J5) which provides all necessary signals to interface with
any flatpanel having a dataword size of 24 bitsor less (see figure 1). The HiQVideocontroller has enough
drive for most panels and does not require any buffering on connectors J5 and J11.
The HiQVideoSeries controllers provide 8mA drive on all data and control signals (FR0A[2] must be set
to 1 when DVCC = 3.3V). A second connector (J11) provides the 12 additional data bits needed for 36-bit
panels (see Figure2). Table 2 has a summary for all panel interface connections.
3.3.3 STN-DD Buffer
STN-DD panels require video data alternating between two separate locations in memory. In addition, a
dual-drive panel requires data from both locations simultaneously. These operations require a frame stor-
age area, called a ’STN-DD buffer’. The HiQVideocontroller’s innovative architecture implements the
STN-DD buffer in an unused area of display memory, reducing chip count and video subsystem cost. The
embedded STN-DD buffer may be enabled by setting FR1A[0,7]=1,0.
Figure 1. shows the 24 bit panel pin assignments for the J5 connector:
Fi
g
ure 1: 24 Bit Flat Panel Connector Pinout
Name Pin # Pin # Name
[+5V] VDDSAFE 1 2 +12 VSAFE
(12 to 45V) or (-12 to -45V) VEESAFE 3 4 nc or DVCC55X (see JP4)
ENABKL 5 6 GND
M78 DE
GND 9 10 LP
FLM 11 12 GND
SNFCLK 13 14 GND
P0 15 16 P1
GND 17 18 P2
P3 19 20 GND
P4 21 22 P5
GND 23 24 P6
P7 25 26 GND
P8 27 28 P9
GND 29 30 P10
P11 31 32 GND
P12 33 34 P13
GND 35 36 P14
P15 37 38 GND
P16 39 40 P17
GND 41 42 P18
P19 43 44 GND
P20 45 46 P21
GND 47 48 P22
P23 49 50 GND

DKHiQV-AGP (Fab. Rev. A) User’s Guide 6
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
Figure 2. provides the 12 additional data bits needed for 36-bit panels on J11.:
Figure 2: 36 Bit Flat Panel Connector Pinout
3.3.4 Simultaneous Display Interface
The DKHiQV-AGP board supports simultaneous flat panel and CRT displays. The HiQVideocontrollers
supports 60 Hz vertical refresh for simultaneous display CRT and TFT/SSTN color panels. Simultaneous
display of CRT and DDSTN with 60 Hz vertical refresh on the CRT and 120 Hz vertical refresh on the ST-
NDD panel are also supported. In this mode, the ENAVEE(61), ENABKL (54), ACTI (53), M (69) and LP
(68) pins have multiple functions. For detailed functions, and implementations, please refer to the 69000
Databook and the DKHiQV-AGP schematics.
3.3.5 Activity Indicator
The HiQVideocontroller provides an output pin called ACTI (69000 pin V1) to facilitate an orderly power-
down sequence. The ACTI output is an active high signal which is driven high every time the CPU executes
a valid VGA memory read/write operation or VGA I/O read/write operation. The DKHiQV-AGP board has
an LED (D7) on the ACTI pin which will glow whenever there is a VGA Access. This pin is configured as
Activity Indicator by default when FR0C[4:3]=00. The power management logic may use this signal to put
the HiQVideocontroller into Panel Off or Standby power modes.
Table 2 summarizes the HiQVideopin connections for the different flat panel configurations.
Refer to the 69000 Databook for the 36-pin panel support information and pin assignments.
Name Pin # Pin # Name
GND 1 2 P24
GND 3 4 P25
GND 5 6 P26
GND 7 8 P27
GND 9 10 P28
GND 11 12 P29
GND 13 14 P30
GND 15 16 P31
GND 17 18 P32
GND 19 20 P33
GND 21 22 P34
GND 23 24 P35
GND 25 26 GND

7 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
Table 2: Flat Panel Connection Summary
Monochrome Color
Pin # Pin
Name DK 50pin Connect. Single Panel DD 8bit DD 16bit TFT 16bit TFT 18/24bit TFT HR 18/24bit STN 4bit pack STN Extended
4bit Pack
STN DD
8bit STN DD 16bit
Pixels Transferred
per Shift Clock 5 1/3 2-2/3 2-2/3 5-1/3
W6 P0 15 P0 UD3 UD7 B0 B0 B00 R0... R0... UR0... UR0...
V7 P1 16 P1 UD2 UD6 B1 B1 B01 GO... B0... UG0... UG0...
Y6 P2 18 P2 UD1 UD5 B2 B2 B02 B0... G1... UB0... UB0...
W7 P3 19 P3 UD0 UD4 B3 B3 B03 R1... R2... UR1... UR1...
V8 P4 21 P4 LD3 UD3 B4 B4 B10 G1... B2... LR0... LR0...
V7 P5 22 P5 LD2 UD2 G0 B5 B11 B1... G3... LG0... LG0...
W8 P6 24 P6 LD1 UD1 G1 B6 B12 B2... R4... LB0... LB0...
U9 P7 25 P7 LD0 UD0 G2 B7 B13 G2... B4... LR1... LR1...
V9 P8 27 - - LD7 G3 G0 G00 B2... SHFCLKU - UG1...
Y9 P9 28 - - LD6 G4 G1 G01 R3... - - UB1...
V10 P10 30 - - LD5 G5 G2 G02 G3... - - UR2...
Y9 P11 31 - - LD4 R0 G3 G03 B3... - - UG2...
V10 P12 33 - - LD3 R1 G4 G10 R4... - - LG1...
W10 P13 34 - - LD2 R2 G5 G11 G4... - - LB1...
Y10 P14 36 - - LD1 R3 G6 G12 B4... - - LR2...
U10 P15 37 - - LD0 R4 G7 G13 R5... - - LG2...
U11 P16 39 - - - - R0 R00 - - - -
W11 P17 40 - - - - R1 R01 - - - -
Y11 P18 42 - - - - R2 R02 - - - -
V11 P19 43 - - - - R3 R03 - - - -
Y12 P20 45 - - - - R4 R10 - - - -
Y13 P21 46 - - - - R5 R11 - - - -
V12 P22 48 - - - - R6 R12 - - - -
U12 P23 49 - - - - R7 R13 - - - -
U6 ENABKL 5 ENABKL ENBKL ENABKL ENABKL ENABKL ENABKL ENABKL ENABKL ENABKL ENABKL
Y5 SHFCLK 13 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK
V6M7MMMMMMMMMM
Y4 LP 10 LP LP LP LP LP LP LP LP LP LP
W5 FLM 11 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM
Y4/Y6 DE 8 DE DE DE DE DE DE DE DE DE DE
VDDSAFE 1----------
+12VSAFE 2----------
VEESAFE 42----------
GND 6,9,12,14,1
7,20,23,24,
29,32,35,
38,41,44,
47, 50

DKHiQV-AGP (Fab. Rev. A) User’s Guide 8
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.4 DKHiQV-AGP Multimedia Interfaces
3.4.1 NTSC/PAL Composite Video Output (TV Out)
The HiQVideocontrollers provide video encoder support and a composite sync signal which someencod-
ers require. DK boards incorporate an NTSC/PAL encoder from Analog Device (AD722 or AD723) to con-
vert the VGA signals to the composite NTSC video and S-VHS video signals. The board provides a
composite NTSC video connector J3 and a S-VHS video connector J1. Pin W6 switches between NTSC
and PAL modes. Composite Video Output is also referred to as TV Out. It can be either NTSC or PAL for-
mat.
Refer to Table 7 for TV-Out jumper settings.

9 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.4.2 Multimedia Card/TV Tuner Interface
The DKHiQV-AGP board provides a video interface from a multimedia card or zoom video port (ZV port).
The 65550 MM card provides YUV video to the DK board. For more detailed information, please refer to
the MM655x MM User’s Guide.
Refer to Table 8 for multimedia jumper settings.
Figure 3 shows the multimedia connector pins:
Fi
g
ure 3: Media Connector Pinout
J8 J10
Name Pin # Pin # Name Name Pin # Pin # Name
GND 1 2 Y0 GND 1 2 UV0
GND 3 4 Y1 GND 3 4 UV1
GND 5 6 Y2 GND 5 6 UV2
GND 7 8 Y3 GND 7 8 UV3
GND 9 10 Y4 GND 9 10 UV4
GND 11 12 Y5 GND 11 12 UV5
GND 13 14 Y6 GND 13 14 UV6
GND 15 16 Y7 GND 15 16 UV7
GND 17 18 HREF GND 17 18 SDA
GND 19 20 VREF GND 19 20 SCL
GND 21 22 LLC2 GND 21 22 NC
GND 23 24 GND GND 23 24 NC
GND 25 26 NC GND 25 26 NC
J9
Name Pin # Pin # Name
GND 1 2 +5V
GND 3 4 +5V
GND 5 6 +12V
GND 7 8 +12V
GND 9 10 -12V
C-GND 11 12 -12V

DKHiQV-AGP (Fab. Rev. A) User’s Guide 10
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.4.3 MPEG and ZV Port Connector
The DKHiQV-AGP board also provides another connector for YUV video interface. The J7 connector re-
ceives YUV data from an MPEG or PCMCIA ZV interface card.
Figure 4 shows the MPEG ZV port pinout:
Fi
g
ure 4: MPEG Video In Connector
Name Pin # Pin # Name
GND 1 2 Y0
GND 3 4 Y1
GND 5 6 Y2
GND 7 8 Y3
GND 9 10 Y4
GND 11 12 Y5
GND 13 14 Y6
GND 15 16 Y7
GND 17 18 UV1
GND 19 20 UV2
GND 21 22 UV3
GND 23 24 UV3
GND 25 26 UV4
GND 27 28 UV5
GND 29 30 UV6
GND 31 32 UV7
GND 33 34 HREF
GND 35 36 VREF
GND 37 38 LLC2
GND 39 40 GND

11 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.5 Mixed Voltage Generation and Power Measurement
The DKHiQV-AGP board has jumpers to choose different supply voltages for each block of the video sub-
system. The voltages chosen could be 5V from the bus, 3.3V from the bus or a voltage from an onboard
voltage regulator. The latter voltage is adjustable by resistor pots, except for the internal clock power sup-
ply. HiQVideocontrollers provide an easy and accurate way to measure the power dissipation of the var-
ious blocks of the video subsystem.
Table 3 describes the various blocks of the video subsystem supplied by individually configurable voltages,
as well as where to measure these voltages and the power dissipation (current) for each block.
Table 3: Video Sub-S
y
stem Volta
g
es
Example: To measure the power consumed by the internal DAC of the 69000, replace the W27 jumper plug
with an ammeter. The desired voltage may be measured at W27 pin 2.
3.6 Power Sequencing and Backlight Control
Flat panel dialyses are extremely sensitive to conditions where full biasing voltage VEESAFE is applied to
the liquid crystal material without enabling the control and data signals to the panel.
The DKHiQV-AGP board provides three controlled voltages: VDDSAFE (VDD) for driver electronics, VEE-
SAFE (VEE) for LCD bias and +12VSAFE (BACKLIGHT) for easy access for most panels. The power se-
quencing control signals ENAVEE, ENAVDD and ENABKL regulate application of bias voltage and +5V to
the panel and +12V to the inverter for backlight operation.
DKHiQV-AGP
Voltage Name Blocks of Video Sub-system Supplied by the Voltage Voltage Measurement Point Current Measurement Point
GVCC BIOS, Video encoder di
g
ital Vcc SH5 SH5
AVCC Video encoder analo
g
Vcc SH5 FB10
XVCC55X Video capture port W34, pin 2 W34
BVCC55X Bus interface W33, pin 2 W33
RAMVCC DRAM W32, pin 2 W32
MVCC55X Memory lo
g
ic W31, pin 2 W31
DVCC55X Panel interface W30, pin 2 W30
IVCC55X Internal lo
g
ic W28, pin 2 W28
AVCC55X Internal DAC W27, pin 2 W27
OSCVCC External oscillator W26, pin 2 W26
69000
Voltage Name Blocks of Video Sub-system Supplied by the Voltage Voltage Measurement Point Current Measurement Point
VVCC55X Video interface W34, pin 2 W34
CVCC55X CRT interface W36, pin 2 W36
PVCC Internal clock synthesizer power 0 W24, pin 2 SH7
SVCC Internal clock synthesizer power 1 W24, pin 2 SH6

DKHiQV-AGP (Fab. Rev. A) User’s Guide 12
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.7 VEESAFE for Panel Operation
3.7.1 Low Voltage for Panel Operation
A new jumper (W39) has been added to allow VEESAFE to be driven by a scaled version of VDDSAFE for
newer panels that have a low voltage requirement for VEESAFE.
W39 = 1-2 VEESAFE is controlled by R28 (potentiometer)
W39 = 2-3 VEESAFE is controlled by W21
It is important for R28 to be fed from VDDSAFE rather than some other voltage source, so that the resulting
VEESAFE will meet the same power sequencing requirements as the panel. The sequencing ofVEESAFE
will be the same as forVDDSAFEwhen the R28 option is selected. The current requirement for low-voltage
VEESAFE is intended to be 1mA max.
3.7.2 High Voltage Operation for VEESAFE
If W39 = 2-3 is selected, the on-board DC-to-DC converter will provide a controllable DC voltage (LCD bias
voltage) for most panels. The voltage range is -12 to -45VDC (Negative) or +12 to +45VDC (Positive). To
receive a (-VEE) voltage in the range of -12 to -45 volts, adjust resistor pot R59. Measure the voltage at
W21 Terminal 1. Place a jumper on W21(1-2). To get a positive (+VEE) voltage in the range of +12 to +45
volts, adjust the resistor pot R59 and measure the voltage at W21 Terminal 3. Place a jumper on W21 (2-
3). Remove power from the system. Hook up the panel to the panel connectors. Turn on the power. This
may lower the voltage at W21 because of the voltage drop caused by the panel load. Adjust pot R59 again
for proper panel voltage. The voltage VEESAFE atW21(+VEE or -VEE) may be generated by the formula:
R64 = (R66 + R59) * {VEESAFE ÷1.31)-1}
WARNING:Improper use of the DC-to-DC converter may cause damage to the panel.
3.8 3DQHO/LQN and LVDS Interfaces
The DK board allows a 3DQHO/LQN or LVDS transmitter adapter card to be installed in the panel connector
(J5). Various jumper options allow flexible selection of 3.3V or 5V power for the adapter card as well as a
PCLK option for STN-DD panel support via PanelLink or LVDS interface.
3.8.1 PCLK for 3DQHO/LQN STN-DD Support
If the 3DQHO/LQN interface is operated at 3.3V as described below there may be a problem with the PCLK
voltage level. Ideally, PCLK should be reduced to 3.3V but this may not be feasible because of the video
capture VCC requirements (with the ABHiQV daughtercard, XVCC55X on the main DK board provides the
VCC power for the video capture as well as PCLK). A possible solution for PCLK may be to add a 1KΩ
resistor in series with PCLK as close to the 3DQHO/LQN clock input as possible to limit the current that might
otherwise flow when a 5V PCLK signal drives a 3.3V 3DQHO/LQN clock input. This solution has not yet been
characterized or tested. The PCLK voltage level is not an issue when using a TFT panel since SHFCLK is
used for the 3DQHO/LQN in that case.

13 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
3.8.2 Clean 3.3V Power for the 3DQHO/LQN Transmitter
JP4 allows 3.3V to be supplied to the 3DQHO/LQN transmitter and receiver cards from the 3V regulator U13
(Voltage adjusted by R75). JP4 also allows 5V to be used instead for other types of interfaces such as 5V
LVDS. For 3DQHO/LQN operation, only the 3DQHO/LQN transmitter and receiver cards should be powered
from this regulator (via JP4), and the voltage should be set to 3.3V (within 5%). In addition, the DVCC55X
voltage should also be set for 3.3V,from U15 via W35 and W30. Anyother 3.3V voltages used inthe system
(except for the 3DQHO/LQN interface) should also come from the U15 regulator. The reason for separating
the 3DQHO/LQN voltage from the other loads is to provide a veryclean 3.3V source to the 3DQHO/LQN chips.
This is most important at XGA frequencies (65 MHz).
4.0 Installation Procedures
1. Unpack the DKHiQV-AGP (Fab Rev. A) board and visually inspect for any damage that may have
occurred during shipping.
2. Read this DKHiQV-AGP (Fab Rev. A) User’s Guide to become familiar with the board operations.
3. Read the ABHiQV (Fab. Rev. B) daughtercard User’s Guide and schematics to become familiar
with board operations.
4. Read the MM6555x (Fab. Rev. B) Multimedia Daughtercard User’s Guide to become familiar with
board operations.
5. Check that all jumpers are in their default positions as shown in Tables 8 through 11. Refer to Fig-
ures 1 and 2 for jumper locations.
Note: For TV out and multimedia settings, refer to Tables 12 and 13.
6. Plug the ABHiQV (Fab Rev. B) daughtercard onto the DKHiQV-AGP board. The connectors/head-
er in the ABHiQV daughtercard is composed of eight 2X16 header-socket-type pins (P1).
7. Power down the host system and plug the DKHiQV-AGP board into an available AGP slot on the
motherboard.
Please note that the DK-HiQV-AGP board does not plug into ISA, VL-bus or PCI-bus.
8. Connect the monitor to the 15-pin VGA connector. The default configuration of the DK board is for
CRT display.
9. Turn on the system power and observe the sign-on message. The sign-on message does not ap-
pear, turn off the system power and follow the instructions in the troubleshooting section of this Us-
er’s Guide.
10. Load the proper driver, BIOS and utilities to activate the ABHiQV daughtercard.
4.1 HiQVideo Utilities and Drivers
The SETCLK utility included in the utilities diskette independently programs MCLK and DCLK of the HiQVid-
eocontroller. The diskette also provides other utilities such as MODETEST. The MODETEST utility runs
through all the standard VGA modes and super VGA modes. The driver diskettes also contain high perfor-
mance display drivers for Windows95. WindowsNT drivers (and other files and utilities) are available on our
BBS (bbs.chips.com) for your use. The diskette also contains text files to help you install these drivers.

DKHiQV-AGP (Fab. Rev. A) User’s Guide 14
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
5.0 DKHiQV - AGP Board Configuration Guide
5.1 DKHiQV - AGP Board Component Layout
Fi
g
ure 5: DKHiQV-AGP Board Component La
y
out
STANDBY
J4 Video
J3 CMPS
Video
J1 S Video
W1
J2 Access Bus
JP1 JP2 JP3
W40
W8
W7
W9
W6
W5
W3
W4
JP10
JP5
JP11
JP9
JP7
JP8
JP6
JP12
JP13
W37
W36
JP4
W21
W39
W38
J5 Panel Connection
J10 J8 J9
W23
J7 MPEG Connection
J11 Panel Conn. II
R76
R75
W35
SH4
W34
W32
W33
W31
W30
W29
W28
W27
SH6
SH5
SH7
W24
W25
W26
R59
R82
W10
W12
W13
W14
W15
W16
W17
W18
W19
W20
JP19
JP15
JP16
JP18
JP20
JP17

15 DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice Revision 1.0 7/13/98
5.2 DKHiQV - AGP Demo Connector Description
Table 4 below identifies the function of the twelve different connectors on the DKHiQV-AGP board. Refer
to Figure 5.
Table 4: DKHiQV-AGP Board Connector Functions
Connectors Function
J1 SVIDEO Video connector
J2 Access Bus
J3 RCA jack, composite video out
J4 15-pin VGA connector
J5 50-pin panel connector
J7 MPEG video in connector
J8, J9, J10 Multimedia card connector
J11 P30-35 Panel data for 36-bit panels
P1 AGP Bus ed
g
e connector