LeCroy 1881M User manual

MODEL 1881M
64 CHANNEL FASTBUS ADC

CAUTION
Cooling
It is imperative that the module 1881M ADC be well cooled. Be sure fans move sufficient air to maintain
exhaust air temperature at less than 50_C.
Installation
"Hot" insertion (insertion with crate power turned on) of modules is supported in accordance with the
FASTBUS specification.
Specifications
The information contained in this manual is subject to change without notice. The reference for product
specification is the Technical Data Sheet effective at the time of purchase.
Electrostatic Sensitivity
While measures have been taken to protect the MTD133 ASIC from electrostatic damage, it is still
imperative to follow anti static procedures when handling this CMOS device. Removal of the MTD133
from its socket will void the product warranty.

Table of Contents
iJuly 23, 1998
Table of Contents
1. ......................................................................................................................................0-iii
1. General Information............................................................................................................1-1
1.1 Purpose..............................................................................................................1-1
1.2 Unpacking and Inspection......................................................................................1-1
1.3 Warranty............................................................................................................1-1
1.4 Product Assistance...............................................................................................1-1
1.5 Maintenance Agreements.......................................................................................1-1
1.6 Documentation Discrepancies.................................................................................1-2
1.7 Software Licensing Agreement................................................................................1-2
1.8 Service Procedure.................................................................................................1-2
2. ......................................................................................................................................1-2
2. Product Description...........................................................................................................2-1
2.1 Introduction........................................................................................................2-1
2.2 General Description..............................................................................................2-1
2.3 Specifications......................................................................................................2-2
2.4 Front Panel.........................................................................................................2-2
2.4.1 Displays..............................................................................................2-2
2.4.2 Inputs.................................................................................................2-2
2.4.3 Outputs...............................................................................................2-3
2.5 Control and Status Registers..................................................................................2-3
2.5.1 Control and Status Register 0..................................................................2-3
2.5.2 Control and Status Register 1..................................................................2-6
2.5.3 Control and Status Register 3..................................................................2-7
2.5.4 Control and Status Register 5..................................................................2-7
2.5.5 Control and Status Register 7..................................................................2-7
2.5.6 Control and Status Register 16................................................................2-7
2.5.7 Control and Status Register C000000h - C000003Fh ..................................2-8
2.6 FASTBUS Operations..........................................................................................2-8
2.6.1 FASTBUS Address cycle.......................................................................2-8
2.6.1.1 Logical Addressing.................................................................2-8
2.6.1.2 Geographic Addressing............................................................2-8
2.6.1.3 Broadcast Addressing..............................................................2-8
2.7 Data Space..........................................................................................................2-9
2.7.1 Header Word Format.............................................................................2-10
2.7.2 Data Word Format................................................................................2-10
2.8 Readout.............................................................................................................2-11
2.8.1 Single Read from Data Space...................................................................2-11
2.8.2 Block Transfer Read from Data Space........................................................2-11
2.9 FASTBUS Write to Data Memory.........................................................................2-11
2.10 Fast Clears........................................................................................................2-11
2.11 Allocation of Restricted Use Lines.........................................................................2-11
2.12 Example Code...................................................................................................2-12
3. ......................................................................................................................................2-14
3. Installation.......................................................................................................................3-1
3.1 General Installation..............................................................................................3-1
3.1.1 Cables.................................................................................................3-1
3.1.2 Input options........................................................................................3-2
4. ......................................................................................................................................3-3
4. Operating Instructions........................................................................................................4-1
4.1 General Operation................................................................................................4-1
4.1.1 Overview.............................................................................................4-1
4.1.2 Setup..................................................................................................4-1
4.1.3 Acquisition..........................................................................................4-1
4.1.4 Buffering and Readout............................................................................4-1
4.1.5 Read and Write Pointers.........................................................................4-1
4.1.6 FASTBUS Control...............................................................................4-2
4.1.7 Memory Test Mode...............................................................................4-2

Table of Contents
July 23, 1998 ii
4.1.8 Re-reading Events.................................................................................4-2
4.1.9 Readout During Conversion....................................................................4-3
4.1.10 FASTBUS Write to Data Memory.........................................................4-3
4.1.11 Fast Clears.........................................................................................4-3
4.1.12 Internal Tester.....................................................................................4-3
5. Theory of Operation...........................................................................................................5-1
5.1 General Description of Buffer Architecture.................................................................5-1
5.1.1 Multi-Event Buffer Memory Organization..................................................5-1
5.1.2 Buffer Memory Pointers..........................................................................5-1
5.1.3 Buffer Full/Empty Conditions.................................................................5-2
5.2 Acquisition and Buffering......................................................................................5-2
5.2.1 Readout of MTDs.................................................................................5-4
5.2.2 Organization of Data in Events.................................................................5-4
5.3 FASTBUS Access to Module................................................................................5-4
5.3.1 Control and Status Registers...................................................................5-4
5.3.2 Secondary Addressing in Data Space.........................................................5-5
5.3.2.1 Default Addressing Mode.........................................................5-5
5.3.2.2 Memory Test Mode (MTM).....................................................5-5
5.4 Mechanisms for FASTBUS Readout.......................................................................5-6
5.4.1 Load Next Event...................................................................................5-6
5.4.2 Block Transfers from Data Space..............................................................5-6
5.4.3 Multi-Module Data Transfers (Multi-Block)...............................................5-7
6. Index...............................................................................................................................6-1

Table of Contents
iii July 23, 1998
List of Figures
2-2. CSR0 Write Bit Definition...............................................................................................2-4
2-3. CSR1 Bit Definition.......................................................................................................2-6
2-4. CSR16 Bit Definition......................................................................................................2-7
2-5. Header word Format........................................................................................................2-10
5-1. Simplified 1881M Interface/Buffer Block Diagram................................................................5-1
5-2. 1881M Circular Buffer.....................................................................................................5-2

1881M General Information
1-1 July 23, 1998
1. General Information
1.1 Purpose
This manual is intended to provide instruction regarding the setup and operation of the LeCroy Model
1881M Analog to Digital Converter. In addition, it describes the converter's theory of operation and
presents information regarding its function and application.
1.2 Unpacking and Inspection
It is recommended that the shipment be thoroughly inspected immediately upon delivery. All material in
the container should be checked against the enclosed Packing List and shortages reported promptly. If the
shipment is damaged in any way, please notify the Customer Service Department or the local field service
office. If the damage is due to mishandling during shipment, you may be requested to assist in contacting
the carrier in filing a damage claim.
1.3 Warranty
LeCroy warrants its instrument products to operate within specifications under normal use and service for a
period of one year from the date of shipment. Component products, replacement parts, and repairs are
warranted for 90 days. This warranty extends only to the original purchaser. Software is thoroughly
tested, but is supplied "as is" with no warranty of any kind covering detailed performance. Accessory
products not manufactured by LeCroy are covered by the original equipment manufacturers' warranty only.
In exercising this warranty, LeCroy will repair or, at its option, replace any product returned to the
Customer Service Department or an authorized service facility within the warranty period, provided that the
warrantor's examination discloses that the product is defective due to workmanship or materials and has not
been caused by misuse, neglect, accident or abnormal conditions or operations.
The purchaser is responsible for the transportation and insurance charges arising from the return of products
to the servicing facility. LeCroy will return all in-warranty products with transportation prepaid.
This warranty is in lieu of all other warranties, express or implied, including but not limited to any
implied warranty of merchantability, fitness, or adequacy for any particular purpose or use. LeCroy shall
not be liable for any special, incidental, or consequential damages, whether in contract, or otherwise.
1.4 Product Assistance
Answers to questions concerning installation, calibration, and use of LeCroy equipment are available from
the Customer Service Department, 700 Chestnut Ridge Road, Chestnut Ridge, New York, 10977-6499,
[phone], or your local field service office.
1.5 Maintenance Agreements
LeCroy offers a selection of customer support services. For example, Maintenance Agreements provide
extended warranty that allows the customer to budget maintenance costs after the initial warranty has
expired. Other services such as installation, training, on-site repair, and addition of engineering
improvements are available through specific Supplemental Support Agreements. Please contact the
Customer Service Department or the local field service office for details.

General Information 1881M
July 23, 1998 1-2
1.6 Documentation Discrepancies
LeCroy is committed to providing state-of-the-art instrumentation and is continually refining and
improving the performance of its products. While physical modifications can be implemented quite
rapidly, the corrected documentation frequently requires more time to produce. Consequently, this manual
may not agree in every detail with the accompanying product and the schematics in the Service
Documentation. There may be small discrepancies in the values of components for the purposes of pulse
shape, timing, offset, etc., and, occasionally, minor logic changes. Where any such inconsistencies exist,
please be assured that the unit is correct and incorporates the most up-to-date circuitry.
1.7 Software Licensing Agreement
Software products are licensed for a single machine. Under this license you may:
•Copy the software for backup or modification purposes in support of your use of the software on a
single machine.
•Modify the software and/or merge it into another program for your use on a single machine.
•Transfer the software and the license to another party if the other party accepts the terms of this
agreement and you relinquish all copies, whether in printed or machine readable form, including
all modified or merged versions.
1.8 Service Procedure
Products requiring maintenance should be returned to the Customer Service Department or authorized
service facility. If under warranty, LeCroy will repair or replace the product at no charge. The purchaser is
only responsible for the transportation charges arising from return of the goods to the service facility. For
all LeCroy products in need of repair after the warranty period, the customer must provide a Purchase Order
Number before any inoperative equipment can be repaired or replaced. The customer will be billed for the
parts and labor for the repair as well as for shipping. All products returned for repair should be identified by
the model and serial numbers and include a description of the defect or failure, name and phone number of
the user. In the case of products returned, a Return Authorization Number is required and may be obtained
by contacting the Customer Service Department in your area.

1881M Product Description
2-1 July 23, 1998
2. Product Description
2.1 Introduction
The LeCroy Model 1881M provides 64 channels of analog to digital conversion in the FASTBUS format.
It is designed for elementary particle and nuclear physics experiments and was developed to meet the fast
conversion time needs of modern experiments. Its conversion time is well matched with that of the 1872A,
1876, and 1877 Time to Digital converters for very fast total system throughput. The 1881M is also
compatible with the LeCroy 1810 Calibration and Timing (CAT) module to simplify the implementation
of multiple module systems. The measurement in the 1881M is performed using the MTD133 and the
MQT200S, full custom ASICs developed by LeCroy Corporation.
2.2 General Description
The 1881M Analog to Digital Converter offers all the flexibility of the 1880 series Analog to Digital
converters, but with an approximately 12 µs conversion time for all 64 channels. It has 50 fC least count
with a full 13 bits of dynamic range above pedestal for each channel. Permissible gate widths may vary
from 50 to 500 ns. Each 1881M has 64 channels of front panel input and a single gate input. Events are
stored in an on-board sixty four event cyclic buffer memory. A threshold memory permits the loading of a
separate constant for each channel, which is used to suppress unwanted data. Both front panel control
inputs are differential ECL (dECL) and are terminated by a balanced 102 Ωimpedance matching network.
The terminations may be disconnected using jumpers to allow daisy chaining of modules.
Operation of the 1881M can be thought of in four phases: programming, acquisition, conversion, and
readout. Once the control and status registers have been properly programmed, the module is in acquisition
mode and ready to accept a gate pulse. The duration of the gate pulse defines the acquisition phase. The
gate may be provided either via a front panel dECL input, via the 1810 CAT module, or a nominal 500 ns
pulse triggered by a write to CSR0 <7>. For the duration of this gate signal, each of the 64 individual
inputs integrate the charge applied to them. Immediately following this acquisition phase, the data is
converted to a digital representation and then placed in a multi-event buffer to await readout. If
sparsification is selected, data is discarded from channels that are below their individual thresholds. The
data is thus 'sparsified' (also known as zero suppression), so that signals on the front end inputs less than
the programmed threshold values are not buffered. Using this method, it is not necessary to transmit
unwanted data over FASTBUS.
A fast clear may be applied to the module any time from 100ns after the end of the gate until the end of the
Fast Clear Window (FCW). If a fast clear is applied during this period, the event currently being converted
will be discarded. It is important to realize that setting the FCW to longer than 10 µs will increase the
conversion time of the module to FCW + 1us. If an external FCW is selected from the CAT of less than
10µs from the end of the gate, then a FCW will cause an internal FCW of 11 µs with a corresponding
conversion time of 12 us. There is no restriction within the 1881M of the maximum FCW that may be
applied externally. Clears should not be applied outside of the fast clear window.
The data of the 1881M is stored as a 32 bit word, each of which contains charge data, channel number, the
geographic address and a word parity bit. The functionality of the 1881M can be tested using the internal
tester in conjunction with a 1810 CAT module. The module does not provide any trigger outputs.

Product Description 1881M
July 23, 1998 2-2
2.3 Specifications
Please refer to the model 1881M technical data sheet for a complete summary of all relevant specifications.
2.4 Front Panel
The LeCroy Module 1881M ADC front panel provides the user with connectors for easy system integration
and LEDs to indicate status. Cables necessary for proper installation can be purchased from LeCroy. See
Section 3.1 for more information regarding cabling.
2.4.1 Displays
Two colored LEDs exist on the front panel of the 1881M to indicate the status of operations. The LED
outputs are pulse stretched for visibility.
•Slave Addressed LED: As per the FASTBUS specification, this yellow LED is lit whenever the ADC
module is address locked by either direct addressing or a broadcast operation.
•GATE LED: This green LED is illuminated whenever the ADC registers a gate. The gate may come
via the front panel input marked Gate, from the 1810 CAT module, or from a write to CSR0 <7>.
2.4.2 Inputs
All analog inputs are received via four 34 pin connectors. A 3M connector type 3414-6034 or a LeCroy
connector part number 403 220 034 with pull tab part number 403 910 034 will mate with the ADC header
and provide strain relief. The bottom two pins of each of the four headers are connected to the clean analog
ground within the module. The analog inputs are numbered from top to bottom in ascending order.
•IN: 64 inputs are used to receive individual channel signals. It is recommended that the source's output
DC impedance exceed 1 KΩfor each of these signals to avoid excessive pedestal spread and degraded
temperature performance. The inputs may be configured in several different modes. These include 50 Ω
single ended, 100 Ωdifferential, and 100 Ωpseudo-differential. It is important to verify the jumper
links are correctly configured. See Section 3.1.2 for Input options
All front-panel control inputs to the 1881M are differential ECL compatible with the ECLine standard.
Each pair of differential inputs is terminated with an effective 102 Ω. Two control inputs are differentially
received via a 6 pin header located at the bottom of the front panel.
The control signals can be connected by single pair headers AMP part number 5-87456-2. A brief
description of each input follows below:
•CLR: A dECL input used to issue fast clears to the module. A clear pulse can be issued at any time
during the FCW provided it is at least 100 ns wide. When a clear is issued, the data of the current
event is cleared and the module returns to acquisition mode after a delay equal to the fast clear time
beyond the trailing edge of the pulse. The control and status registers are not affected by a clear. This
signal may also be applied by writing CSR0<31> or from the 1810 CAT via TR0. Note all the clear
sources are simply OR'ed.
•GATE: A front panel dECL input which receives the gate input pulse. This signal defines the time
during which charge will be integrated on each of the 64 IN inputs. The gate pulse may also be applied
from the 1810 CAT module via TR6 on FASTBUS. The source is selected using CSR1 <1>. The
test gate is generated by a write to CSR0<7>. It is OR’ed with the selected source. It should be
noted that if the selected gate source is high this will cause internal gates not to function.

1881M Product Description
2-3 July 23, 1998
2.4.3 Outputs
The front panel CIP (Conversion in Progress) output from the 1881M is differential ECL compatible with
the ECLine standard. Each of differential outputs is pulled down with 300 Ωto -5.2 V. If the CIP signal is
used, it should be terminated at the receiving end in 100 Ω. The best method of doing this is to connect
two 51 Ωresistors in series across the signal at the receiver and connect the center tap via a 0.1 µF
capacitor to ground. If LeCroy ECL line products are used to receive the signal the termination is already
included internally. Differential ECL cannot be Wire OR’ed.
•CIP: Conversion in Progress (CIP) is a single dECL signal provided to aid in the gating logic. While
CIP is true, the unit is not capable of accepting a new gate. It should be noted that if an extended
FCW is used this will delay the end of CIP. It is the users responsibility to ensure that GATEs are
NOT issued during CIP.
2.5 Control and Status Registers
Seventy control and status registers (CSR) are implemented in the 1881M: CSR0, CSR1, CSR3, CSR5,
CSR7, CSR16, and CSRC0000000h- C000003Fh.
2.5.1 Control and Status Register 0
Functions necessary even for the simplest of operations are contained in CSR0. In order to implement these
functions most economically, the definition of the bits for CSR0 are not the same for Read and Write
operations. Some bits are inherently meaningful only for write operations, because their status can only be
altered by writing to another bit in the register. Other bits, such as the module identification bits, are only
meaningful for read operations. When read, the 1881M presents 104Fh on the Address/Data bus lines 16-31
as its manufacturer's identification. CSR0 is the default register when a primary address to control space is
issued. See section 2.6.1 for more information regarding addressing. See Figures 2-1 and 2-2 for individual
bit definitions.
Figure 2-1 CSR0 Read Bit Definition
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR 0 READ BIT DEFINITIONS
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 00 0 011001 X
LOGICAL ADDRESSING ENABLED
1881M MODULE IDENTIFICATION - 104F
X - USED BITS
* - UNUSED BITS
BYTE 3 BYTE 2 BYTE 1 BYTE 0
MULTIBLOCK CONFIGURATION
00 - BYPASS
01 - PRIMARY LINK
10 - END LINK
11 - MIDDLE LINK
0
MEMORY TEST MODE ENABLED
0 X XX X
CSR0 POWER-UP OR MASTER RESET STATE: 0x104F0000
1

Product Description 1881M
July 23, 1998 2-4
Figure 2-2 CSR0 Write Bit Definition
CSR0 After Master Reset or Power-up - 104F0000 h
•FAST CLEAR: abort conversion and buffering of the last event. The preferred method of clearing the
unit is via a CAT or front panel input as the FAST CLEAR must occur during the FCW which is
difficult to guarantee if carried out over FASTBUS.
•MASTER RESET: Returns the module to its power-up configuration. All CSR’s are returned to
their power-up states. This is the easiest method of resetting all the output buffers in a crate if the
system goes out of step.
•CONFIGURE MULTIBLOCK: If either of these bits are set, when accessing the unit all data space
block transfers must be done as part of a multi-block scan. The board in the highest numbered slot
should be programmed as the primary link. The board in the lowest number slot should be
programmed as the end link. The boards in between should be programmed as middle links. The
board set must contiguous. It is acceptable but not recommended (due to increased module to module
token pass time in multi-block block transfers) to have non participating boards in the block
providing they are either multi-block compatible and set to bypass or have their daisy chain lines
connected through. This can be useful during diagnostics of the data acquisition system. Priming on
LNE (CSR0<8>) must be enabled when the module is participating in a MDT (Multi-Block) scan.
Failure to do so will result in the module responding to the transfer with SS=3, the MDT error
response
•LOAD NEXT EVENT: Advances Read pointer (this is the data space NTA when MTM is set) to
first location of next event, then copies word count from header word of that event to CSR5. This
makes the 1881M ready for a block transfer to readout one entire event.
•ENABLE PRIMING ON LNE: Enables the first two stages of the internal data pipeline to be primed
when a Load Next Event is issued. This will reduce the token pass time in multi-block scans. This Is
not recommended in MTM mode as it makes the understanding of NTA behavior complicated.
Priming on LNE must be enabled when the module is participating in a MDT (Multi-Block) scan.
Failure to do so will result in the module responding to the transfer with SS=3, the MDT error
response.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR 0 WRITE BIT DEFINITIONS
X
X - USED BITS
* - UNUSED BITS
X X* X ** * X X * * *X * * X XX X X
MASTER RESET - PULSE
FAST CLEAR - PULSE
LOAD NEXT EVENT - PULSE
TRIGGER TEST GATE - PULSE
ENABLE LOGICAL ADDRESS
BYTE 3 BYTE 2 BYTE 1 BYTE 0
XX X
CONFIGURE MULTIBLOCK
00 - BYPASS
01 - PRIMARY LINK
10 - END LINK
11 - MIDDLE LINK
**X
ENABLE MEMORY TEST MODE
*** X X
ENABLE GATE
ENABLE PRIMING ON LNE

1881M Product Description
2-5 July 23, 1998
•TEST GATE: A write to this bit is intended only for confidence testing and will generate a
nominally 500 ns gate pulse. The enable test pulse bit CSR1 <29> must be set if a programmable
amplitude test pulse is desired.
•MTM : Memory test mode allows the direct addressing of the buffer memory using the data space
NTA (normally writes to data space NTA are ignored.). When this bit is clear the 1881M acts as a
FIFO (First In First Out) from DSR0.
•GATE ENABLE : This bit must be set to enable the module for data acquisition.
•ENABLE LOGICAL ADDRESS: This bit must be set for the module to respond to the logical
address as stored in CSR3. This bit also selects which address is included in the data header word.

Product Description 1881M
July 23, 1998 2-6
2.5.2 Control and Status Register 1
The acquisition configuration of the module is primarily defined in CSR1.
Figure 2-3 CSR1 Bit Definition
•ENABLE SPARSIFICATION : Setting this bit causes data values which are less than the threshold
for the corresponding channels to be discarded during conversion. Only those data values which exceed
their respective thresholds are written to the buffer. CSRC0000000 h - CSRC0000003F h contain the
thresholds for channels 0 - 63 respectively. If this bit is reset (the power up state) the unit will always
readout 64 channels.
•ENABLE INTERNAL TESTER : This bit must be set for the internal tester to be operative. If set, a
level on UR0 and UR1, normally provided by the 1810 CAT will determine the amplitude of a test
pulse applied to all channels. The test pulse may be software triggered or external but should be
approximately 500ns in duration.
•FAST CLEAR WINDOW: Bits <27:24> determine the length of time the on-board timer permits the
user to issue a fast clear to the module after the end of acquisition. The fast clear window begins
immediately following the end of the gate . For the on-board FCW to be used the 1810 CAT FCW
must be disabled ( CSR1 <2> = 0 ). Once the fast clear window has ended, the current event is placed
in the multiple event buffer and must either be read out or skipped. When read, the status of the bits is
presented. +
a
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR 1 BIT DEFINITIONS
X X
X - USED BITS
* - UNUSED BITS
0 00 X0 00 X X X0 X X
BYTE 3 BYTE 2 BYTE 1 BYTE 0
X X X X 0 00 0 0 0 X
ENABLE SPARSIFICATION
ENABLE INTERNAL TESTER
FAST CLEAR WINDOW
0000 2.05us 1000 18.4us
0001 4.10us 1001 20.5us
0010 6.14us 1010 22.5us
0011 8.19us 1011 24.6us
0100 10.2us 1100 26.6us
0101 12.3us 1101 28.7us
110122131072ns
0110 14.3us 1110 30.7us
0111 16.4us 1111 32.8us
524280ns
ENABLE FC FROM TR5 (CAT)
ENABLE FCW FROM TR5 (CAT)
ENABLE GATE FROM TR6 (CAT)
ENABLE CIP TO TR7
0 00 0*0
CSR1 POWER-UP OR MASTER RESET STATE: 0x0000040
CONVERSION MODE
00 reserved
01 13 bit
10 12 bit
11 reserved
Overrun detect disable

1881M Product Description
2-7 July 23, 1998
•OVERUN DETECT DISABLE: In normal operating modes this bit should NOT be set. When set the
unit will allow the 1881M to overrun. The FULL condition will not prevent further gates and the unit
will cycle from FULL to empty continually. The only purpose of this bit is during setup, when the
readout electronics is not operating and it is desired to setup the trigger with an oscilloscope. When
this bit is reset the front end does not provide a true veto so the experimenter must veto gates with
CIP to prevent half width gates breaking through as CIP finishes.
After Master Reset or Power-up, CSR1 defaults to 00000040 h (13 bit 50fC mode).
2.5.3 Control and Status Register 3
As per FASTBUS specification, CSR3 is used to store the desired logical address for the unit.
CSR3<31:16> contain the logical address. This register powers up to 0 and is not disturbed by a master
reset, CSR0<30>. CSR3<15:0> are ignored on write and always readback as zero.
2.5.4 Control and Status Register 5
CSR5 is implemented as a 7 bit read/write register used to control the number of words transferred during a
block transfer. It is decremented after each transfer, during a FASTBUS readout. After a Load Next Event
command has been issued, CSR5 is automatically loaded with the word count for the next event to be read
out. Only bits 0 through 6 are meaningful. Bits <31:7> will read back as 0. CSR5 is set to 00000000 h
by a Master Reset.
2.5.5 Control and Status Register 7
CSR7 is used to specify the broadcast classes to which an 1881M will respond. It is implemented as a 4
bit read/write register. Bits 3 through 0 correspond to broadcast classes 3 through 0 respectively. If bit N
is set, the 1881M will be selected by a broadcast to class N devices. CSR7 is not affected by Master
Reset. The unit will always ignore broadcasts to groups 4-7.
2.5.6 Control and Status Register 16
CSR16 is implemented as a 16 bit read-write register used to indicate and control the location of the read
and the write buffer addresses. CSR16 <13:8> indicate the next buffer to be readout, and CSR16 <5:0>
indicate the next buffer address to be filled. Master Reset and Power-up reset CSR16 to 00003F00 h.
Unused bits always read back as zero.
Figure 2-4 CSR16 Bit Definition
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR 16 BIT DEFINITIONS
X - USED BITS
* - UNUSED BITS
BYTE 3 BYTE 2 BYTE 1 BYTE 0
0 0 0 0 X X X0 0 0 0 0 0 0 0 0 0 0 0 X X X
0 0 X X 0 0 X X
READ BUFFER WRITE BUFFER
X X
CSR16 POWER-UP OR MASTER RESET STATE: 0x00003F00

Product Description 1881M
July 23, 1998 2-8
2.5.7 Control and Status Register C000000h - C000003Fh
These 64 read/write registers are used to program the threshold settings for each of the input channels. If
during buffering a given channel's data value is less than its threshold setting, that data will not be buffered.
The threshold is NOT subtracted from the data written into the buffer. The threshold value RAM is 13 bits
wide and is accessed via the low 13 bits of CSRC0000000h- C0000003Fh. The upper 16 bits will be
ignored on write and always read back as zero. These CSR's are NOT cleared by power-up or Master
Reset. Setting bits 12 and 13 of a threshold will disable the channel completely
2.6 FASTBUS Operations
2.6.1 FASTBUS Address cycle
The 1881M ADC responds to geographical, logical and broadcast addressing.
2.6.1.1 Logical Addressing
CSR3<31:16 > contain the logical address to which the 1881M will respond in both CSR Space and Data
Space.
2.6.1.2 Geographic Addressing
The model 1881M responds to geographical addressing in both CSR space and Data Space.
2.6.1.3 Broadcast Addressing
The following is a list of Broadcast operations responded to by the 1881M. The case numbers are from the
IEEE 960-1989 FASTBUS specification, Table 4.3.2. Example address use G=0 and L=1 for broadcasts
on the local FASTBUS segment only.
•Case 1: General Broadcast. 00000001h. All devices respond to subsequent data cycles.
•Case 2: 00000005 h . Only devices of class N respond to subsequent data cycles.
•Case 3: Sparse Data Scan : 00000009h Devices respond by asserting T-Pin during following read
cycle if data present.
•Case 3a: Sparse Data Scan: 00000019 h. Devices respond by asserting T-Pin if they contain no
data or are available for use.
•Case 4: 0000000D. Devices respond by asserting T-Pin during following read cycle.
•Case 8-B: 000000BD h. Identical to the case 3 scan above except it is specific to LeCroy ADC’s.
•Case 8-C: 000000CD h. 1881M ADCs respond by asserting T-Pin during following read cycle if
unsuppressed data is present in the next buffer.
CSR7<3:0 > controls the classes of class N broadcast to which the 1881M will respond in both Data and
CSR Spaces.
Important note: In some rare cases, the module will not be able to respond to a broadcast primary address
cycle within the 500nsec minimum Master/ANC Logic handshake time. In these circumstances, the
module will assert the Fastbus WAIT signal for the period of time required by the slave to properly decode
the broadcast.

1881M Product Description
2-9 July 23, 1998
2.7 Data Space
Data memory in the 1881M ADC is a 8K word circular buffer, organized in sixty four pages of 128 words
each. Data resulting from an event is stored in one of the sixty four buffers. Each event buffer contains
enough locations to hold the maximum data resulting from a single event (65 words). An event is defined
as the occurrence of a Gate without a clear within the fast clear window.
In the power-up or reset state, Memory Test Mode is disabled, and the 1881M data space consists of only
DSR0 from the FASTBUS point of view. Writes to the Data Space NTA have no effect. CSR16 controls
the read buffer, as well as the write buffer which will be used to store the next event readout of the
MTD133s. Only the data page portion of the buffers can be accessed. At power-up, or when a master
reset is issued, the read buffer will be 63, and the write buffer will be 0. Once an event occurs and is
buffered, the write buffer number is automatically incremented. CSR16 is a read-write register which can be
used to control the position of the read and write buffers. Under normal operating circumstances, it is not
necessary to change these buffers because it is done automatically. CSR16<10:8>, the read buffer, is
modified by the Load Next Event command and CSR16<2:0>, the write buffer, is modified by the
MTD133 readout circuitry (see figure 2-4).
When Memory Test Mode is enabled, any location within the 8K data space is directly accessible via
FASTBUS. At any particular time, there are 128 (one complete buffer) secondary addresses (DSRs)
available in data space. The buffer currently pointed to by CSR16 can be modified by the Load Next Event
command or by writing CSR16 directly. This mode can be very useful to determine exactly what is going
on within the unit when debugging the system and it may be used for normal operation. It should be
noted, however, that the unit will not be FASTBUS compliant, as the module’s data space NTA will
move during priming operations (assuming Priming on LNE has been enabled).
CSR5<6:0> controls the number of words transferred in a block read. During normal data acquisition, a
Load Next Event both advances the read buffer to the next event, and loads CSR5<6:0> with the correct
word count for the event contained in the next buffer. This can be done for an entire crate of 1881Ms (and
1877s) by using a broadcast command. The maximum number of words transferred is limited to one full
buffer (128 words).
When the read pointer is one less than the write pointer (modulo 64) the buffers are considered empty.
When the read pointer and the write pointer are equal, the buffers are considered full. The condition "not
empty" is used for the Sparse Data Scan. The condition "full" is used to extend Conversion in Progress
(CIP) until the buffers are not full.

Product Description 1881M
July 23, 1998 2-10
2.7.1 Header Word Format
The first word (address zero) of each buffer contains a header word for the event data which follows and is
normally the first word readout during a block transfer. This header word contains the word count for that
event as well as parity, phase, buffer number, and geographic or logical address of the module. The word
count is automatically loaded into CSR5 when a Load Next Event command is issued. After each
FASTBUS block transfer data cycle, the word count register is decremented. The parity bit is high or low
so as to make the total number of bits in the header word even.
Figure 2-5 1881M Header Word
2.7.2 Data Word Format
The 1881M time data is read out in 32 bit data word. The 13 least significant bits are the charge data and
the 6 bits from 17 through 22 are the channel identification. The most significant byte contains the
geographic address, parity, and the buffer number (modulo 4). Here again the parity bit is high or low so
as to make the total number of bits in the word even.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEADER WORD FORMAT
BYTE 3 BYTE 2 BYTE 1 BYTE 0
G G G G G 0 0 0 P 0 0 B B B B B B W W W W W W W
LOGICAL ADDRESS
OR
GEOGRAPHIC ADDRESS
WORD COUNT
BUFFER NUMBER
WORD PARITY
00000000
GEOGRAPHIC ADDRESS
BUFFER NUMBER ( MODULO 4)
EVEN WORD PARITY
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1881M DATA WORD FORMAT
BYTE 3 BYTE 2 BYTE 1 BYTE 0
G G G G G P B B 0 C C C C C C 0 0 0 D D D D D D D D D D D D D D
DATA
CHANNEL NUMBER ( 0 - 63 decimal)
Figure 2-6 1881M Data Word

1881M Product Description
2-11 July 23, 1998
2.8 Readout
2.8.1 Single Read from Data Space
Reading of the data can be done using random read cycles, however, first the correct number of words to
read must be ascertained. Assuming Load Next Event has been used to select the desired event to read, the
first location of this buffer, the header word, must be read to find out how many words are in the event.
Bits <6:0> of the header word contain the word count for the event. This word count is the number of data
words plus one for the header word itself. With this information the correct number of words for the event
can be read by repeated reads to DSR0.
2.8.2 Block Transfer Read from Data Space
Block transfers are the preferred way to read data from the 1881M, and this is facilitated by the Load Next
Event function, CSR0<10>. A write to CSR0<10>, increments the internal read pointer by one and loads
CSR5 with the word count for that event. This can be done for an entire crate at one time using a
broadcast. A subsequent block read will transfer data until automatic decrementing of CSR5 reaches 0, the
end of the event's data. . When the unit is done reading out all the data for that event SS = 2. The first
word transferred is the header word.
2.9 FASTBUS Write to Data Memory
Although not pertinent to data acquisition, it is possible to write to the data memory via FASTBUS.
This may be desired for testing. For this purpose, the data memory appears as a 8192 x 32 bit word
RAM. Data may be written into this RAM using random, or broadcast modes. Block writes to data space
are not supported. Since the 1881M event manager is not managing this loading, the parity checking,
channel identification, and geographic address identification normally present in the data are not present
when read back.
2.10 Fast Clears
A fast clear can be applied any time during the fast clear window. This will cause the event just recorded
in the front end not to be buffered. The write page will not be incremented. The buffering situation will be
as though the cleared event never took place. This action requires a minimum time given in the
specification. This is the time starting from the beginning edge of the fast clear pulse until the module is
ready to accept another event. Fast clears can be applied either from the front panel input, by writing
CSR0<31>, which can of course be done using a broadcast write, or via a model 1810 CAT (TR0).
2.11 Allocation of Restricted Use Lines
Using CSR1, the 1881M can be enabled to accept Common, Fast Clear Window, and Fast Clear inputs on
the TR lines. In addition, during internal test mode the 1810 CAT can be used to control the magnitude of
the test pulse using the UR lines. These lines have been allocated to be compatible with the LeCroy model
1810 Calibration and Timing module facilitating distribution of these signals throughout a crate. The
assignments are:
TR0 - Fast Clear
TR1,2 - Gate (TR1 +, TR2 -)
TR3 - Test Pulse