LG 60PN6500 User manual

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
Printed in KoreaP/NO : MFL67643201 (1302-REV01)
CHASSIS : PU31A
MODEL : 60PN6500 60PN6500-UA
MODEL : 60PN6550 60PN6550-UA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
PLASMA TV
SERVICE MANUAL

- 2 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CONTENTS
CONTENTS .............................................................................................. 2
SAFETY PRECAUTIONS ........................................................................ 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION ................................................................ 5
BLOCK DIAGRAM.................................................................................. 12
EXPLODED VIEW .................................................................................. 13
SCHEMATIC CIRCUIT DIAGRAM ..............................................................

- 3 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩand 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
IMPORTANT SAFETY NOTICE
To Instrument's
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
SAFETY PRECAUTIONS

- 4 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement .
1. Application range
This spec sheet is applied all of the 42” 50”, 60” PDP TV with PU31A chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
(1) Performance: LGE TV test method followed
(2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
4. Model General Specification
No Item Specication Remark
1 Receiving System 1) ATSC / NTSC-M / 64&256 QAM
2 Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
5) CADTV : 01~135
3 Input Voltage 1) AC 100 ~ 240V 50/60Hz N.America Mark : 110V, 60Hz
4 Market NORTH AMERICA
5 Screen Size 42 inch Wide(1024 × 768) 42PN all model
50 inch Wide(1024 × 768) 50PN4500 model
50 inch Wide(1920 × 1080) 50PN6500/50PN5300 model
60 inch Wide(1920 × 1080) 60PN6500/60PN5300 model
6 Aspect Ratio 16:9
7 Tuning System FS
8 Module PDP42T4#### (1024 × 768) 42PN all model
PDP50T5#### (1024 × 768) 50PN4500 model
PDP50R5#### (1920 × 1080) 50PN6500/50PN5300 model
PDP60R5#### (1920 × 1080) 60PN6500/60PN5300 model
9 Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
10 Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %

- 5 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range
This spec. sheet applies to PU31A chassis applied PDP TV all
models manufactured in TV factory.
2. Specification
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~, 50/60 Hz.
(5) Before adjustment, execute Heat-Run for 5 minutes.
■ After Receive 100% Full white pattern (06CH) then
process Heat-run
(or “8. Test pattern” condition of Ez-Adjust status)
■How to make set white pattern
1) Press Power ON button of Service Remocon
2) Press ADJ button of Service remocon. Select “10. Test
pattern” and, after select “White” using navigation
button, and then you can see 100% Full White pattern.
* In this status you can maintain Heat-Run useless any
pattern generator
* Notice: if you maintain one picture over 20 minutes
(Especially sharp distinction black with white
pattern – 13Ch, or Cross hatch pattern – 09Ch)
then it can appear image stick near black level.
3. Adjustment items
3.1. PCB Assembly adjustment
■Adjust 480i Comp1
■Adjust 1080p Comp1/RGB
●If it is necessary, it can adjustment at Manufacture Line
●You can see set adjustment status at “9. ADJUST
CHECK” of the “In-start menu”
3.2. Set Assembly Adjustment
■EDID (The Extended Display Identification Data )
■Color Temperature (White Balance) Adjustment
■Make sure RS-232C control
■Selection Factory output option
4. PCB Assembly Adjustment
4.1. Using RS-232C
- Adjust 3 items at 3.1. PCB assembly adjustments
" 4.1. ■Adjustment sequence" one after the order.
■Adjustment sequence
■Necessary items before Adjustment items
●Pattern Generator : (MSPG-925FA)
●Adjust 480i comp1
(MSPG-925FA:model :209, pattern :65) - comp1 Mode
●Adjust 1080p comp1
(MSPG-925FA:model :225 , pattern :65) - comp1 Mode
●Addjust RGB (MSPG-925FA:model :225 , pattern :65)
- RGB-Pc Mode
* If you want more information then see the below Adjustment
method (Factory Adjustment)
■Adjustment sequence
●aa 00 00: Enter the ADc Adjustment mode.
●xb 00 40: change the mode to component1 (No actions)
●ad 00 10: Adjust 480i comp
●ad 00 10: Adjust 1080p comp
●xb 00 60: change to RGB-Pc mode(No action)
●ad 00 10: Adjust 1080p RGB
●xb 00 90: Endo of Adjustmennt
Order command Set response
1. Inter the
Adjustment
mode
aa 00 00 a 00 OK00x
2. Change
the Source
XB 00 40
XB 00 60
b 00 OK40x (Adjust 480i Comp1 )
(Adjust 1080p Comp1)
b 00 OK60x (Adjust 1080p RGB)
3. Start
Adjustment
ad 00 10
4. Return the
Response
OKx ( Success condition )
NGx ( Failed condition )
5. Read
Adjustment
data
( main )
ad 00 20
( main )
ad 00 30
(main : component1 480i, RGB 1080p)
000000000000000000000000007c007b006dx
(main : component1 1080p)
000000070000000000000000007c00830077x
6. Conrm
Adjustment
ad 00 99 NG 03 00x (Failed condition)
NG 03 01x (Failed condition)
NG 03 02x (Failed condition)
OK 03 03x (Success condition)
7. End of
Adjustment
ad 00 90 d 00 OK90x
< See ADC Adjustment RS232C Protocol_Ver1.0 >

- 6 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
5. Factory Adjustment
-> PU31A : USE INTERNAL ADC(LM1) : using internal pattern.
5.1. Auto Adjust Component 480i/1080p RGB
1080p
■Summary : Adjustment component 480i/1080i and RGB
1080p is Gain and Black level setting at Analog
to Digital converter, and compensate the RGB
deviation
■Using instrument
●Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator
(It can output 480i/1080i horizontal 100% color bar
pattern signal, and its output level must setting
0.7V±0.1V p-p correctly)
●You must make it sure its resolution and pattern cause
every instrument can have different setting
●Adjustment method 480i Comp1, Adjust 1080p Comp1/
RGB (Factory adjustment)
●ADC 480i Component1 adjustment
- Check connection of Component1
- MSPG-925FA -> Model: 209, Pattern 65
●Set Component 480i mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”
●ADC 1080p Component1 / RGB adjustment
- Check connection both of Component1 and RGB
- MSPG-925FA -> Model: 225, Pattern 65
●Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”
●After get each the signal, wait more a second and enter
the “IN-START” with press IN-START key of Service
remocon. After then select “7. External ADC” with
navigator button and press “Enter”.
●After Then Press key of Service remocon “Right Arrow
(VOL+)”
●You can see “ADC Component1 Success”
●Component1 1080p, RGB 1080p Adjust is same method.
●Component 1080p Adjustment in Component1 input
mode
●RGB 1080p adjustment in RGB input mode
●If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”
* caution : Set Volume 0 after adjustment
5.2. Use Internal ADC(S7R)
- ADJ(EZ ADJUST) -> 6.ADC Calibration -> ADC
Calibration(START)
* EDID (The Extended Display Identification Data)/DDC
(Display Data Channel) Download.
■Summary
● It is established in VESA, for communication between
PC and Monitor without order from user for building
user condition. It helps to make easily use realize
“Plug and Play” function.
● For EDID data write, we use DDC2B protocol.
- Auto Download
■ After enter Service Mode by pushing “ADJ” key,
■ Enter EDID D/L mode.
■ Enter “START” by pushing “OK” key.
* Caution:
- Never connect HDMI & D-sub Cable when the user
downloading .
- Use the proper cables below for EDID Writing
< Adjustment pattern : 480i / 1080p 60Hz Pattern >

- 7 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
■ It only needs to PCM EDID D/L for North America Product.
(PU31A)
* Edid data and Model option download(RS232)
- Manual Download
■ Write HDMI EDID data
● Using instruments
- Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
- S/W for DDC recording (EDID data write and read)
- D-sub jack
- Additional HDMI cable connection Jig.
● Preparing and setting.
- Set instruments and Jig. Like pic.5), then turn on PC
and Jig.
- Operate DDC write S/W (EDID write & read)
- It will operate in the DOS mode.
■ EDID data (Model name = LG TV)
- PCM ONLY
- North America _2D_FHD_HDMI 1
NO Enter
download MODE
EDID data Model
option download
Item download ‘Mode In’ download
CMD 1 A A
CMD 2 A E
Data 0 0 *Note1
0 *Note2
When transfer the
‘Mode In’,
Carry the command.
Automatically download
(The use of a internal
pattern)
< For write EDID data, setting Jig and another instruments >
Item Adjust ‘Mode Out’’ Adjustment Conrmation
CMD 1 A A
CMD 2 E E
Data 0 9 9
0 9
When transfer the
‘Mode In’,
Carry the command.
To check Download
on Assembly line.
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 01 01
01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 97
02 03 19 F1 48 90 04 05 02 03 20 22 01 23 09 57
07 67 03 0C 00 10 00 B8 2D 02 3A 80 18 71 38 2D
40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71
1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00
72 51 D0 1E 20 62 28 55 00 40 84 63 00 00 1E 0E
1F 00 80 51 00 1E 30 40 80 37 00 40 84 63 00 00
1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 EB

- 8 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- North America _2D_FHD_HDMI 2
- PCM+AC3 FOR SVC
- FHD_HDMI 1
- FHD_HDMI 2
- See Working Guide if you want more information about EDID
communication.
- Adjustment Color Temperature(White balance)
■ Using Instruments
● Color Analyzer: CA-210 (CH 10)
- Using LCD color temperature, Color Analyzer (CA-
210) must use CH 10, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
2100. See the Coordination bellowed one.
● Auto-adjustment Equipment (It needs when Auto-adjust-
ment – It is availed communicate with RS-232C : Baud
rate: 115200)
● Video Signal Generator MSPG-925F 720p, 216Gray
(Model: 217, Pattern 78)
■ Connection Diagram (Auto Adjustment)
● Using Inner Pattern
● Using HDMI input
< connection Diagram for Adjustment White balance >
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 01 01
01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 97
02 03 19 F1 48 90 04 05 02 03 20 22 01 23 09 57
07 67 03 0C 00 20 00 B8 2D 02 3A 80 18 71 38 2D
40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71
1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00
72 51 D0 1E 20 62 28 55 00 40 84 63 00 00 1E 0E
1F 00 80 51 00 1E 30 40 80 37 00 40 84 63 00 00
1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 DB
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 01 01
01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 97
02 03 1C F1 48 90 04 05 02 03 20 22 01 26 15 07
50 09 57 07 67 03 0C 00 10 00 B8 2D 02 3A 80 18
71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D
80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E
01 1D 00 72 51 D0 1E 20 62 28 55 00 40 84 63 00
00 1E 0E 1F 00 80 51 00 1E 30 40 80 37 00 40 84
63 00 00 1C 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E9
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 01 01
01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 97
02 03 1C F1 48 90 04 05 02 03 20 22 01 26 15 07
50 09 57 07 67 03 0C 00 20 00 B8 2D 02 3A 80 18
71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D
80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E
01 1D 00 72 51 D0 1E 20 62 28 55 00 40 84 63 00
00 1E 0E 1F 00 80 51 00 1E 30 40 80 37 00 40 84
63 00 00 1C 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D9

- 9 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
■ White Balance Adjustment
If you can’t adjust with inner pattern, then you can adjust
it using HDMI pattern. You can select option at “Ez-Adjust
Menu – 7. White Balance” there items “NONE, INNER,
HDMI”. It is normally setting at inner basically. If you can’t
adjust using inner pattern you can select HDMI item, and
you can adjust.
In manual Adjust case, if you press ADJ button of service
remocon, and enter “Ez-Adjust Menu – 7. White Balance”,
then automatically inner pattern operates. (In case of
“Inner” originally “Test-Pattern. On” will be selected in The
“Test-Pattern. On/Off”.
● Connect all cables and equipments like Pic.5)
● Set Baud Rate of RS-232C to 115200. It may set 115200
orignally.
● Connect RS-232C cable to set
● Connect HDMI cable to set
■ RS-232C Command (Commonly apply)
● “wb 00 00”: Start Auto-adjustment of white balance.
● “wb 00 10”: Start Gain Adjustment (Inner pattern)
● “jb 00 c0” :
● …
● “wb 00 1f”: End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00 2f-
end)
● “wb 00 ff”: End of white balance adjustment (inner pattern
disappear)
■Adjustment Mapping information
● When Color temperature (White balance) Adjustment
(Automatically)
- Press “Power only key” of service remocon and operate
automatically adjustment.
- Set BaudRate to 115200.
● You must start “wb 00 00” and finish it “wb 00 ff”.
● If it needs, then adjustment “Offset”.
■ White Balance Adjustment (Manual adjustment)
● Test Equipment: CA-210
- Using PDP color temperature, Color Analyzer (CA-210)
must use CH 10, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.
● Manual adjustment sequence is like bellowed one.
- Turn to “Ez-Adjust” mode with press ADJ button of service
remocon.
- Select “10.Test Pattern” with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
10cm from center of PDP module when adjustment.
- Press “ADJ” button of service remocon and select
“7.White-Balance” in “Ez-Adjust” then press “►” button of
navigation key. (When press “►” button then set will go to
full white mode)
- Adjust at three mode (Cool, Medium, Warm)
- If “cool” mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then control
R, G gain adjustment High Light adjustment.
- If “Medium” and “Warm” mode Let R-Gain to 192 and R,
G, B-Cut to 64 and then control G, B gain adjustment
High Light adjustment.
- All of the three mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then control
G, B gain adjustment High Light adjustment.
- With volume button (+/-) you can adjust.
- After all adjustment finished, with Enter (■ key) turn to
Ez-Adjust mode. Then with ADJ button, exit from
adjustment mode
* Attachment: White Balance adjustment coordination and
color temperature.
● Using CS-1000 Equipment.
- COOL : T=11000K, ∆uv=0.000, x=0.276 y=0.283
- MEDIUM : T=9300K, ∆uv=0.000, x=0.285 y=0.293
- WARM : T=6500K, ∆uv=0.000, x=0.313 y=0.329
RS-232C
COMMAND
[CMD ID DATA]
M
I
N
CENTER
(DEFAULT)
M
A
X
Cool Mid Warm Cool Mid Warm
R Gain jg Ja jd 00 184 192 192 192
G Gain jh Jb je 00 187 183 159 192
B Gain ji Jc jf 00 192 161 95 192
R Cut 64 64 64 127
G Cut 64 64 64 127
B Cut 64 64 64 127
RS-232C COMMAND
[CMD ID DATA]
Meaning
wb 00 00 White Balance adjustment start.
wb 00 10 Start of adjust gain
(Inner white pattern)
wb 00 1f End of gain adjust
wb 00 20 Start of offset adjust
(Inner white pattern)
wb 00 2f End of offset adjust
wb 00 ff End of White Balance adjust
(Inner pattern disappeared)

- 10 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
● When tester will measure on Cool condition, adjust W30 on
TV display menu.
● When tester will measure on medium condition, adjust 0 on
TV display menu.
● When tester will measure on warm condition, adjust W30 on
TV display menu.
● Using CA-210 Equipment. (10 CH)
- Contrast value: 216 Gray
- Brightness spec.
5.3. Test of RS-232C control.
- Press In-Start button of Service Remocon then set the
“4.Baud Rate” to 115200. Then check RS-232C control and
5.4. Selection of Country option.
- Selection of country option is allowed only North American
model (Not allowed Korean model). It is selection of Country
about Rating and Time Zone.
■ Models: All models which PU31A Chassis (See the rst
page.)
■ Press “In-Start” button of Service Remocon, then enter the
“Option” Menu with “PIP CH-“ Button
■ Select one of these three (USA, CANADA, MEXICO) de-
pends on its market using “Vol. +/-“button.
* Caution : Don’t push The INSTOP KEY after completing the
function inspection.
* Caution : Inspection only PAL M / NTSC
6. GND and ESD Testing
6.1. Prepare GND and ESD Testing.
■ Check the connection between set and power cord
6.2. Operate GND and ESD auto-test.
■ Fully connected (Between set and power cord) set enter the
Auto-test sequence.
■ Connect D-Jack AV jack test equipment.
■ Turn on Auto-controller(GWS103-4)
■ Start Auto GND test.
■ If its result is NG, then notice with buzzer.
■ If its result is OK, then automatically it turns to ESD Test.
■ Operate ESD test
■ If its result is NG, then notice with buzzer.
■ If its result is OK, then process next steps. Notice it with
Good lamp and STOPER Down.
6.3. Check Items.
■ Test Voltage
● GND: 1.5KV/min at 100mA
● Signal: 3KV/min at 100mA
■ Test time: just 1 second.
■ Test point
● GND test: Test between Power cord GND and Signal
cable metal GND.
● ESD test: Test between Power cord GND and Live and
neutral.
■ Leakage current: Set to 0.5mA(rms)
6.4. POWER PCB Ass’y Voltage adjustment
(Va, Vs voltage adjustment)
6.4.1. Test equipment : : D.M.M 1EA
6.4.2. Connection Diagram for Measuring
: refer to g.1
<XPOWER4 60T3/R3 PSU>
6.4.3. Adjustment method
6.4.3.1. Vs adjustment (refer g.1)
(1) Connect + terminal of D.M.M. to Vs pin of P811, connect
-terminal to GND pin of P811
(2) After turning VR901, voltage of D.M.M adjustment as same
as Vs voltage which on label of panel left/top ( deviation ;
±0.5V)
6.4.3.2. Va adjustment (refer g.1)
(1) After receiving 100% Full White Pattern, HEAT RUN.
(2) Connect + terminal of D.M.M. to Va pin of P811, connect
-terminal to GND pin of P811
(3) After turning VR502,voltage of D.M.M adjustment as same
as Va voltage which on label of panel left/top (deviation;
±0.5V)
Color
temperature
Test
Equipment
Color Coordination
x y
COOL CA-210 0.276 ± 0.002 0.283 ± 0.002
MEDIUM CA-210 0.285 ± 0.002 0.293 ± 0.002
WARM CA-210 0.313 ± 0.002 0.329 ± 0.002
Item White average
brightness
Brightness uniformity
Min 49 -20
Typ 60
Max +20
Unit cd/m² %
Remark - 100% Window White
Pattern
- 100IRE(255Gray)
- Picture: Vivid(Medium)
- 85IRE(216Gray) 100%
Window White Pattern
- Picture: Vivid(Medium)
(g.1) PCB Assy Voltage adjustment

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Only for training and service purposes
7. Default Service option.
7.1. ADC-Set.
■ R-Gain adjustment Value (default 128)
■ G-Gain adjustment Value (default 128)
■ B-Gain adjustment Value (default 128)
■ R-Offset adjustment Value (default 128)
■ G-Offset adjustment Value (default 128)
■ B-Offset adjustment Value (default 128)
7.2. White balance. Value.
7.3. Temperature Threshold
■ Threshold Down Low 20
■ Threshold Up Low 23
■ Threshold Down High 70
■ Threshold Up High 75
8. USB DOWNLOAD(*.epk le download)
■ Put the USB Stick to the USB socket
■ Press Menu key, and move OPTION
■ Press “FAV” Press 7 times
■ Select download le (epk le)
■ After download is nished, remove the USB stick.
■ Press “IN-START” key of ADJ remote control, check the
S/W version.
9. Tool option
Center(Default)
COOL Mid Warm
R Gain 192 192 192
G Gain 192 192 192
B Gain 192 192 192
R Cut 64 64 64
G Cut 64 64 64
B Cut 64 64 64
60PN6500-UA 60PN6550-UA
Tool option 1 20996 20998
Tool option 2 8706 8706
Tool option 3 41097 41089
Country US
CA
MX
US
CA
MX

- 12 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BLOCK DIAGRAM

- 13 - LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LV1
A10
A2
400
305
301 300
580 520
601
240
200
201
204
206
208
205
910
900
207
202
203
120
302
303
304
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
CI_ADDR[7]
CI_ADDR[0]
CI_ADDR[9]
CI_ADDR[14]
CI_ADDR[1]
CI_ADDR[10]
CI_ADDR[4]
CI_ADDR[6]
BUF2_FE_TS_DATA[0-7]
CI_ADDR[12]
CI_ADDR[3]
CI_ADDR[8]
CI_ADDR[5]
CI_ADDR[13]
CI_ADDR[2]
CI_ADDR[11]
PCM_D[0-7]
PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]
PCM_D[0]
PCM_D[1]
PCM_D[2]
BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]
BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]
BUF2_FE_TS_DATA[7]
BUF1_FE_TS_DATA[0-7]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[5]BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[2]
BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[7]
BUF2_FE_TS_DATA[1]
BUF1_FE_TS_DATA[7]
BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[1]
BUF2_FE_TS_DATA[3]
BUF2_FE_TS_DATA[6]
BUF2_FE_TS_DATA[0]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[0]
AV/SC1_R_IN
R120
2.7K
EU
BUF2_FE_TS_DATA[0-7]
+3.3V_CI
BUF1_FE_TS_DATA[0-7]
R121
10K
R151
10K
EU
C111
220pF
50V
EU
AR102 33
EU
REG /PCM_REG
SCART1_MUTE
L100
EU
120-ohm
CI_IOWR
R103
100
EU
R136
330
EU
Q104
MMBT3904(NXP)
EU
E
B
C
PCM_A[7]
PCM_A[6]
BUF2_FE_TS_SYN
SC1_ID
PCM_D[0-7]
P_17V
CI_TS_VAL
/PCM_CE
CI_OE
BUF2_FE_TS_DATA[0-7]
CI_TS_CLK
R106
75
R123
33
EU
CI_TS_DATA[5] PCM_5V_CTL
BUF2_FE_TS_CLK
PCM_A[2]
PCM_A[10]
SCART1_Rout
R145
6.8K
EU
PCM_A[8]
CI_WE
SC1_G+/COMP1_Y+
R153
5.6K
EU
0
R129
EU
C107
5600pF
50V
EU
R118
470K
EU
CI_IORD
+3.3V
SC1_R+/COMP1_Pr+
AR103
33
EU
R134
100
1/4W
EU
R119
75
EU
R147
10K
EU
/CI_CD1
R104
10K
R114
10K
EU
CI_ADDR[13]
JK102
10067972-000LF
EU
G1G2
57
21
52
16
10
47
41
5
36
59
23
45
54
18
49
43
13
7
38
2
25
56
20
51
15
9
46
40
4
35
58
22
53
17
11
48
42
12
6
37
1
24
55
19
50
44
14
8
39
3
2660
2761
2862
2963
3064
31
32
33
34
65
66
67
68
69
C100
22uF
10V
EU
Q114
ZXMP3F30FHTA
EU
G
D S
SC1_SOG_IN
/PCM_IOWR
R116
470K
R198
10K
READY
CI_IORD
R148
15K
EU
AR105 33
EU
R117
75
EU
R149
15K
EU
CI_ADDR[14]
CI_ADDR[0-14]
AR106 33
EU
SC1_B+/COMP1_Pb+
/PCM_IORD
R126
12K
R132 100
EU
C104
0.1uF
16V
EU
R138
2K
EU
R144
470
EU
C108
5600pF
50V
EU
+3.3V_ST
PCM_A[13]
+5V
PCM_A[1]
R107
75
CI_ADDR[6]
BUF1_FE_TS_CLK
/PCM_WAIT
AR109
33EU
AR110
33 EU
R100 33
EU
CI_TS_DATA[6]
R143
180
EU
AV/SC1_L_IN
AV/SC1_CVBS_IN
/PCM_IRQA
+5V
CI_OE
PCM_A[12]
Q103
MMBT3906(NXP)
EU
E
B
C
R101 33
EU
AR108
33EU
IC100
TC74LCX244FT
EU
3
2Y4
2
1A1
4
1A2
1
1OE
6
1A3
5
2Y3
7
2Y2
8
1A4
9
2Y1
10
GND 11 2A1
12 1Y4
13 2A2
14 1Y3
15 2A3
16 1Y2
17 2A4
18 1Y1
19 2OE
20 VCC
PCM_A[0]
CI_TS_DATA[7]
R111
10K
EU
CI_WE
R184
10K
READY
C137
0.1uF
16V
EU
C101
0.1uF
16V
EU
CI_TS_DATA[2]
AR104
33
EU
C114
27pF
50V
EU
R124
10K
CI_ADDR[3]
R110
0
READY
CI_TS_DATA[4]
L101
EU
120-ohm
R127
12K
C109
27pF
50V
EU
R102
100
EU
IC101
AZ4580MTR-E1
3
IN1+
2
IN1-
4
VEE
1
OUT1
5IN2+
6IN2-
7OUT2
8VCC
R130 33EU
Q100
MMBT3904(NXP)
EU
E
B
C
MMBT3904(NXP)
Q101
EU
BUF2_FE_TS_VAL_ERR
DTV/MNT_VOUT
JK100
PSC008-02
EU
1AUDIO_R_OUT
2AUDIO_R_IN
3AUDIO_L_OUT
4AUDIO_GND
5B_GND
6AUDIO_L_IN
7B_OUT
8ID
9G_GND
10 D2B_IN
11 G_OUT
12 D2B_OUT
13 R_GND
14 RGB_GND
15 R_OUT
16 RGB_IO
17 SYNC_GND1
18 SYNC_GND2
19 SYNC_OUT
20 SYNC_IN
21 COM_GND
23
SHIELD
22 AV_DET
R131 33EU
MMBT3904(NXP)
Q102
EU
R165
10K
EU
CI_ADDR[8]
PCM_A[3]
BUF1_FE_TS_SYN
R112
0
READY
CI_DET
CI_TS_DATA[0]
CI_IOWR
SCART1_Lout
CI_TS_SYNC
R133
10K
EU
CI_ADDR[0]
R139
2K
EU
C115
27pF
50V
EU
R141
220
EU
PCM_A[5]
R105
1K
CI_ADDR[1]
R135
0
EU
CI_ADDR[2]
/PCM_WE
R108
75
PCM_A[11]
CI_TS_DATA[3]
BUF2_FE_TS_SYN
R181
10K
EU
C136
0.1uF
16V
READY
C131
0.1uF
16V
READY
CI_ADDR[12]
CI_ADDR[4]
PCM_A[4]
CI_ADDR[7]
BUF2_FE_TS_CLK
SC1_FB
BUF1_FE_TS_VAL_ERR
CI_ADDR[5]
AR100 33
EU
R154
5.6K
EU
BUF2_FE_TS_VAL_ERR
R115
470K
R113
75
EU
+5V_CI_ON
L103
EU
120-ohm
+5V
CI_ADDR[11]
AR107 33
EU
CI_ADDR[10]
PCM_A[9]
+3.3V_CI
R150
10K
EU
+3.3V
REG
/CI_CD2
R187
10K
EU
/PCM_OE
C105
0.1uF
16V
EU
R109
10K
EU
CI_TS_DATA[1]
+5V_CI_ON
PCM_A[14]
CI_ADDR[9]
PCM_RST
+5V
Q113
MMBT3904(NXP)
EU
E
B
C
R146
18K
EU
R128 0
READY
+3.3V_CI
R152
6.8K
EU
C102
100uF
16V
EU
R137
470
EU
R140
470
EU R189
1K
READY
R122 0
EU
R156 33
EU
R157 33
EU
C112
10uF
16V
EU
C113
10uF
16V
EU
C116
10uF
16V
EU
AV_L_IN
AV_R_IN
AV_DET
AV/SC1_DET
R155 100
EU
JP112 JP113 JP114
JP115
R125
4.7K
READY
+5V
C103
4.7uF
10V
READY
+5V
D100
20V
IC102
AP2151WG-7
READY
3FLG
2GND
4
EN
1OUT 5
IN
SCART,CI Slot
L13
1
DTV_R_OUT
SC1_VOUT
CI POWER ENABLE CONTROL
<CI SLOT>
<Full SCART>
3.3V_CI
2012-09-20
PDP L13
EAX65071305
7
JIG_GND
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

USB DOWN STREAM
Fiber Optic
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R280
0
ET_NET
+3.3V
R266
1K
C227
0.1uF
16V
MAX3232
R278
10K
R285
100
+5V_ST
D204
5.6V
ET_NET
R224
10K
Commercial
USB1_CTL
C225
0.1uF
16V
MAX3232
CK-_HDMI1
JK207
PEJ027-04
US_Commercial
6B T_TERMINAL2
7B B_TERMINAL2
5T_SPRING
4R_SPRING
7A B_TERMINAL1
6A T_TERMINAL1
3E_SPRING
R298
10K
R267
1K
R220
10K
Commercial
D1+_HDMI1
+5V_ST
RN
COMP2_L_IN
R228
10K
Commercial
PM_RXD
SPDIF_OUT
IC206
MAX3232CDR
MAX3232
3C1-
2V+
4C2+
1C1+
6V-
5C2-
7DOUT2
8RIN2 9
ROUT2
10
DIN2
11
DIN1
12
ROUT1
13
RIN1
14
DOUT1
15
GND
16
VCC
CEC_REMOTE_S7
C203
10pF
50V
IR
COMP2_Pr+
+5V
R256 10K
R263
12K
R216
75
+5V
COMP2_Y+
JK200
HDMI2_REAR
14
13
5D1_GND
20
SHIELD
12
11
2D2_GND
19
18
10 CK+
4D1+
1D2+
17
9D0-
8D0_GND
3D2-
16
7D0+
6D1-
15
TN
RGB_DDC_SCL
+3.3V_ST
JK210
XRJV-01V-0-D12-080
ET_NET
11
22
33
44
55
66
77
88
9
9
D2-_HDMI1
PC_R_IN
USB1_OCD
TX
R284 22
DSUB_B+
+3.3V_ST
R25710K
R270
10K
READY
D0-_HDMI1
R200
1K
COMP2_R_IN
D1-_HDMI1
R297
10K
+3.3V
R225
1K
R258
33
R205
33
R253
75
R211
10
R210
10
US_Commercial
+5V
PC_L_IN
R276 100
MAX3232
HPD1
C202
10pF
50V
R259
10K
Q204
MMBT3904(NXP)
Commercial
E
B
C
R222
12K
Commercial
COMP2_Pb+
R213
0
NON_Commercial
JP201
R255
470K
R204
3.3K
R268
100
C229
0.1uF
16V
MAX3232
JP241
JK206
PEJ027-04
PHONE JACK
6B T_TERMINAL2
7B B_TERMINAL2
5T_SPRING
4R_SPRING
7A B_TERMINAL1
6A T_TERMINAL1
3E_SPRING
R229
100K
Commercial
R252
75
R223
12K
Commercial
R264
10K
R217
10K
R273
0
ET_NET
TX
JP202
+2.5V
DDC_SCL_1
DDC_SDA_1
R281
10K
R291
0
ET_NET
JK209
3AU04S-305-ZC-(LG)
1234
5
GND
R219
470K
Commercial
R282
10K
JK208
PPJ234-02
5A
[GN]O-SPRING
6A
[GN]E-LUG
4A
[GN]CONTACT
7B
[BL]E-LUG-S
5B
[BL]O-SPRING
7C
[RD]E-LUG-S
5C
[RD]O-SPRING_1
4C
[RD]CONTACT_1
5D [WH]O-SPRING
4E [RD]CONTACT_2
5E [RD]O-SPRING_2
6E [RD]E-LUG
D200
5.6V
ET_NET
JK205
SPG09-DB-010
Commercial
1
RED
2
GREEN
3
BLUE
4
GND_1
5
DDC_GND
6
RED_GND
7
GREEN_GND
8
BLUE_GND
9
NC
10
SYNC_GND
11
GND_2
12
DDC_DATA
13
H_SYNC
14
V_SYNC
15
DDC_CLOCK
16
SHILED
R251
75
C213
10uF
10V
PC_SER_DATA
R262
12K
DSUB_VSYNC
R214
75
AV2_DET
Q200
MMBT3904(NXP)
E
B
C
R283 22
R290
0
ET_NET
CEC_REMOTE
R207
33
C226
0.1uF
16V
MAX3232 DSUB_HSYNC
SIDE_USB_DM
R254
470K
C220
10pF
50V
D205
5.6V
ET_NET
CK+_HDMI1
+3.3V
SIDE_USB_DP
RGB_DDC_SDA
C212
0.1uF
16V
R208
33
R202
10K
JK204
JST1223-001
1
GND
2
VCC
3
VINPUT
4
FIX_POLE
TP
PM_TXD
R212
10
DSUB_G+
C200
0.1uF
16V
ET_NET
R218
470K
Commercial
D206
5.6V
ET_NET
PC_SER_CLK
R279
10K
D0+_HDMI1
+3.3V
DSUB_R+
D2+_HDMI1
RP
R215
75
DSUB_DET
R271
33
R233
100K
Commercial
5V_DET_HDMI_1
COMP2_DET
R201
1.8K
R221
10K
Commercial
C219
0.1uF
16V
CEC_REMOTE
R206
33
Commercial
R277
100
MAX3232
C228
0.1uF
16V
MAX3232
R265
10K
JK203
SPG09-DB-009
Commercial
1
2
3
4
5
6
7
8
9
10
+3.3V_ST
RGB_DDC_SCL
JK202
PPJ231-01
GROWTH
8
6
7
5
4
AV_DET
AV_R_IN
AV_L_IN
JP207
CEC_REMOTE
D0-_HDMI3
R237
1K
HPD3
JK201
HDMI1_SIDE
14
13
5D1_GND
20
BODY_SHIELD
12
11
2D2_GND
19
18
10 CK+
4D1+
1D2+
17
9D0-
8D0_GND
3D2-
16
7D0+
6D1-
15
D1+_HDMI3
DDC_SCL_3
CK+_HDMI3
R231
33
JP208
D0+_HDMI3
5V_DET_HDMI_3
R238
1.8K
+5V
R244
3.3K
D1-_HDMI3
Q202
MMBT3904(NXP)
E
B
C
R288
10K
CK-_HDMI3
D2-_HDMI3
R289
10K
R232
10K
R209
10K
DDC_SDA_3
D2+_HDMI3
R246
33
RGB_DDC_SDA
R226
0
P_JACK TO RS232C
R227
0
P_JACK TO RS232C
C201
0.1uF
16V
R275
0
READY
R274
0
READY
AV/SC1_CVBS_IN
R230
75
GROWTH
VA208
VA210
VA209
VA203
VA207
VA204
VA206
VA205
VA202
VA200
VA201
VA214
Commercial VA213
Commercial
R203
0
GROWTH R234
0
GROWTH
VA216
VA217
IC204
BD82020FVJ
3IN_2
2IN_1
4EN
1GND
5
OC
6
OUT_1
7
OUT_2
8
OUT_3
P602
12507WS-04L
NON_Commercial
1
2
3
4
5
VA211
VA212
P603
12507WS-04L
NON_Commercial
1
2
3
4
5
<RGB PC>
<SPDIF>
<PHONE JACK>
<RS232C>
<HDMI2_REAR>
For CEC
L13
JACK INTERFACE
2
10mm
<SIDE USB>
<COMPONENT>
2012-06-01
<ETHERNET (T2 UK)>
7
<WIRED IR>
SWITCH ADDED
<AV (Growth & SCA)>
<HDMI1_SIDE>
(1) NON-OS Normal : O (RS232 Debug)
(2) NON-OS Commercial : O (PC Audio)
(3) OS Normal : X
(4) OS Commercial : O (PC Audio)
<FOR COMMERCIAL>
<HDMI> <IN/OUT>
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TUNER
BUF1_FE_TS_DATA[7]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[4]
FE_TS_DATA[7]
FE_TS_DATA[6]
FE_TS_DATA[5]
FE_TS_DATA[4]
FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3] BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[0]
FE_TS_DATA[7]
FE_TS_DATA[6]
FE_TS_DATA[1]
FE_TS_DATA[5]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[0]
BUF1_FE_TS_VAL_ERR
R331 0 FNIM
TU_SDA
+3.3V_TU
R305
10K
FNIM
C306
0.1uF
16V
T2_SDA
BUF1_FE_TS_CLK
R328 0 DVB_T2
C316
68pF
50V
R317
82
C307
0.1uF
16V
RF_SWITCH
FE_TS_CLK
FE_TS_SYN
+1.8V_TU
R309
1.5K R311 10K
R327 0 DVB_T2
R333 0 FNIM
R330 0 DVB_T2
TU_GND
TU_GND
FE_TS_CLK
T2_SCL
R332 0 FNIM
R30622
R301
100
TU_CVBS
R326 0 DVB_T2
C303
10uF
16V
C314
10uF
6.3V
FNIM
R323 0 FNIM
FE_TS_SYN
IF_AGC_MAIN
+3.3V_TU
RF_SWITCH_CTL
+3.3V_TU
FE_TS_VAL_ERR
R308
1.5K
+1.25V_TU
TU_GND
C302
0.1uF
16V
R338
0
TUNER_RESET
FE_TS_DATA[0-7]
BUF1_FE_TS_SYN
R312
4.7K
R3030
H_NIM
BUF1_FE_TS_DATA[0-7]
+5V
TU_SCL
C315
0.1uF
16V
FNIM DEMOD_RESET
C308
0.1uF
16V
TU_SIF
R310
1K
RF_SWITCH
+3.3V_TU
R329 0 DVB_T2
FE_TS_DATA[0-7]
R313
1.5K
R304
100
FNIM
R314
1.5K
R315 22
R316
470
IF_N_MSTAR
C305
68pF
50V
R336
0SBTVD
IF_P_MSTAR
C317
68pF
50V
C310
0.1uF
16V
R324 0 DVB_T2
C304
68pF
50V
R335 0
SBTVD
TU_GND
TU_GND
C311
0.1uF
16V
R30722
R325 0 DVB_T2
TU301
TDSS-G201D
DVB_T/C
5+B1[3.3V]
11 DIF[N]
2RESET
10 DIF[P]
4SDA
1NC_1
9IF_AGC
8NC_3
3SCL
7+B2[1.8V]
6NC_2
12
SHIELD
A1 A1 B1
B1
FE_TS_VAL_ERR
R337
0
R318 22
Q301
MMBT3906(NXP)
E
B
C
TU_GND
TU303
TDSS-H501F
ATSC
5+B1[3.3V]
11 DIF[N]
2RESET
10 DIF[P]
4SDA
1NC
9IF_AGC
8ALIF_[P]
3SCL
7+B2[1.8]
6ALIF_[N]
12
SHIELD
A1 A1 B1
B1
TU305
TDSN-B601F
SBTVD
1RF_S/W_CTL
2RESET_TUNER
3SCL
4SDA
5+B1[3.3V]
6SIF
7+B2[1.8V]
8CVBS
9NC_1
10 NC_2
11 NC_3
12 +B3[3.3V]
13 +B4[1.23V]
14 RESET_DEMOD
15 GND
16 ERROR
17 SYNC
18 VALID
19 MCLK
20 D0
21 D1
22 D2
23 D3
24 D4
25 D5
26 D6
27 D7
28
SHIELD
A1 A1 B1
B1
R320
2K
R322
430
R319
430
TU302
TDSH-G501D
CHINA
5+B1[3.3V]
11 DIF[N]
2RESET
10 DIF[P]
4SDA
1NC
9IF_AGC
8CVBS
3SCL
7+B2[1.8V]
6SIF
A1 A1 B1
B1
A2
A2
B2
B2
TU304
TDSH-T101F
CO_PANAMA
5+B1[3.3V]
11 DIF[N]
2RESET
10 DIF[P]
4SDA
1RF_S/W_CTL
9IF_AGC
8CVBS
3SCL
7+B2[1.8V]
6SIF
12
SHIELD
A1 A1 B1
B1
TU_GND
TU306
TDSQ-G605D
DVB_T2
1NC_1
2RESET
3SCL
4SDA
5+B1[3.3V]
6SIF
7+B2[1.8V]
8CVBS
9NC_2
10 NC_3
11 NC_4
12 NC_5
13 NC_6
14 NC_7
15 GND
16 ERROR
17 SYNC
18 VALID
19 MCLK
20 D0
21 D1
22 D2
23 D3
24 D4
25 D5
26 D6
27 D7
28 GND_1
29 GND_2
30 +B3[1.23V]
31 T2_RESET
36
SHIELD
32 +B4[3.3V]
33 NC_8
34 T2_SCL
35 T2_SDA
A1 A1 B1
B1
+3.3V_TU
Q302
MMBT3906(NXP)
READY
E
B
C
R339 0
A_DEMODE
R340
220
READY
R341
220
READY
Close to Tuner Pin
Tuner block
TDSS-G501D
TDSH-G501D
TDSN-T501F
TDSN_B601F
TDSQ_G605D
TUNER OPT1 OPT2 OPT3
DVB-T/C
China
DVB-T_SCA
SBTVD
DVB_T2
HNIM
HNIM
FNIM
FNIM
RF_SW
RF_SW
X
X
X
37
Close to Tuner Pin
Close to Tuner Pin
Close to Tuner Pin
TDSS-H501F ATSC HNIM X
TU301
TU302
TU303
TU304
TU305
TU306
HNIM
OPT4
W/O AD
With AD
W/O AD
W/O AD
W/O AD
With AD
L13 2012-06-01
DVB-T2 OPT
A-DEMODE OPT
DVB_T/C OPT
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PCM_D[6]
PCM_D[7]
PCM_D[5]
PCM_D[0-7]
PCM_D[0]
PCM_D[3]
PCM_D[1]
PCM_D[2]
PCM_D[4]
PCM_A[12]
PCM_A[8]
PCM_A[1]
PCM_A[9]
PCM_A[6]
PCM_A[13]
PCM_A[11]
PCM_A[14]
PCM_A[5]
PCM_A[0]
PCM_A[7]
PCM_A[3]
PCM_A[2]
PCM_A[4]
PCM_A[10]
BUF1_FE_TS_DATA[7]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[4]
CI_TS_DATA[6]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[5]
CI_TS_DATA[4]
CI_TS_DATA[3]
CI_TS_DATA[7]
CI_TS_DATA[0]
C477
0.1uF
C436 10uF
C487 0.1uF
10uFC455
C431 0.1uF
C482 0.1uF
R410 1K
HD
L401
BLM18PG121SN1D
C438 0.1uF
P_SCL
C441 0.1uF
R453
2.2K
I2C_SCL
10uFC435
L406
BLM18PG121SN1D
+3.3V
10uFC434
+1.5V_DDR
AUD_MASTER_CLK
C485
0.1uF
C401
0.1uF
R472 1K
C472 1uF
AVSS_PGA
AVDD2P5
C478 0.1uF
L407
BLM18SG121TN1D
R462 1K
OS
+1.26V_VDDC
PWM0
R461 1K
+3.3V
D400
BAW56 GEANDE
+1.26V_VDDC
PWM1
C492 0.1uF
4V
C442
0.1uF
C484 0.1uF
AVDD_NODIE
C480 0.1uF
R409 1K
FHD
C465 10uF
R459 1K
LED_RED
VDD33
C467 1uF
C440 0.1uF
L400
BLM18PG121SN1D
C445
0.1uF
C489
0.1uF
4V
C491 0.1uF
4V
SOC_RESET
RF_SWITCH_CTL
+3.3V_ST
I2C_SDA
R405 1K
C453
0.1uF
4V
READY
10uFC457
C4000
0.1uF
4V
READY
AVDD25_PGA
AVDD_MIU
+3.3V_ST
+2.5V
C474 0.1uF
C402
0.1uF
C490 0.1uF
C444
0.1uF
+3.3V
MODEL_OPT_1
C446
1uF
R470 1K
L402
BLM18PG121SN1D
C432 0.1uF
L405
BLM18PG121SN1D
R452
2.2K
P_SDA
C4001
0.1uF
4V
READY
+3.3V
R403
100K
AUD_SCK
R463 1K
NON_OS
R408
10
C493 0.1uF
4V
C4003
0.1uF
C4004
0.1uF
C4005
0.1uF
4V
READY
C4006
0.1uF
4V
READY
C4002 0.1uF READY
C497
10uF
10V
R451
2.2K
R450
2.2K
CEC_REMOTE_S7
R406
22
P_SDA
SPDIF_OUT
COMP2_L_IN
PC_L_IN
PC_R_IN
C403 2.2uF
C406 2.2uF
C404 2.2uF
COMP2_R_IN
C408 2.2uF
C407 2.2uF
C405 2.2uF
AV/SC1_L_IN
AV/SC1_R_IN
SCART1_Lout
SCART1_Rout
L408
BLM18SG121TN1D
C411
0.1uF
C410
1uF
C409
4.7uF C412
10uF
P_SCL
R404 22
T2_SCL
T2_SDA
R401 22 DVB_T2
R402 22 DVB_T2
AUD_MASTER_CLK
AUD_SCK
AUD_LRCH
AUD_LRCK
LED_RED
PWM0
COMP2_DET
PWM1
KEY2
KEY1
17V_DET
VS_DET
SPI_SCK R40733
SPI_SDI
SPI_SDO R41333
/SPI_CS R41433
SCART1_MUTE
RGB_DDC_SCL R415 22
R416 22
RGB_DDC_SDA
PM_RXD
PM_TXD
PM_TXD
PM_RXD
I2C_SCL
I2C_SDA
AC_DET R417100
R411
1K
DISP_EN
RL_ON
VS_ON
/FLASH_WP
5V_ON
RXB4+
RXB4-
RXB3+
RXB3-
RXBCK+
RXBCK-
RXB2-
RXB2+
RXB1+
RXB1-
RXB0+
RXB0-
RXA4-
RXA4+
RXA3-
RXA3+
RXACK+
RXACK-
RXA2-
RXA2+
RXA1-
RXA1+
RXA0+
RXA0-
MODEL_OPT_1
DEMOD_RESET
RF_SWITCH_CTL
AV2_DET
TUNER_RESET
R419
22
EU AMP_SCL
5V_DET_HDMI_3
AMP_RESET_N
5V_DET_HDMI_1
AMP_SDA
CI_DET
DSUB_DET
PCM_5V_CTL
PCM_D[0-7]
PCM_A[0-14]
PCM_RST
/PCM_IRQA
C456
0.1uF
16V
EU
+5V
R458
10K
EU
R457 22
EU
/CI_CD1
/PCM_IOWR
/PCM_OE
/PCM_IORD
/PCM_WE
/PCM_CE
/PCM_WAIT
R460
10K
EU
/PCM_REG
R456 22EU
/CI_CD2
USB1_OCD
USB1_CTL
AR400
22 OS
/PF_CE1
/PF_CE0
/PF_WP
PF_ALE
AR401
22
OS
/PF_OE
/PF_WE
/F_RB
BUF1_FE_TS_CLK
BUF1_FE_TS_VAL_ERR
BUF1_FE_TS_SYN
BUF1_FE_TS_DATA[0-7]
CI_TS_SYNC
CI_TS_CLK
CI_TS_VAL
CI_TS_DATA[0-7]
C458
2pF
50V
EU
C462 0.1uF
H_NIM IF_P_MSTAR
C461 0.1uF
H_NIM
R465 100
H_NIM IF_N_MSTAR
R466 100
H_NIM
C463
100pF
READY
C464
100pF
READY
R467 47
A_DEMODE
C459 0.1uF
A_DEMODE
TU_SIF
C460 0.1uF
A_DEMODE
R468 47
A_DEMODE
TU_SDA
TU_SCL
+1.26V_VDDC
+1.26V_VDDC
AVDD2P5
AVDD25_PGA
AVSS_PGA
AVDD_NODIE
VDD33
C466 1uF
AVDD_MIU
R471 100
H_NIM
C469
0.047uF
25V
H_NIM
L410
H_NIM
BLM18PG121SN1D
R469
10K
H_NIM
IF_AGC_MAIN
+3.3V
C468
0.1uF
H_NIM
C414 0.047uF
DSUB_R+ R436 33 C415 0.047uF
R435
68
R437 68 C416 0.047uF
C417 0.047uF
DSUB_G+ R438 33
R428 68 C418 0.047uF
R429 33
DSUB_B+ C419 0.047uF
C420 1000pF
DSUB_HSYNC R422 22
DSUB_VSYNC R423 22
SC1_FB
SC1_ID
R440 33
R431 33
R442 33
SC1_R+/COMP1_Pr+ R441 68
SC1_B+/COMP1_Pb+ C426 0.047uF
C422 0.047uF
SC1_G+/COMP1_Y+ C424 0.047uF
C425 0.047uF
C421 0.047uF
R430 68
R439
68
C423 0.047uF
R420 10K
R421 2.4K
C427 1000pF
SC1_SOG_IN R432
0
READY
R418 100
R444 33
R434 33
R446 33
COMP2_Pr+ R445 68
COMP2_Pb+ C439 0.047uF
C429 0.047uF
COMP2_Y+ C433 0.047uF
C437 0.047uF
C428 0.047uF
C443 1000pF
R433 68
R443
68
C430 0.047uF
C449 0.047uF
C447 0.047uF
A_DEMODE
C448 0.047uFR425 33
R426 33
R424 33
A_DEMODE
COMP2_Y+
TU_CVBS
AV/SC1_CVBS_IN
DTV/MNT_VOUT
R427 68
L409 C413 0.047uF
RN
RP
R448
49.9 R449 49.9
C450
0.1uF
R454
49.9
C454
0.1uF
R455
49.9
TN
TP
AV/SC1_DET
SIDE_USB_DP
SIDE_USB_DM
SOC_RESET
TX DDC_SDA_3
CK-_HDMI3
D0-_HDMI3
D1-_HDMI3
D2-_HDMI3
HPD3
CK+_HDMI3
D0+_HDMI3
D1+_HDMI3
D2+_HDMI3
DDC_SCL_3
DDC_SCL_1
HPD1
D1+_HDMI1
D2-_HDMI1
CK-_HDMI1
DDC_SDA_1
D1-_HDMI1
D2+_HDMI1
D0-_HDMI1
CK+_HDMI1
D0+_HDMI1
AMP_MUTE R473
0
R464
2.2K R474 2.2K
UART_TXD
UART_RXD
UART_TXD
UART_RXD
R41222 EU
R475 1K
READY
IC400
LGE2111C-MS (PDP_13_MS10)
MS10
PCMDATA0/GPIO126
AB17
PCMDATA1/GPIO127
AB19
PCMDATA2/GPIO128
Y16
PCMDATA3/GPIO120
AD15
PCMDATA4/GPIO119
AE15
PCMDATA5/GPIO118
AD14
PCMDATA6/GPIO117
AB15
PCMDATA7/GPIO116
AC16
PCMADR0/GPIO125
Y17
PCMADR1/GPIO124
AA16
PCMADR2/GPIO122
AB16
PCMADR3/GPIO121
AD16
PCMADR4/GPIO99
Y18
PCMADR5/GPIO101
AE20
PCMADR6/GPIO102
Y19
PCMADR7/GPIO103
AC20
PCMADR8/GPIO108
AB18
PCMADR9/GPIO110
AD17
PCMADR10/GPIO114
AC15
PCMADR11/GPIO112
AE17
PCMADR12/GPIO104
AA19
PCMADR13/GPIO107
AA18
PCMADR14/GPIO106
AC19
PCM_RESET/GPIO129
AA17
PCMIRQA_N/GPIO105
AD20
PCMIOWR_N/GPIO109
AC18
PCMOE_N/GPIO113
AE14
PCMIORD_N/GPIO111
AD18
PCMCE_N/GPIO115
AC17
PCMWE_N/GPIO197
AD19
PCMCD_N/GPIO130
AE21
PCMREG_N/GPIO123
AE18
PCMWAIT_N/GPIO100
W16
PCM2_CD_N/GPIO135
Y21
PCM2_RESET/GPIO134
Y20
PCM2_CE_N/GPIO131
AA20
PCM2_IRQA_N/GPIO132
AB22
PCM2_WAIT_N/GPIO133
AB20
NF_ALE/GPIO141
AD10
NF_WPZ/GPIO198
Y9
NF_CEZ/GPIO137
AA10
NF_CLE/GPIO136
Y10
NF_REZ/GPIO139
AB10
NF_WEZ/GPIO140
AC9
NF_RBZ/GPIO142
AC10
TS1DATA0/GPIO88 Y14
TS1DATA1/GPIO89 AA14
TS1DATA2/GPIO90 AD13
TS1DATA3/GPIO91 Y13
TS1DATA4/GPIO92 AA13
TS1DATA5/GPIO93 AD12
TS1DATA6/GPIO94 AC12
TS1DATA7/GPIO95 W10
TS1CLK/GPIO98 AB13
TS1VALID/GPI96 AC14
TS1SYNC/GPIO97 W13
TS0DATA0/GPIO77 AB12
TS0DATA1/GPIO78 AD11
TS0DATA2/GPIO79 W9
TS0DATA3/GPIO80 AE11
TS0DATA4/GPIO81 AB11
TS0DATA5/GPIO82 AE12
TS0DATA6/GPIO83 AC13
TS0DATA7/GPIO84 AB14
TS0CLK/GPIO87 AA11
TS0VALID/GPIO85 Y11
TS0SYNC/GPIO86 AC11
IP AC3
IM AD2
SIFP AD1
SIFM AD3
IF_AGC AC2
GPIO73 AB3
GPIO74 AC4
I2C_SCKM1/GPIO75 AE3
I2C_SDAM1/GPIO76 AE2
IC400
LGE2111C-MS (PDP_13_MS10)
MS10
A_RX0N
F2
A_RX0P
G1
A_RX1N
G2
A_RX1P
G3
A_RX2N
H2
A_RX2P
H3
A_RXCN
F3
A_RXCP
F1
DDCDA_CK/GPIO23
H5
DDCDA_DA/GPIO24
H4
HOTPLUGA/GPIO19
H6
C_RX0N
AC6
C_RX0P
AD7
C_RX1N
AC7
C_RX1P
AD8
C_RX2N
AE8
C_RX2P
AC8
C_RXCN
AE6
C_RXCP
AD6
DDCDC_CK/GPIO27
AC5
DDCDC_DA/GPIO28
AE5
HOTPLUGC/GPIO21
AD5
HOTPLUGD/GPIO22
K6
CEC/GPIO5
R6
SPDIF_IN/GPIO152
B6
SPDIF_OUT/GPIO153
M7
AUL1 Y3
AUR1 AA2
AUL3 AA1
AUR3 AA3
AUL4 W3
AUR4 Y2
EARPHONE_OUTL AA9
EARPHONE_OUTR AB9
AUOUTL2 AB4
AUOUTR2 AB5
AUVRP Y5
AUVAG AA4
AUVRM AA5
I2S_IN_BCK/GPIO150 C10
I2S_IN_SD/GPIO151 B10
I2S_IN_WS/GPIO149 B9
I2S_OUT_BCK/GPIO156 A9
I2S_OUT_MCK/GPIO154 B8
I2S_OUT_WS/GPIO155 A8
I2S_OUT_SD/GPIO157 C9
IC400
LGE2111C-MS (PDP_13_MS10)
MS10
PWM0/GPIO66
AA22
PWM1/GPIO67
Y22
PWM2/GPIO68
V24
PWM3/GPIO69
U23
PWM4/GPIO70
T22
PWM_PM/GPIO199
C7
SAR0/GPIO31
E7
SAR1/GPIO32
D7
SAR2/GPIO33
J6
SAR3/GPIO34
D1
SAR4/GPIO35
C1
PM_SPI_SCK/GPIO1
A5
PM_SPI_SDI/GPIO2
B5
PM_SPI_SDO/GPIO3
B4
PM_SPI_SCZ1/GPIO_PM[6]/GPIO12
C4
PM_SPI_SCZ2/GPIO_PM[10]/GPIO16
B3
PM_SPI_CZ0/GPIO_PM[12]/GPIO0
D3
DDCA_CK/UART0_RX
E2
DDCA_DA/UART0_TX
D2
UART1_RX/GPIO44
E5
UART1_TX/GPIO43
E4
UART2_RX/GPIO64
U24
UART2_TX/GPIO65
U25
PM_UART_TX/GPIO_PM[1]/GPIO7
D4
PM_UART_RX/GPIO_PM[5]/GPIO11
D5
I2C_SCKM2/DDCR_CK/GPIO72
AA21
I2C_SDAM2/DDCR_DA/GPIO71
AB21
GPIO_PM[0]/GPIO6
M5
GPIO_PM[2]/GPIO8
L7
GPIO_PM[4]/GPIO10
J4
GPIO_PM[8]/GPIO14
L5
GPIO_PM[9]/GPIO15
L6
GPIO_PM[11]/GPIO17
L4
LVB0M W24
LVB0P V23
LVB1M W23
LVB1P W25
LVB2M Y24
LVB2P Y25
LVBCKM AA24
LVBCKP Y23
LVB3M AB24
LVB3P AA23
LVB4M AB23
LVB4P AB25
LVA0M AC24
LVA0P AC25
LVA1M AD24
LVA1P AD25
LVA2M AC23
LVA2P AE24
LVACKM AD23
LVACKP AE23
LVA3M AD22
LVA3P AC22
LVA4M AD21
LVA4P AC21
GPIO36 N5
GPIO37 A6
GPIO38 M6
GPIO39 R4
GPIO40 P5
GPIO41 D6
GPIO42 M4
GPIO45 C8
GPIO46 C5
GPIO49 E6
GPIO50 E3
GPIO51 K5
GPIO52 B7
GPIO53 K7
GPIO54 J5
IC400
LGE2111C-MS (PDP_13_MS10)
MS10
RIN0M
M1
RIN0P
M2
GIN0M
L3
GIN0P
L2
BIN0M
K2
BIN0P
K1
SOGIN0
K3
HSYNC0
J2
VSYNC0
J3
RIN1M
R3
RIN1P
R1
GIN1M
R2
GIN1P
P3
BIN1M
N3
BIN1P
N2
SOGIN1
P2
HSYNC1
R7
VSYNC1
R5
RIN2M
V1
RIN2P
V2
GIN2M
U3
GIN2P
U2
BIN2M
T2
BIN2P
T1
SOGIN2
T3
CVBS0
T5
CVBS1
T4
CVBS2
T6
VCOM
U4
CVBSOUT2
T7
RN A2
RP B2
TN B1
TP C2
LED0/GPIO55 A3
LED1/GPIO56 C3
USB1_DM AE9
USB1_DP AD9
HWRESET K4
IRIN/GPIO4 C6
XIN AE4
XOUT AD4
IC400
LGE2111C-MS (PDP_13_MS10)
MS10
VDDC_1
P17
VDDC_2
R17
VDDC_3
R18
VDDC_4
T17
VDDC_5
T18
VDDC_6
U18
VDDC_7
J9
VDDC_8
J11
VDDC_9
P8
VDDC_10
R8
VDDC_11
U11
VDDC_12
V10
AVDDLV
U17
DVDD_DDR
P18
AVDD25_LAN
Y8
AVDD2P5_DADC
AA8
AVDD_MOD
AB8
AVDD25_PGA
AB1
AVSS_PGA
AB2
AVDD_NODIE
W4
AVDD_DMPLL
W5
AVDD_DVI_USB_MPLL
W6
AVDD_AU33
Y6
VDDP
AA6
AVDD_PLL
W7
DVDD_NODIE
Y4
AVDD_DDR0_C
J14
AVDD_DDR0_D_1
J15
AVDD_DDR0_D_2
J16
AVDD_DDR0_D_3
K16
AVDD_DDR1_C
J17
AVDD_DDR1_D_1
L16
AVDD_DDR1_D_2
L17
AVDD_DDR1_D_3
M16
GND_EFUSE
J8
TEST
K8
GND_91
R19
GND_92
R23
GND_93
T23
GND_94
U5
GND_95
U6
GND_96
V3
GND_97
V4
GND_98
V11
GND_99
V15
GND_100
V16
GND_101
V17
GND_102
V18
GND_103
V19
GND_104
V20
GND_105
V21
GND_106
W1
GND_107
W2
GND_108
W11
GND_109
W15
GND_110
W17
GND_111
W18
GND_112
W20
GND_113
W21
GND_114
W22
GND_115
Y7
GND_116
AA7
GND_117
AB6
GND_118
AB7
GND_1 A15
GND_2 A17
GND_3 A20
GND_4 B14
GND_5 B16
GND_6 B18
GND_7 B21
GND_8 C11
GND_9 C12
GND_10 C13
GND_11 C20
GND_12 C23
GND_13 C25
GND_14 D23
GND_15 E17
GND_16 E18
GND_17 E20
GND_18 E23
GND_19 F4
GND_20 F5
GND_21 F6
GND_22 F7
GND_23 F18
GND_24 G4
GND_25 G5
GND_26 G6
GND_27 G7
GND_28 G10
GND_29 G12
GND_30 G15
GND_31 G19
GND_32 G20
GND_33 G24
GND_34 H7
GND_35 H10
GND_36 H12
GND_37 H13
GND_38 H14
GND_39 H15
GND_40 H19
GND_41 H25
GND_42 J1
GND_43 J7
GND_44 J12
GND_45 J13
GND_46 J19
GND_47 J20
GND_48 J24
GND_49 K12
GND_50 K13
GND_51 K14
GND_52 K15
GND_53 K18
GND_54 K19
GND_55 K25
GND_56 L8
GND_57 L12
GND_58 L13
GND_59 L14
GND_60 L15
GND_61 L18
GND_62 L19
GND_63 L20
GND_64 L24
GND_65 M3
GND_66 M8
GND_67 M12
GND_68 M13
GND_69 M14
GND_70 M15
GND_71 M17
GND_72 M18
GND_73 M19
GND_74 M24
GND_75 N1
GND_76 N7
GND_77 N13
GND_78 N14
GND_79 N15
GND_80 N16
GND_81 N17
GND_82 N18
GND_83 N19
GND_84 N20
GND_85 N25
GND_86 P13
GND_87 P14
GND_88 P19
GND_89 P21
GND_90 P24
R447
1M
X400
24MHz
4
GND_2
1 X-TAL_1 2 GND_1
3
X-TAL_2
C451 10pF
C452 10pF
4
L13
MAIN
2012-06-201
7
DECAP FOR SOC
(HIDDEN - UCC)
<SOC_RESET>
AB3
Close to IC with width trace
VDDC : 2026mA
AVDD2P5:172mA
F4
MODEL OPTION
<Normal 2.5V>
<VDDC 1.05V>
HD
PIN NAME
FHD
MODEL_OPT_0
LOW
<Normal Power 3.3V>
AVDD_NODIE:7.362mA
HIGH
AVDD_DDR1:55mA
DECAP FOR SOC (HIDDEN - UCC)
<DDR3 1.5V> <STby 3.3V>
DECAP FOR SOC (HIDDEN - UCC)
MODEL_OPT_1
PIN NO.
AVDD_DDR0:55mA
<CHIP Config>
(I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)
B51_no_EJ : 4’b0000 Boot from 8051 with SPI flash
SB51_WOS : 4’b0001 Secure B51 without scramble
SB51_WS : 4’b0010 Secure B51 with scramble
MIPS_SPE_NO_EJ : 4’b0100 Boot from MIPS with SPI flash
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash
MIPS_WOS : 4’b1001 Secure MIPS without scramble
MIPS_WS : 4’b1010 Scerur MIPS with SCRAMBLE
<CHIP Config(LED_R/BUZZ)>
Boot from SPI CS1N(EXT_FLASH) 1’b0
Boot from SPI_CS0N(INT_FLASH) 1’b1
C4000,C4005,C4006 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE
C453 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE
C4001 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE
C4002 SHOULD NEAR MAIN IC
DECAP READY FOR TEST
DECAP FOR SOC
(HIDDEN - UCC)
AUDIO IN
AUDIO OUT
T2_I2C
I2S_I/F
for SYSTEM EEPROM
from CI SLOT
Internal demod out
DTV_IF
Close to MSTAR
Close to MSTAR
ANALOG SIF
TUNER_I2C
Close to MSTAR
NON_A_DEMODE
AGC 1.25V
100 OHM SERIAL
A_DEMODE 0ohm
*H/W opt :
ETHERNET
<ANALOG & DIGITAL INPUT> <HDMI& SOUND>
<GPIO& LVDS> <VCC &GND>
<PCM & CI>
#POWER FOR MAIN#
<HW_OPT>
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PCM_A[0]
PCM_A[4]
PCM_A[1]
PCM_A[7]
PCM_A[2]
PCM_A[6]
PCM_A[5]
PCM_A[3]
R573
22
/PF_CE1
RXA4+
RXACK+
AR519
22
OS
RXA2-
R579
2K
R542
10K
R565
1K
OS
RXA1+
RXA4-
RXB3+
RXB2+
PC_SER_DATA
R569
4.7K
READY
/PF_CE0
PC_SER_CLK
R516
100
RXA2-
+3.3V
RXBCK+
R515
4.7K
Commercial
R577 4.7K
RXB4-
RXA0+
/PF_WP
P_SDA
RXB0+
SPI_SCK
RXB2-
/PF_OE
RXB1+
+3.3V_ST
+3.3V_ST
RXACK+
KEY1
RXA4-
RXB2-
RXB2+
R574
22
RXB1-
PF_ALE
+3.3V
R518
100
RXBCK+
RXB3-
RXA1+
RXB0-
PCM_A[0-7]
KEY2
R517
100
P503
TF05-51S
HD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
R556
3.3K
OS
RXB3-
C555
0.1uF
OS
SPI_SDO
/FLASH_WP
R514
22
I2C_SDA
+5V
RXA0-
RXA4+
IC505
W25Q80BVSSIG
Winbond_OS
3
%WP[IO2]
2
DO[IO1]
4
GND
1
CS
5DI[IO0]
6CLK
7HOLD[IO3]
8VCC
RXA1-
C556
0.1uF
R540
10K
RXB1-
+3.3V_ST
SPI_SDI
LD500
+3.3V_ST
RXA3+
RXB4+
R575
33
P500
104060-8017
FHD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
/PF_WE
RXA3-
/F_RB
RXBCK-
RXB3+
/SPI_CS
RXA3+
RXA2+
RXA0-
Q500
MMBT3904(NXP)
@optio
E
B
C
+3.3V_ST
R567
1K
OS
RXA0+
+5V
IR
C517
10pF
50V
RXA2+
C552
0.1uF
RXACK-
LED_RED
DISP_EN
RXA3-
C520
10pF
50V
RXB0-
R568
4.7K
OS
R564
10K
+3.3V
RXACK-
RXA1-
RXB4+
AR518
22
OS
RXB0+
I2C_SCL
C554
10uF10V
OS
RXBCK-
RXB4-
R512 4.7K
P_SCL
R513 4.7K
C550
0.1uF
OS
RXB1+
R578
47K
D500
MMBD6100
A2
C
A1
C535
0.1uF
16V
C534
0.1uF
16V
SPI_SCK
/FLASH_WP
R581
33
READY
R580
10K
READY
SPI_SDO
IC506
MX25L6406EMI-12G
READY
3
NC_1
2
VCC
4
NC_2
1
HOLD#
6
NC_4
5
NC_3
7
CS#
8
SO/SIO1 9WP#
10 GND
11 NC_5
12 NC_6
13 NC_7
14 NC_8
15 SI/SIO0
16 SCLK
SPI_SDI
/SPI_CS
+3.3V_ST
C557
0.1uF
READY
+3.3V_ST
C547
0.1uF
16V
P501
12507WR-06L
1
2
3
4
5
6
7UART_RXD
R520 0
R519 0
UART_TXD
P_SDA
PC_SER_CLK
PC_SER_DATA
P_SCL
IC503-*2
M24256-BRMN6TP
ST_OS
3
E2
2
E1
4
VSS
1
E0
5SDA
6SCL
7WC
8VCC
IC503-*1
AT24C256C-SSHL-T(Cu)
ATMEL_OS
3
A2
2
A1
4
GND
1
A0
5SDA
6SCL
7WP
8VCC
IC503-*3
AT24C512C-SSHD-T
ATMEL_NON-OS
3
A2
2
A1
4
GND
1
A0
5SDA
6SCL
7WP
8VCC
IC503
M24512-RMN6TP
ST_NON_OS
3
E2
2
E1
4
VSS
1
E0
5SDA
6SCL
7WC
8VCC
IC505-*3
MX25L6406EM2I-12G
MX_NON-OS
3
WP
2
SO/SIO1
4
GND
1
CS
5SI/SIO0
6SCLK
7HOLD
8VCC
IC505-*1
MX25L8006EM2I-12G
MX_OS
3
WP#
2
SO/SIO1
4
GND
1
CS#
5SI/SIO0
6SCLK
7HOLD#
8VCC
IC505-*2
W25Q64FVSSIG
Winbond_NON-OS
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5DI[IO0]
6CLK
7%HOLD[IO3]
8VCC
C518
470pF
READY
C519
470pF
READY
D501
20V
D503 20V D504 20V
D505
20V
D502
20V
IC504
H27U1G8F2CTR-BC
26 NC_17
27 NC_18
28 NC_19
29 I/O0
30 I/O1
31 I/O2
32 I/O3
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VCC_2
38 NC_23
39 NC_24
40 NC_25
41 I/O4
42 I/O5
43 I/O6
44 I/O7
45 NC_26
46 NC_27
47 NC_28
48 NC_29
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
R/B
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
IC504-*1
TC58NVG0S3ETA0BBBH
Toshiba_OS
26 NC_17
27 NC_18
28 NC_19
29 I/O1
30 I/O2
31 I/O3
32 I/O4
33 NC_20
34 NC_21
35 NC_22
36 VSS_2
37 VCC_2
38 NC_23
39 NC_24
40 NC_25
41 I/O5
42 I/O6
43 I/O7
44 I/O8
45 NC_26
46 NC_27
47 NC_28
48 NC_29
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
RY/BY
4
NC_4
5
NC_5
25 NC_16 24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
R522
0
READY
R521
0
READY
Memory.LVDS,IR
L13
5
2012-06-01
NAND Flash
1GBit
LVDS
Key/IR
* LCI: LVDS Connection Indicator
7
NON OS
OS:256KB 
NON_OS:512KB
NVRAM
SERIAL FLASH
NON_OS:64MB
OS:8MB
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_AMP
C620
10uF
25V
C615
10uF
10V
C685
330pF
50V
+5V
AUD_LRCH
R637
39
C677
0.1uF
16V
R618
240
FNIM
AC_DET
L611
10.0uH
Coil_TAIYO
R620
1
FNIM
+1.26V_VDDC
R670
0.1uF
16V
C680
0.1uF
50V
C687
0.1uF
50V
R675
1
IC608
AP1117E33G-13
OUT
IN ADJ/GND
L616
CIS21J121
L600
120
R667
0.1uF
16V
READY
SPK_R+
AMP_SCL
P_17V
R662
1
R612
1
+3.3V_AMP
R641
4.7K
C613
10uF
25V
READY
Q604
ZXMP3F30FHTA
G
D S
+3.3V
C674
33pF
50V
READY
R659
10K
C617
10uF
6.3V
C618
10uF
6.3V
C614
10uF
10V
FNIM
C688
0.22uF
50V
L603
10.0uH
Coil_GET
R636
39
SPK_L+
+1.5V_DDR
+5V
C606
0.1uF
16V
+5V
C601
0.1uF
16V
L614
10.0uH
Coil_TAIYO
AR600
100
R632
39 L602 10.0uH
Coil_GET
C624
1uF
10V
5V_ON
C691
0.22uF
50V
C621
0.1uF
50V
SPK_L-
+1.25V_TU
R640
4.7K
AMP_RESET_N
AMP_SDA
L610
10.0uH
Coil_GET
C626
3300pF
50V
+5V_ST
C679
0.1uF
50V
+3.3V_AMP
+3.3V_AMP
+3.3V_ST
R621
1
C675
33pF
50V
READY
C600
10uF
10V
C694
0.22uF
50V
C698
1000pF
50V
C630
0.1uF
16V
L612
10.0uH
Coil_TAIYO
+5V
L609
10.0uH
Coil_GET
Q603
MMBT3904(NXP)
E
B
C
+1.8V_TU
C625
10uF
6.3V
FNIM
SPK_L+
L615
10.0uH
Coil_TAIYO
R671
10K
READY
C692
0.22uF
50V
IC604
AZ1117BH-ADJTRE1
OUTPUT
INPUT ADJ/GND
+3.3V_DDR
+5V_ST
P601
WAFER-ANGLE
1
2
3
4
AUD_SCK
R652
22
+2.5V
C678
0.1uF
16V
IC602
AP1117EG-13
FNIM
ADJ/GND
OUTIN
R633
39
RL_ON
C607
0.1uF
16V
P600
SMAW200-H18S1
14
9
4
18
13
8
3
17
12
7
2
16
11
6
1
15
10
5
19
R600
10K
C689
0.22uF
50V
C672
0.1uF
16V
IC603
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5GND
6SW
7VBST
8VIN
9
[EP]GND
R653
22
AMP_MUTE
C684
330pF
50V
C616
10uF
10V
C690
0.1uF
50V
L601
BLM18PG121SN1D C697
1000pF
50V
C610
0.1uF
16V
R614
220
5%
AUD_LRCK
R657
10K
READY
SPK_R-
C631
10uF
6.3V
P_17V
C686
1uF
50V
C696
1000pF
50V
SPK_R-
+5V
+3.3V
C693
0.22uF
50V
SPK_R+
R615 1 FNIM
C699
1000pF
50V
C605
10uF
10V
AUD_MASTER_CLK
RL_ON
C681
1uF
50V
R613
100
5%
+5V_ST
RL_ON
C673
2.2uF
10V
IC613
AZ1117BH-ADJTRE1
OUTPUT
INPUT ADJ/GND
SPK_L-
+3.3V_ST
C619
10uF
6.3V
C608
10uF
10V
C695
68uF
35V
IC600
AP2121N-3.3TRE1
1
GND
2VOUT 3
VIN
C612
10uF
6.3V
R664
10K
1/16W
5%
R609
100
+5V_ST
VS_DET
VS_ON
+3.3V_TU
L606
120-ohm
2A
L605
2.2uH
L604
120
R611
33
C629
10uF
16V
C650
10uF
16V
C609
10uF
16V
R648
100
C623
100pF
50V
C628
0.1uF
25V
+3.3V_ST
R624 15K
READY
R628
4.7K
+3.3V_AMP
17V_DET
R617
33K
1%
R619
51K
1%
R601
10K
READY
R606 4.7K
+5V
R607
10K
READY
C611
10uF
10V
IC605
AP1117E33G-13
OUT
IN ADJ/GND
C627
10uF
6.3V
+5V
R608
1
R673
200
1%
R674
1K
1%
+3.3V_DDR
R639
10K
C622
0.1uF
R604
4.7K
IC606
STA380BWF
1 VCC_REG
2 VSS_REG
3 OUT2B
4 GND2
5 VCC2
6 OUT2A
7 OUT1B
8 VCC1
9 GND1
10 OUT1A
11 VDD_REG
12 GND_REG
13 NC_1
14 NC_2
15 NC_3
16 NC_4
17 NC_5
18 NC_6
19 NC_7
20 NC_8
21 NC_9
22 NC_10
23 NC_11 24 NC_12
25
NC_13 26
NC_14 27
NC_15 28
VDDDIG1 29
GNDDIG1 30
FFX3A 31
FFX3B 32
EAPD/FFX4A 33
TWARNEXT/FFX4B 34
VREGFILT 35
AGNDPLL 36
MCLK
37
BICKI
38
LRCKI
39
SDI
40
RESET
41
PWDN
42
INTLINE
43
SDA
44
SCL
45
SA
46
TESTMODE
47
GNDDIG2
48
VDDDIG2
49
[EP]
C602
2.2uF
10V
READY
C603
10uF
16V
IC601
TJ1118S-2.5
1
GND
2OUT 3
IN
C632
2pF
50V
READY
D600
5V
READY
C633
1000pF
50V
C634
10uF
6.3V
C604
1uF
10V
Power,AMP
L13
6
2012-06-01
SPEAKER_R
SPEAKER_L
+5V->+1.8V_TU
<Power Wafer>
R1
R1
--> +1.5V_DDR
R1
+5V->+2.5V
Vout=0.765*(1+R1/R2)
Vout=1.25*(1+R2/R1)
+5V->+1.25V_TU
+5V_ST --> 3.3Vst
+5V->+3.3V
->+3.3V_TU
Vout=1.25*(1+R2/R1)
R2
R1
R2
R2
5V_STBY --> MULTI 5V1.26V Core
R2
3A
3A
300mA
200mA
400mA80mA
600mA
400mA
7
600mA
+5V->+3.3V_DDR
POWER & AMP
<ST-BY>
<MUTI>
<AUDIO AMP>
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR_256
2011/06/03
12
GP4L_S7LR2
AVDD_DDR0
A_MA5
C1215 0.1uF
AVDD_DDR0
B-MA1
R1205
1K 1%
B-MA5
B_MA8
A_MA0
B-MDQSUB
A_MA10
C1236 0.1uF
OS
R1231
10K
C1202
1000pF
A-MA12
B-MDQU3
B_MA2
A-MBA1
B-MDQL2
B-MA0
A-MVREFDQ
A-MCKE
A-MDML
A_MA11
A_MODT
A_MRESETB
C1229 0.1uF
OS
B-MA2
B-MODT
B-MCKB
A-MBA0
B_MBA2
B-MRASB
B-MBA0
A-MA7
A-MDQL7
A-MA13
A_MA14
B-MA11
A_MBA0
B-MDQL5
A-MCASB
C1204
1000pF
B-MRESETB
C1232 0.1uF
OS
B-MRASB
B-MVREFDQ
A-MA8
A-MDMU
B-MA9
A-MA12
R1203
240
1%
B-MA4
+1.5V_DDR
B-MVREFCA
C1247
1000pF
OS
AVDD_DDR0
C1248
0.1uF
OS
B-MDQU4
A-MDQSLB
A-MRASB
B-MDQU2
B_MA1
B-MA14
C1230 0.1uF
OS
A-MDQU7
A_MA6
A-MA2
B-MDQL1
A-MBA2
AVDD_DDR0
R1204
1K 1%
R1226
240
1%
OS
A-MVREFCA
B-MDMU
C1210 0.1uF
A-MDQSU
L1202
CIC21J501NE
B_MA12
A_MBA1
AVDD_DDR0
B-MBA2
B-MA3
A-MRESETB
B-MDQU7
B-MA12
A-MDQL1
R1237
56
1%OS
B-MDQSU
A-MDQU1
R1238
56
1%
OS
R1227
1K 1%
OS
B-MVREFDQ
A-MDQL0
B-MA13
C1209
0.01uF
50V
B_MA0
A-MDQL6
B-MA11
B_MCASB
C1227 10uF
OS
B_MA10
AVDD_DDR0
A-MODT
C1213 0.1uF
B_MCKE
C1234 0.1uF
OS
B-MA1
R1225
1K 1%
OS
A-MCASB
B-MDQL3
B-MCK
A-MODT
B-MA8
A-MDQL4
A_MCASB
A-MDQU2
C1233 0.1uF
OS
B_MA13
A-MA7
C1207 0.1uF
B-MCASB
B-MDQU5A-MDQU5
B-MDQL6
B_MRESETB
A-MA1
B_MA9
A-MDQU6
A_MRASB
B-MA10
C1238
1uF
C1249
1000pF
OS
C1231 0.1uF
OS
B-MDQSLB
A_MA2
B-MA7
A-MA13
A-MDQL5
B_MWEB
A-MA0
B-MDQU6
A-MA14
A-MCKB
A-MDQU4
R1232
10K
OS
A-MA11
A-MA11
C1218
1uF
B_MA11
R1236 56
1%
B-MDQSL
A-MDQU0
B-MBA2
A-MA5
B-MWEB
R1202
1K 1%
C1235 0.1uF
OS
R1201
1K 1%
B-MBA0
A-MDQL3
B-MDML
A-MRESETB
A-MWEB
B-MCKE
B-MA8
A-MA4
A-MBA1
R1228
1K 1%
OS
B-MDQL7
AVDD_DDR0
A-MA6
B_MBA0
B-MCKE
A-MA14
A-MA6
B-MBA1
B-MDQL0
A_MA9
B-MCASB
C1214 0.1uF
C1205 10uF
C1203
0.1uF
B-MA3
R1224
1K 1%
OS
C1250
0.1uF
OS
A_MA3
B-MA6
B-MA0
AVDD_DDR0
B_MRASB
A_MA7
A-MCK
A-MA5
B-MA10
B_MA7
B_MA5
B-MDQU1
B-MVREFCA
C1216 0.1uF
B-MA9B_MBA1
A-MDQSUB
C1251
10uF
A-MA2
B_MA4
AVDD_DDR0
A-MA3
C1212 0.1uF
C1241
1uF
A-MVREFCA
A-MA10
A-MVREFDQ
B-MA2
A-MA1
B-MA4
B_MA14
A-MA0
B-MA12
B-MA7
A_MWEB
C1211 0.1uF
C1228 0.1uF
OS
A-MA9
C1208 0.1uF
A-MA4
A_MBA2
A-MDQL2
B-MA6
A_MA4
A-MA9
A_MA12
A_MA8
C1201
0.1uF
A-MDQU3
B-MWEB
B_MA6
A_MCKE
A-MBA0
A-MWEB
B-MBA1
C1240
0.01uF
50V
OS
B-MDQU0
B-MDQL4
B-MRESETB
B-MODT
A-MA3
A-MBA2
A-MA8
R1235 56
1%
B-MA14
C1219
1uF
A-MA10
B_MODT
B-MA5
A_MA13
B-MA13
A-MCKE
A-MDQSL
A-MRASB
B_MA3
A_MA1
K4B1G1646G-BCK0
IC1201
SS_1G_1600
EAN61836301
A0 N3
A1 P7
A2 P3
A3 N2
A4 P8
A5 P2
A6 R8
A7 R2
A8 T8
A9 R3
A10/AP L7
A11 R7
A12/BC N7
A13 T3
NC_5 M7
BA0 M2
BA1 N8
BA2 M3
CK J7
CK K7
CKE K9
CS L2
ODT K1
RAS J3
CAS K3
WE L3
RESET T2
DQSL F3
DQSL G3
DQSU C7
DQSU B7
DML E7
DMU D3
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
DQU0 D7
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B1G1646G-BCK0
IC1202
OS_SS_1G_1600
EAN61836301
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
AR1214 56
AR1225 56
OS
AR1223 56
AR1219 56 AR1204 56
OS
AR1211 56
OS
AR1212 56
OS
AR1209 56
OS
AR1210 56
OS
AR1202 56
OS
AR1218 56
AR1208 56
OS
AR1221 56
AR1203 56
OS
AR1220 56
AR1215 56
AR1206 56
OS
AR1213 56
AR1216 56 AR1207 56
OS
AR1217 56
AR1205 56
OS
AR1222 56
AR1224 56
A_MA8
A_MA5
A_MA6
A_MA10
A_MA3
A_MA0
A_MA1
A_MA11
A_MA14
A_MA9
A_MA2
A_MA4
A_MA12
A_MA7
A_MA13
B_MA3
B_MA2
B_MA5
B_MA8
B_MA4
B_MA6
B_MA13
B_MA7
B_MA9
B_MA10
B_MA11
B_MA12
B_MA1
B_MA0
B_MA14
A-MDQL7
A-MDQL6
A-MDQL2
A-MDQL5
A-MDQL3
A-MDQL4
A-MDQL1
A-MDQL0
A-MDQU2
A-MDQU0
A-MDQU4
A-MDQU5
A-MDQU7
A-MDQU1
A-MDQU3
A-MDQU6
A_MCASB
A_MRASB
A_MWEB
A-MDML
A-MDMU
A_MODT
A_MBA0
A_MBA1
A_MBA2
A_MRESETB
A_MCKE
A-MCK
A-MCKB
A-MDQSLB
A-MDQSL
A-MDQSUB
A-MDQSU
B-MDQL2
B-MDQL6
B-MDQL5
B-MDQL7
B-MDQL0
B-MDQL3
B-MDQL4
B-MDQL1
B-MDQU5
B-MDQU7
B-MDQU1
B-MDQU4
B-MDQU3
B-MDQU2
B-MDQU0
B-MDQU6
B_MCASB
B_MRASB
B_MWEB
B-MDML
B-MDMU
B_MODT
B_MBA2
B_MBA1
B_MBA0
B_MRESETB
B_MCKE
B-MCK
B-MCKB
B-MDQSLB
B-MDQSL
B-MDQSUB
B-MDQSU
IC400
LGE2111C-MS (PDP_13_MS10)
MS10 A_DDR3_A0
F9
A_DDR3_A1
E10
A_DDR3_A2
G9
A_DDR3_A3
C14
A_DDR3_A4
F11
A_DDR3_A5
A14
A_DDR3_A6
F10
A_DDR3_A7
C15
A_DDR3_A8
D11
A_DDR3_A9
C16
A_DDR3_A10
G13
A_DDR3_A11
E11
A_DDR3_A12
F12
A_DDR3_A13
B15
A_DDR3_A14
D10
A_DDR3_DQL0
B23
A_DDR3_DQL1
B19
A_DDR3_DQL2
A23
A_DDR3_DQL3
C19
A_DDR3_DQL4
B24
A_DDR3_DQL5
C18
A_DDR3_DQL6
A24
A_DDR3_DQL7
A18
A_DDR3_DQU0
D15
A_DDR3_DQU1
F17
A_DDR3_DQU2
F14
A_DDR3_DQU3
E16
A_DDR3_DQU4
D14
A_DDR3_DQU5
D16
A_DDR3_DQU6
E14
A_DDR3_DQU7
F16
A_DDR3_CASZ
A12
A_DDR3_RASZ
B11
A_DDR3_WEZ
E9
A_DDR3_DQML
B20
A_DDR3_DQMU
D17
A_DDR3_ODT
A11
A_DDR3_BA0
B12
A_DDR3_BA1
G11
A_DDR3_BA2
B13
A_DDR3_RESET
G8
A_DDR3_MCLKE
F13
A_DDR3_MCLK
B17
A_DDR3_MCLKZ
C17
A_DDR3_DQSL
B22
A_DDR3_DQSBL
C22
A_DDR3_DQSU
A21
A_DDR3_DQSBU
C21
B_DDR3_A0 E22
B_DDR3_A1 G21
B_DDR3_A2 F20
B_DDR3_A3 E24
B_DDR3_A4 K20
B_DDR3_A5 F24
B_DDR3_A6 J21
B_DDR3_A7 F23
B_DDR3_A8 H22
B_DDR3_A9 G23
B_DDR3_A10 L21
B_DDR3_A11 G22
B_DDR3_A12 J22
B_DDR3_A13 G25
B_DDR3_A14 H20
B_DDR3_DQL0 P23
B_DDR3_DQL1 L25
B_DDR3_DQL2 R24
B_DDR3_DQL3 K23
B_DDR3_DQL4 T25
B_DDR3_DQL5 J23
B_DDR3_DQL6 T24
B_DDR3_DQL7 K24
B_DDR3_DQU0 N21
B_DDR3_DQU1 P22
B_DDR3_DQU2 L22
B_DDR3_DQU3 R21
B_DDR3_DQU4 P20
B_DDR3_DQU5 R22
B_DDR3_DQU6 M22
B_DDR3_DQU7 N22
B_DDR3_CASZ D24
B_DDR3_RASZ B25
B_DDR3_WEZ F22
B_DDR3_DQML L23
B_DDR3_DQMU R20
B_DDR3_ODT C24
B_DDR3_BA0 D25
B_DDR3_BA1 K22
B_DDR3_BA2 E25
B_DDR3_RESET E21
B_DDR3_MCLKE M20
B_DDR3_MCLK H23
B_DDR3_MCLKZ H24
B_DDR3_DQSL P25
B_DDR3_DQSBL N23
B_DDR3_DQSU N24
B_DDR3_DQSBU M23
IC400-*1
LGE2111C (PDP_13_None MS10)
NONE_MS10
A_DDR3_A0
F9
A_DDR3_A1
E10
A_DDR3_A2
G9
A_DDR3_A3
C14
A_DDR3_A4
F11
A_DDR3_A5
A14
A_DDR3_A6
F10
A_DDR3_A7
C15
A_DDR3_A8
D11
A_DDR3_A9
C16
A_DDR3_A10
G13
A_DDR3_A11
E11
A_DDR3_A12
F12
A_DDR3_A13
B15
A_DDR3_A14
D10
A_DDR3_DQL0
B23
A_DDR3_DQL1
B19
A_DDR3_DQL2
A23
A_DDR3_DQL3
C19
A_DDR3_DQL4
B24
A_DDR3_DQL5
C18
A_DDR3_DQL6
A24
A_DDR3_DQL7
A18
A_DDR3_DQU0
D15
A_DDR3_DQU1
F17
A_DDR3_DQU2
F14
A_DDR3_DQU3
E16
A_DDR3_DQU4
D14
A_DDR3_DQU5
D16
A_DDR3_DQU6
E14
A_DDR3_DQU7
F16
A_DDR3_CASZ
A12
A_DDR3_RASZ
B11
A_DDR3_WEZ
E9
A_DDR3_DQML
B20
A_DDR3_DQMU
D17
A_DDR3_ODT
A11
A_DDR3_BA0
B12
A_DDR3_BA1
G11
A_DDR3_BA2
B13
A_DDR3_RESET
G8
A_DDR3_MCLKE
F13
A_DDR3_MCLK
B17
A_DDR3_MCLKZ
C17
A_DDR3_DQSL
B22
A_DDR3_DQSBL
C22
A_DDR3_DQSU
A21
A_DDR3_DQSBU
C21
B_DDR3_A0 E22
B_DDR3_A1 G21
B_DDR3_A2 F20
B_DDR3_A3 E24
B_DDR3_A4 K20
B_DDR3_A5 F24
B_DDR3_A6 J21
B_DDR3_A7 F23
B_DDR3_A8 H22
B_DDR3_A9 G23
B_DDR3_A10 L21
B_DDR3_A11 G22
B_DDR3_A12 J22
B_DDR3_A13 G25
B_DDR3_A14 H20
B_DDR3_DQL0 P23
B_DDR3_DQL1 L25
B_DDR3_DQL2 R24
B_DDR3_DQL3 K23
B_DDR3_DQL4 T25
B_DDR3_DQL5 J23
B_DDR3_DQL6 T24
B_DDR3_DQL7 K24
B_DDR3_DQU0 N21
B_DDR3_DQU1 P22
B_DDR3_DQU2 L22
B_DDR3_DQU3 R21
B_DDR3_DQU4 P20
B_DDR3_DQU5 R22
B_DDR3_DQU6 M22
B_DDR3_DQU7 N22
B_DDR3_CASZ D24
B_DDR3_RASZ B25
B_DDR3_WEZ F22
B_DDR3_DQML L23
B_DDR3_DQMU R20
B_DDR3_ODT C24
B_DDR3_BA0 D25
B_DDR3_BA1 K22
B_DDR3_BA2 E25
B_DDR3_RESET E21
B_DDR3_MCLKE M20
B_DDR3_MCLK H23
B_DDR3_MCLKZ H24
B_DDR3_DQSL P25
B_DDR3_DQSBL N23
B_DDR3_DQSU N24
B_DDR3_DQSBU M23
IC400-*1
LGE2111C (PDP_13_None MS10)
PCMDATA0/GPIO126
AB17
PCMDATA1/GPIO127
AB19
PCMDATA2/GPIO128
Y16
PCMDATA3/GPIO120
AD15
PCMDATA4/GPIO119
AE15
PCMDATA5/GPIO118
AD14
PCMDATA6/GPIO117
AB15
PCMDATA7/GPIO116
AC16
PCMADR0/GPIO125
Y17
PCMADR1/GPIO124
AA16
PCMADR2/GPIO122
AB16
PCMADR3/GPIO121
AD16
PCMADR4/GPIO99
Y18
PCMADR5/GPIO101
AE20
PCMADR6/GPIO102
Y19
PCMADR7/GPIO103
AC20
PCMADR8/GPIO108
AB18
PCMADR9/GPIO110
AD17
PCMADR10/GPIO114
AC15
PCMADR11/GPIO112
AE17
PCMADR12/GPIO104
AA19
PCMADR13/GPIO107
AA18
PCMADR14/GPIO106
AC19
PCM_RESET/GPIO129
AA17
PCMIRQA_N/GPIO105
AD20
PCMIOWR_N/GPIO109
AC18
PCMOE_N/GPIO113
AE14
PCMIORD_N/GPIO111
AD18
PCMCE_N/GPIO115
AC17
PCMWE_N/GPIO197
AD19
PCMCD_N/GPIO130
AE21
PCMREG_N/GPIO123
AE18
PCMWAIT_N/GPIO100
W16
PCM2_CD_N/GPIO135
Y21
PCM2_RESET/GPIO134
Y20
PCM2_CE_N/GPIO131
AA20
PCM2_IRQA_N/GPIO132
AB22
PCM2_WAIT_N/GPIO133
AB20
NF_ALE/GPIO141
AD10
NF_WPZ/GPIO198
Y9
NF_CEZ/GPIO137
AA10
NF_CLE/GPIO136
Y10
NF_REZ/GPIO139
AB10
NF_WEZ/GPIO140
AC9
NF_RBZ/GPIO142
AC10
TS1DATA0/GPIO88 Y14
TS1DATA1/GPIO89 AA14
TS1DATA2/GPIO90 AD13
TS1DATA3/GPIO91 Y13
TS1DATA4/GPIO92 AA13
TS1DATA5/GPIO93 AD12
TS1DATA6/GPIO94 AC12
TS1DATA7/GPIO95 W10
TS1CLK/GPIO98 AB13
TS1VALID/GPI96 AC14
TS1SYNC/GPIO97 W13
TS0DATA0/GPIO77 AB12
TS0DATA1/GPIO78 AD11
TS0DATA2/GPIO79 W9
TS0DATA3/GPIO80 AE11
TS0DATA4/GPIO81 AB11
TS0DATA5/GPIO82 AE12
TS0DATA6/GPIO83 AC13
TS0DATA7/GPIO84 AB14
TS0CLK/GPIO87 AA11
TS0VALID/GPIO85 Y11
TS0SYNC/GPIO86 AC11
IP AC3
IM AD2
SIFP AD1
SIFM AD3
IF_AGC AC2
GPIO73 AB3
GPIO74 AC4
I2C_SCKM1/GPIO75 AE3
I2C_SDAM1/GPIO76 AE2
IC400-*1
LGE2111C (PDP_13_None MS10)
A_RX0N
F2
A_RX0P
G1
A_RX1N
G2
A_RX1P
G3
A_RX2N
H2
A_RX2P
H3
A_RXCN
F3
A_RXCP
F1
DDCDA_CK/GPIO23
H5
DDCDA_DA/GPIO24
H4
HOTPLUGA/GPIO19
H6
C_RX0N
AC6
C_RX0P
AD7
C_RX1N
AC7
C_RX1P
AD8
C_RX2N
AE8
C_RX2P
AC8
C_RXCN
AE6
C_RXCP
AD6
DDCDC_CK/GPIO27
AC5
DDCDC_DA/GPIO28
AE5
HOTPLUGC/GPIO21
AD5
HOTPLUGD/GPIO22
K6
CEC/GPIO5
R6
SPDIF_IN/GPIO152
B6
SPDIF_OUT/GPIO153
M7
AUL1 Y3
AUR1 AA2
AUL3 AA1
AUR3 AA3
AUL4 W3
AUR4 Y2
EARPHONE_OUTL AA9
EARPHONE_OUTR AB9
AUOUTL2 AB4
AUOUTR2 AB5
AUVRP Y5
AUVAG AA4
AUVRM AA5
I2S_IN_BCK/GPIO150 C10
I2S_IN_SD/GPIO151 B10
I2S_IN_WS/GPIO149 B9
I2S_OUT_BCK/GPIO156 A9
I2S_OUT_MCK/GPIO154 B8
I2S_OUT_WS/GPIO155 A8
I2S_OUT_SD/GPIO157 C9
IC400-*1
LGE2111C (PDP_13_None MS10)
PWM0/GPIO66
AA22
PWM1/GPIO67
Y22
PWM2/GPIO68
V24
PWM3/GPIO69
U23
PWM4/GPIO70
T22
PWM_PM/GPIO199
C7
SAR0/GPIO31
E7
SAR1/GPIO32
D7
SAR2/GPIO33
J6
SAR3/GPIO34
D1
SAR4/GPIO35
C1
PM_SPI_SCK/GPIO1
A5
PM_SPI_SDI/GPIO2
B5
PM_SPI_SDO/GPIO3
B4
PM_SPI_SCZ1/GPIO_PM[6]/GPIO12
C4
PM_SPI_SCZ2/GPIO_PM[10]/GPIO16
B3
PM_SPI_CZ0/GPIO_PM[12]/GPIO0
D3
DDCA_CK/UART0_RX
E2
DDCA_DA/UART0_TX
D2
UART1_RX/GPIO44
E5
UART1_TX/GPIO43
E4
UART2_RX/GPIO64
U24
UART2_TX/GPIO65
U25
PM_UART_TX/GPIO_PM[1]/GPIO7
D4
PM_UART_RX/GPIO_PM[5]/GPIO11
D5
I2C_SCKM2/DDCR_CK/GPIO72
AA21
I2C_SDAM2/DDCR_DA/GPIO71
AB21
GPIO_PM[0]/GPIO6
M5
GPIO_PM[2]/GPIO8
L7
GPIO_PM[4]/GPIO10
J4
GPIO_PM[8]/GPIO14
L5
GPIO_PM[9]/GPIO15
L6
GPIO_PM[11]/GPIO17
L4
LVB0M W24
LVB0P V23
LVB1M W23
LVB1P W25
LVB2M Y24
LVB2P Y25
LVBCKM AA24
LVBCKP Y23
LVB3M AB24
LVB3P AA23
LVB4M AB23
LVB4P AB25
LVA0M AC24
LVA0P AC25
LVA1M AD24
LVA1P AD25
LVA2M AC23
LVA2P AE24
LVACKM AD23
LVACKP AE23
LVA3M AD22
LVA3P AC22
LVA4M AD21
LVA4P AC21
GPIO36 N5
GPIO37 A6
GPIO38 M6
GPIO39 R4
GPIO40 P5
GPIO41 D6
GPIO42 M4
GPIO45 C8
GPIO46 C5
GPIO49 E6
GPIO50 E3
GPIO51 K5
GPIO52 B7
GPIO53 K7
GPIO54 J5
IC400-*1
LGE2111C (PDP_13_None MS10)
RIN0M
M1
RIN0P
M2
GIN0M
L3
GIN0P
L2
BIN0M
K2
BIN0P
K1
SOGIN0
K3
HSYNC0
J2
VSYNC0
J3
RIN1M
R3
RIN1P
R1
GIN1M
R2
GIN1P
P3
BIN1M
N3
BIN1P
N2
SOGIN1
P2
HSYNC1
R7
VSYNC1
R5
RIN2M
V1
RIN2P
V2
GIN2M
U3
GIN2P
U2
BIN2M
T2
BIN2P
T1
SOGIN2
T3
CVBS0
T5
CVBS1
T4
CVBS2
T6
VCOM
U4
CVBSOUT2
T7
RN A2
RP B2
TN B1
TP C2
LED0/GPIO55 A3
LED1/GPIO56 C3
USB1_DM AE9
USB1_DP AD9
HWRESET K4
IRIN/GPIO4 C6
XIN AE4
XOUT AD4
IC400-*1
LGE2111C (PDP_13_None MS10)
VDDC_1
P17
VDDC_2
R17
VDDC_3
R18
VDDC_4
T17
VDDC_5
T18
VDDC_6
U18
VDDC_7
J9
VDDC_8
J11
VDDC_9
P8
VDDC_10
R8
VDDC_11
U11
VDDC_12
V10
AVDDLV
U17
DVDD_DDR
P18
AVDD25_LAN
Y8
AVDD2P5_DADC
AA8
AVDD_MOD
AB8
AVDD25_PGA
AB1
AVSS_PGA
AB2
AVDD_NODIE
W4
AVDD_DMPLL
W5
AVDD_DVI_USB_MPLL
W6
AVDD_AU33
Y6
VDDP
AA6
AVDD_PLL
W7
DVDD_NODIE
Y4
AVDD_DDR0_C
J14
AVDD_DDR0_D_1
J15
AVDD_DDR0_D_2
J16
AVDD_DDR0_D_3
K16
AVDD_DDR1_C
J17
AVDD_DDR1_D_1
L16
AVDD_DDR1_D_2
L17
AVDD_DDR1_D_3
M16
GND_EFUSE
J8
TEST
K8
GND_91
R19
GND_92
R23
GND_93
T23
GND_94
U5
GND_95
U6
GND_96
V3
GND_97
V4
GND_98
V11
GND_99
V15
GND_100
V16
GND_101
V17
GND_102
V18
GND_103
V19
GND_104
V20
GND_105
V21
GND_106
W1
GND_107
W2
GND_108
W11
GND_109
W15
GND_110
W17
GND_111
W18
GND_112
W20
GND_113
W21
GND_114
W22
GND_115
Y7
GND_116
AA7
GND_117
AB6
GND_118
AB7
GND_1 A15
GND_2 A17
GND_3 A20
GND_4 B14
GND_5 B16
GND_6 B18
GND_7 B21
GND_8 C11
GND_9 C12
GND_10 C13
GND_11 C20
GND_12 C23
GND_13 C25
GND_14 D23
GND_15 E17
GND_16 E18
GND_17 E20
GND_18 E23
GND_19 F4
GND_20 F5
GND_21 F6
GND_22 F7
GND_23 F18
GND_24 G4
GND_25 G5
GND_26 G6
GND_27 G7
GND_28 G10
GND_29 G12
GND_30 G15
GND_31 G19
GND_32 G20
GND_33 G24
GND_34 H7
GND_35 H10
GND_36 H12
GND_37 H13
GND_38 H14
GND_39 H15
GND_40 H19
GND_41 H25
GND_42 J1
GND_43 J7
GND_44 J12
GND_45 J13
GND_46 J19
GND_47 J20
GND_48 J24
GND_49 K12
GND_50 K13
GND_51 K14
GND_52 K15
GND_53 K18
GND_54 K19
GND_55 K25
GND_56 L8
GND_57 L12
GND_58 L13
GND_59 L14
GND_60 L15
GND_61 L18
GND_62 L19
GND_63 L20
GND_64 L24
GND_65 M3
GND_66 M8
GND_67 M12
GND_68 M13
GND_69 M14
GND_70 M15
GND_71 M17
GND_72 M18
GND_73 M19
GND_74 M24
GND_75 N1
GND_76 N7
GND_77 N13
GND_78 N14
GND_79 N15
GND_80 N16
GND_81 N17
GND_82 N18
GND_83 N19
GND_84 N20
GND_85 N25
GND_86 P13
GND_87 P14
GND_88 P19
GND_89 P21
GND_90 P24
H5TQ1G63EFR-PBC
IC1201-*1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_7
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
H5TQ1G63EFR-PBC
IC1202-*1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_7
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
CLose to Saturn7M IC
CLose to DDR3 CLose to DDR3
CLose to Saturn7M IC
<NONE MS10>
CLose to DDR3
Copyright © 2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only