Linear Technology DC752A Quick setup guide

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DEMO MANUAL DC752A
Description
LTC2704
Quad 16-Bit VOUT Softspan DAC
DemonstrationcircuitDC752A-BfeaturestheLTC2704-16
Quad 16-bit SoftSpan™ VOUT DAC. This device features
six output ranges, 0V to 5V, 0V to 10V, ±5V, ±10V, ±2.5V
and –2.5V to 7.5V that are independently settable for each
channel.EachDAChasanoffsetadjustinputpinandacom-L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan and QuikEval are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
pensation pin to allow optimization of transient response.
Design files for this circuit board are available at
http://www.linear.com/demo
Figure 1. Connection Diagram
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DEMO MANUAL DC752A
Quick start proceDure
Connect a clean ±15V power supply to the turret posts at
the top of the DC752A board. Connect J1 to a DC590 USB
serial controller using the supplied 14-conductor ribbon
cable. Connect DC590 to a host PC with a standard USB
A/Bcable. Run the QuikEval™ evaluation software supplied
withDC590ordownloaditfromwww.linear.com/software.
The correct control panel will be loaded automatically. The
softwareautomaticallysetstheLTC2704outputsaccording
to the entries in the control panel. A square wave option
is available to test settling time.
Additional software documentation may be available from
the Help menu item, as features may be added periodically.
Figure 2. Software Screenshot
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DEMO MANUAL DC752A
JUMPERS
JP8, JP9: Tie points for GND1 and GND2, respectively.
The default selection is TIE for both jumpers. This con-
nects all DAC grounds to the analog ground plane, and is
suitable for most applications that do not have large return
currents into the GND1 and GND2 turrets. Alternatively,
selecting REMOTE allows GND1 and GND2 to differ by as
much as ±300mV from analog ground.
JP1, JP2, JP4, JP6: Sense connections for DACA, DACB,
DACC, and DACD, respectively. Selecting TIE connects
OUTFx (output force) output directly to OUTSx (output
sense). Selecting REMOTE allows for remote sensing of
the output voltage. This also allows a power gain stage
such as the LT1970 to be added with no degradation of
accuracy.
JP3 (REF1): Voltage reference selection for DACA and
DACB, either 5V for the onboard LT1236 reference or
REMOTE if an external reference source is connected to
the REF1 turret post.
JP5 (REF2): Voltage reference selection for DACC and
DACD, either 5V for the onboard LT1236 reference or
REMOTE if an external reference source is connected to
the REF2 turret post.
JP10 (VOSA), JP12 (VOSB), JP11 (VOSC), JP13 (VOSD):
offset adjustment selection for DACA, DACB, DACC, and
DACD, respectively. If no offset adjustment is required,
select GND. Selecting ADJ connects the offset pin to the
associated 10-turn pot, allowing adjustment of the DAC’s
offset.
JP7: Select source for 5V VCC supply. Normally this should
be left in the REF position for lowest noise operation. The
REG position selects the 5V regulated supply from the
14-pin QuikEval connector. To apply an external supply,
remove JP7 completely.
ANALOG CONNECTIONS (TURRET POSTS)
OUTFA, OUTFB, OUTFC, OUTFD: DAC voltage outputs.
OUTSA, OUTSB, OUTSC, OUTSD: DAC feedback inputs.
The LTC2704 RFB inputs have a nominal 10k resistance,
so resistance between this point an the load or buffer
output must be kept low.
REF1,REF2:DAC Reference voltage. If theonboardLT1236
references are selected, the voltage may be measured at
these points. If a remote reference is selected, then an
external reference must be applied to these points.
REFM1, REFM2: Inverted reference output from the
LTC2704.Donotdrivethesepointswithanexternalsource.
POWER AND GROUND CONNECTIONS
Analog Power: The +15V, –15V, and GND turret posts
are the analog supplies for the internal DAC amplifiers.
These should be connected to a well regulated, low noise
power supply.
VCC:Connection to VCC. See schematic and description
for JP7.
Grounding: Separate power and signal grounds are pro-
vided. Signal ground is connected to the exposed ground
planes at the top and bottom edges of the board, and to
the two turrets labeled AGND. Use signal ground as the
reference point for measurements and connections to
external circuits. Any large currents drawn from the DAC
outputs should be returned to the power ground turret
closest to pin 1 on the 14-pin header. In this situation,
GND1 and GND2 can be used to sense the ground voltage
attheload,compensating for return resistance between the
load and power ground return. The maximum difference
in voltage between the load and power ground should be
less than 300mV.
HarDware setup
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DEMO MANUAL DC752A
parts List
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 4 C1, C2, C3, C4 Cap., NPO 27pF 25V 5% AVX 06033A270JAT1A
2 5 C5, C6, C8, C10, C13 Cap., X7R 0.1µF 16V 20% AVX 0603YC104MAT2A
3 3 C7, C11, C12 Cap., X5R 4.7µF 6.3V 20% TDK C1608X5R0J475MT
4 2 C9, C14 Cap., X5R 4.7µF 25V 20% Taiyo Yuden TMK316BJ475ML
5 4 C15, C16, C17, C18 Cap., X7R 0.1µF 25V 10% Taiyo Yuden TMK107BJ104KA
6 4 D1, D3, D4, D5 Diode, Dual Switching Diode ON Semi. BAV99LT1
7 1 D2 LED, GRN Panasonic LN1351-C-TR
8 6 D6, D7, D8, D9, D10, D11 Schottky (Dual) Diode, BAT54S Zetex BAT54S
9 13 JP1-JP13 Headers, 3 Pins 2mm Ctrs. CommConn Con Inc. 2802S-03G2
10 13 XJP1-XJP13 Shunt, 2 Pins 2mm Ctrs. CommConn Con Inc. CCIJ2MM-138GW
11 1 J1 Headers, 14 Pin 2mm Ctrs. Molex 87331-1420
12 2 R2, R1 Res., Chip 10k 0.1W 5% AAC CR16-103JM
13 1 R3 Res., Chip 1k 0.06W 5% AAC CR16-102JM
14 3 R4, R5, R6 Res., Chip 4.99k 0.1W 1% AAC CR16-4991FM
15 4 R9, R10, R13, R14 Pot. 11 Turns 20k Bourns 3224W-1-203E
16 0 TP1, TP4, TP6, TP19, TP20 (Opt) Testpoint
17 20 TP2, TP3, TP5, TP7-TP18, TP21-TP25 Turret, Testpoint Mill Max 2308-2
18 1 U2 I.C., µPWR LDO Linear Technology Corp. LT1790ACS6-5
19 1 U3 EEPROM, Serial MICROCHIP, 24LC025-I /ST
20 2 U4, U5 I.C., Precision Ref. Linear Technology Corp. LT1236ACS8-5
21 1 U6 I.C., SoftSpan DAC Linear Technology Corp. LTC2704CGW-16
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DEMO MANUAL DC752A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
scHematic Diagram
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Quad 16-Bit Voltage Output,
Softspan DAC

LTC2704CGW-16
DC752A-A
DC752A-B
"Future Use"
U6
4
DEMO CIRCUIT 752A
Wednesday, August 09, 2006
1 1
RUDY B MARK T.
NONE
SCHEMATIC
C:\ORCADWIN\CAPTURE\752A\752A_00_REV4.DSN
SIZE DATE:
DWG NO. REV
SHEET OF
TITLE:
CONTRACT NO.
APPROVALS
DRAWN:
CHECKED: APPROVED: ENGINEER:
DESIGNER:
TECHNOLOGY
Fax: [phone] Milpitas, CA 95035
Phone: [phone]
1630 McCarthy Blvd.
LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCK
CS/LDSRO
SDI
WP VSS
VCC REF2
REF1
CLR
LDAC
FLT
CS/LD SDI SRO SCK
VOSD VOSC VOSA VOSB
REFM1
REFM2
VOSA VOSB
REF1 REFM1 RE FM2
REF2
VOSC VOSD
+5V
+7V
+15V
-15V
5VREF1
VS V S 5VREF2
VCC
5VREF2 5VREF1
-15V+15V
+5V
VCC
VCC
VCC
VS
+15V +7V
GND2
GND2
GND2
GND1 GND2
GND1
GND1
GND1
GND2
GND1
GND1 GND1
GND2 GND2
C13
0.1uF
D3
BAV99LT1
D5
BAV99LT1
TP25 REFM2
R3 1K
R5
4.99K
1%
C8 0.1uF
U4 LT1236ACS8-5
6
4
5
2VOUT
GND TRIM
VIN
TP12
OUTFD
JP9
TIE REMOTE
GND2
1 3 2
TP16 AGND
TP17 GND1
C3
(Opt)
TP11 OUTSD
TP21 +15V
TP7 OUTFB
TP1
JP7
REG
REF
LT1790
1 3 2
JP4 OUTC
REMOTE
TIE
1 3 2
CCW CW
R10
20K
C12 4.7uF
D9
BAT54S
3 21
U5 LT1236ACS8-5
6
4
5
2VOUT
GND TRIM
VIN
C1
(Opt)
TP10
OUTFC
TP22 PGND
U2 LT1790ACS6-5
6
1 2
4 3 5
VOUT
GND GND
VIN
DNC DNC
JP13
GND
ADJ
VOSD
1 3 2
JP6 OUTD
REMOTE
TIE
1 3 2
R6
4.99K
1%
TP8 OUTSC
JP8
TIE REMOTE
GND1
1 3 2
C4
(Opt)
TP23 -15V
C9 4.7uF
25V
TP18 GND2
D1
BAV99LT1
CCW CW
R13
20K
CCW CW
R14
20K
C17 1uF
25V
TP15 AGND
D7
BAT54S
3 21
TP9 REF1
TP20
TP5
OUTSB
CCW CW
R9
20K
C18 1uF
25V
U3
24LC025
1 2 3 4
8 7 6 5
A0 A1 A2
VSS
VCC WP SCL SDA
D10
BAT54S
3 21
C11
4.7uF
JP2 OUTB
REMOTE
TIE
1 3 2
C14
4.7uF
25V
TP4
D4
BAV99LT1
C7
4.7uF
TP24 REFM1
J1
1 3
2 4
5 6 7 8 9 10
11 13
12 14
 See Table
5 7 6 3 39 37 38 41 28 30 29 26 18 16 17 20
25
42
1
8
15
22
34
2
43 24 21
9
10 11 12 13 14 35 33 32 44 23
4 40 27 19
31
36
C1A
OUTSA
OUTFA
AGNDA
C1B
OUTSB
OUTFB
AGNDB
C1C
OUTSC
OUTFC
AGNDC
C1D
OUTSD
OUTFD
AGNDD
VP1
VP2
VM
VM
VM
VM
VCC REFG1
REF1 REF2 REFG2
LDAC
CS/LD SDI SRO SCK CLR FLT GND AGND REFM1 REFM2
VOSA
VOSB
VOSC
VOSD
VM
VM
C10
0.1uF
TP13 REF2
R2
10K
R4
4.99K
1%
JP11
GND
ADJ
VOSC
1 3 2
TP3
OUTFA
R1
10K
TP2
OUTSA
D6
BAT54S
3 21
C5
0.1uF
TP14 VCC
JP5
REMOTE
REF2
5V
1 3 2
JP10
GND
ADJ
VOSA
1 3 2
D11 BAT54S
3 21
C2
(Opt)
C15 1uF
25V
TP6
TP19
JP1 OUTA
REMOTE
TIE
1 3 2
C6
0.1uF
D8
BAT54S
3 21
D2 GRN FLT
JP3
REMOTE
REF1
5V
1 3 2
C16 1uF
25V
JP12
GND
ADJ
VOSB
1 3 2
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DEMO MANUAL DC752A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2013
LT 0613 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LT C ) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LT C for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LT C from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LT C assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LT C currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LT C applica-
tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
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