Linear Technology DC2491A Quick setup guide

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DEMO MANUAL DC2491A
DESCRIPTION
LT3045EDD
20V, 500mA, Ultralow Noise
Ultrahigh PSRR RF LDO Regulator
DemocircuitDC2491AfeaturestheLT
®
3045EDD,a500mA,
ultralow noise and ultrahigh power supply rejection
ratio(PSRR) low dropout (LDO) regulator with program-
mable current limit.
DC2491A operates over an input voltage range of 3.8V
to 20V. The LT3045 delivers a maximum output current
of 500mA. In addition to featuring ultralow noise and
ultrahigh PSRR, the regulator offers programmable power
good functionality as well as programmable current limit.
Current monitoring is also achieved by sensing the ILIM
pin voltage.
Built-in protection includes reverse battery protection,
reverse current protection, internal current limit with
foldback, and thermal limit with hysteresis.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
The LT3045 data sheet gives a complete description of the
device, operation and applications information. The data
sheet must be read in conjunction with this demo manual
for DC2491A. The LT3045EDD is assembled in a 10-lead
(3mm × 3mm) plastic DFN package with an exposed pad
on the bottom-side of the IC. Proper board layout is es-
sential for maximum thermal performance.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2491A
Specifications are at TA= 25°C
PARAMETER CONDITIONS MIN TYP MAX
Input Voltage Range (VIN) IOUT = 150mA, VOUT = 3.3V 3.8V 20V
Input Voltage Range (VIN) IOUT = 500mA, VOUT = 3.3V 3.8V 8.3V*
Output Voltage (VOUT) VIN = 5V, IOUT = 500mA 3.2V 3.3V 3.4V
Shutdown Input Current (IIN) JP1 = OFF, VIN = 5V 0.1μA
*The maximum input voltage for 500mA load current is set by the 60°C temperature rise of LT3045 on the demo circuit. Higher input voltage can be
reached if larger copper area or force-air cooling is applied. The output current is also limited by the differential of input and output voltage, please refer
the data sheet for details.

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DEMO MANUAL DC2491A
QUICK START PROCEDURE
Figure 1. Test Procedure Setup Drawing for DC2491A
DC2491A is easy to set up to evaluate the performance of
the LT3045EDD. Refer to Figure 1 for proper measurement
equipment setup and follow the procedure below.
1. Connect load between VOUT and GND terminals.
2. With power off, connect the input power supply to the
VIN and GND terminals.
3. Make sure the shunt of JP1 is at ON option.
4. Turn the input power supply on and make sure the
voltage is between 3.8V and 20V.
5. Refer to Application Notes AN70 and AN159 for mea-
suring output noise and PSRR.
6. With JP1 at USER SELECT option, R6 and R7 can be
used to set an accurate undervoltage lockout (UVLO)
threshold.
*The maximum output current will be limited by internal current limit based on differential voltage of input and output voltage, please refer to the data sheet.

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DEMO MANUAL DC2491A
Figure 2. Layer 3 of DC2491A
Best PSRR Performance: PCB Layout for Input Trace
For applications utilizing the LT3045 for post-regulating
switching converters, placing a capacitor directly at the
LT3045 input results in AC current (at the switching fre-
quency) to flow near the LT3045. Without careful attention
to PCB layout, this relatively high frequency switching cur-
rent generates an electromagnetic field (EMF) that couples
totheLT3045 output, thereby degrading its effectivePSRR.
While highly dependent on the PCB, the switching pre-
regulator, and the input capacitor size, amongother factors,
the PSRR degradation can easily be 30dB at 1MHz. This
degradation is present even if the LT3045 is de-soldered
from the board, because it effectively degrades the PSRR
of the PC board itself. While negligible for conventional low
PSRR LDOs, LT3045’s ultrahigh PSRR requires careful
attention to higher order parasitics in order to realize the
full performance offered by the regulator.
PCB LAYOUT
The LT3045 demo board alleviates this degradation in
PSRR by using a specialized layout technique. On layer3,
the input trace (VIN) is highlighted in red, with the return
path (GND) highlighted on the bottom layer together with
input capacitor C1. When an AC voltage is applied to the
input of the board, AC current flows on this path, thus
generating EMF. This EMF couples to output capacitor
C2 and related traces, making the PSRR appear worse
than it actually is. With the input trace directly above
the return path, the EMFs are in opposite directions,
and consequently cancel each other out. Making sure
these traces exactly overlap each other maximizes the
cancellation effect and thus provides the maximum
PSRR offered by the regulator.
Figure 3. Bottom Layer of DC2491A

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DEMO MANUAL DC2491A
Figure 5. Split Pads for C2 on Top Layer of DC2491A
Best AC Performance: PCB Layout for Output
Capacitor C2
For ultrahigh PSRR performance, the LT3045 bandwidth
is made quite high (~1MHz), making it very close to the
output capacitor’s self-resonance frequency (~1.6MHz).
Therefore, it is very important to avoid adding extra imped-
ance (ESL and ESR) outside the feedback loop. To that end,
minimize the effects of PCB trace and solder inductance
by Kelvin connecting OUTS and SET pin capacitor (CSET)
GND directly to output capacitor (C2) terminals using split
capacitor techniques. Pad 4 connects to the OUTS pin and
Pad 1 connects to the GND side of the SET pin capacitor.
With only small AC current flowing through these connec-
tions, the impact of solder joint/PCB trace inductance on
stability is eliminated. While the LT3045 is robust enough
not to oscillate if the recommended layout is not followed,
phase/gain margin and PSRR will degrade.
C
2
R
SET
C
SET
C1
OUT
IN
SET
LT3045
100μA
OUTS
PG
ILIM
GND
PGFB
EN/UV
V
OUT
V
IN
4
3
1
2
PCB LAYOUT
Figure 4. C2 and CSET Connections for Best Performance

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DEMO MANUAL DC2491A
BOARD PHOTO

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DEMO MANUAL DC2491A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 1 CIN CAP., ALUM, 22µF, 35V, 5mm × 5.4mm SUN ELECTRONIC INDUSTRIES CORP., 35CE22BSS
2 2 C1, C4 CAP., X7R, 4.7μF, 25V, 10% 1206 MURATA, GRM31CR71E475KA88L
3 1 C2 CAP., X5R, 10μF, 25V, 10% 1206 MURATA, GJ831CR61E106KE83L
4 1 R1 RES., CHIP, 200k, 1/16W, 5% 0603 VISHAY, CRCW0603200KJNED
5 1 R3 RES., CHIP, 33.2k, 1/8W, 1% 0603 VISHAY, CRCW060333K2FKEA
6 1 R5 RES., CHIP, 453k, 1/8W, 1% 0603 VISHAY, CRCW0603453KFKEA
7 1 R6 RES., CHIP, 49.9k, 1/8W, 1% 0603 VISHAY, CRCW060349K9FKEA
8 1 R7 RES., CHIP, 249Ω, 1/16W, 1% 0603 VISHAY, CRCW0603249RFKEA
9 1 U1 IC, LT3045EDD DFN 3mm × 3mm LINEAR TECH., LT3045EDD#PBF
Optional Electronic Components
1 0 C3, C5 (OPT) CAP., 1206
2 0 R2, R4 (OPT) RES., 0603
31 R8 RES., CHIP, 0Ω, 1/16W, 5% 0603 VISHAY, CRCW06030000Z0EA
Hardware
1 6 E1 – E6 TESTPOINT, TURRET, 0.094" PBF MILL-MAX, 2501-2-00-80-00-00-07-0
2 1 JP1 HEADER 3-PIN 0.079" DOUBLE ROW WURTH ELEKTRONIK, 62000621121
3 1 XJP1 SHUNT, 0.079" CENTER WURTH ELEKTRONIK, 60800213421
4 2 J1, J2 CONN, BNC, 5 PINS CONNEX, 112404
5 4 MH1 – MH4 STAND-OFF, NYLON 6.4mm WURTH ELEKTRONIK, 702931000

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DEMO MANUAL DC2491A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
1. ALL RESISTORS ARE 0603.
NOTE: UNLESS OTHERWISE SPECIFIED
*
SEE DEMO MANUAL
*
U1
LT3045EDD
IN
1
IN
2
EN/UV
3
PG
4
ILIM
5
OUT 10
OUTS 9
GND
8
SET 7
PGFB 6
GND
11
C3
OPT 1206
J2
MONITOR
OUTPUT NOISE
R7
249
R4
OPT
E6
GND
R5
453K
JP1
USER SELECT
OFF ON
EN/UV
1 2 3
5 6
4
C1
4.7uF 1206
25V
R1
200K
+
CIN
22µF
35V
35CE22BSS
C2
10uF
25V 1206
C5 OPT 1206
E2
GND
J1
MONITOR
INPUT RIPPLE
R8
0
E1
VIN
3.8V-20V
R2
OPT
R3 33.2K
R6
49.9K
E3
EN/UV
E4
PG
E5 3.3V, 500mA
VOUT
C4
4.7uF 1206
25V

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DEMO MANUAL DC2491A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2016
LT 0816 • PRINTED IN USA
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