
2
DEMO MANUAL DC239
NO-DESIGN SWITCHER
LTC1502CMS8-3.3
1
2
3
DC239 SCHEM
4
ON
SHDN
JP1
8
7
C1
1µF
R1
100Ω
6
5
V
IN
GND
C3
1µF
J3
V
IN
C2
10µF
C
OUT
10µF
J2
V
OUT
3.3V/10mA
J1
J4
C
IN
10µF
LTC1502-3.3
U1
C2
C1
+
C1
–
/SHDN
V
OUT
C3
+
C3
–
1
2
3
4
C2
C1
+
C1
–
/SHDN
GND
8
7
6
5
V
OUT
C3
+
C3
–
V
IN
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
REFERENCE
DESIGNATOR QUANTITY PART NUMBER DESCRIPTION VENDOR TELEPHONE
C1, C3 2 0603ZG105ZAT1A 1µF 10V Y5V Capacitor AVX (843) 946-0362
C2, COUT, CIN 3 1206ZG106ZAT1A 10µF 10V Y5V Capacitor AVX (843) 946-0362
JP1 1 2802S-03G2 3-Pin, 2mm Jumper Comm Con (626) 301-4200
J1, J2, J3, J4 4 2501-2 0.090 Turret Testpoint Mill-Max (516) 922-6000
R1 1 CR16-101JM 100Ω1/16W 5% Chip Resistor TAD (800) 508-1521
U1 1 LTC1502CMS8-3.3 MSOP Step-Up DC/DC IC LTC (408) 432-1900
1 CCIJ2mm-138-G 2-Pin 2mm Shunt Comm Con (626) 301-4200
PARTS LIST
OPERATIO
U
The LTC1502-3.3 uses a switched capacitor quadrupler
charge pump to produce a boosted output voltage. The
quadrupler charge pump consists of two voltage doubler
charge pumps (CP1 and CP2 on the Block Diagram)
cascaded in series. CP1 doubles the input voltage V
IN
, and
the CP1 output voltage is stored on external capacitor C2.
The C2 pin also serves as the input for doubler CP2, whose
output is stored on the output capacitor C
OUT
. Each
doubler is controlled by a 2-phase clock that is generated
in the timing-control circuit. On phase one of the clock, the
flying capacitors C1 and C3 are charged to their respective
input voltages. On phase two, each charged flying capaci-
tor is stacked on top of the input voltage and discharged
through an internal switch onto its respective output. This
sequence of charging and discharging the flying capaci-
tors (CP1 and CP2) continues at the free running oscillator
frequency (500kHz typ) until the output is in regulation.
Regulation is achieved by comparing the divided output
voltage to a fixed voltage reference. The charge pump
clocks are disabled when the output voltage is above the
desired regulation point set by COMP1. When the output
has dropped below the lower trip point of COMP1, the
charge pump clocks are turned back on until V
OUT
is
boosted back into regulation.
Enhanced Start-Up
Enhanced start-up capability is provided by the COMP2
circuitry. COMP2 compares the divided C2 voltage to the
input voltage, V
IN
. The COMP2 output disables the output
charge pump, CP2, whenever the divided C2 voltage is
lower than V
IN
. The CP2 output is thereby forced into a
high impedance state until the voltage on C2 has been
raised above V
IN
(the C2 pin should not be loaded for
proper start-up). This allows a higher internal gate drive
voltage to be generated (from the C2 pin) before the part’s
output (V
OUT
) is connected to a load. Hysteresis in COMP2
forces CP2 to be turned ON and OFF while C
OUT
is charged
Demo Board Schematic
SCHE ATIC A D PACKAGE DIAGRA S
U
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