Linear DC1339 User manual

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
1
DESCRIPTION
LTC2302
Demonstration circuit 1339 features the
LTC2302 low noise, 500ksps, 12-Bit, ADC.
The LTC2302 has an SPI compatible serial
interface that can be used to select channel
polarity and unipolar or bipolar settings.
DC1339A demonstrates the DC and AC
performance of the LTC2302 in conjunction
with the DC590B QuikEval and DC890B Fast
DAACS data collection boards. Use DC590B
to demonstrate DC performance such as
peak-to-peak noise and DC linearity. Use
DC890B if precise sampling rates are required
or to demonstrate AC performance such as
SNR, THD, SINAD and SFDR. Alternatively,
by connecting the DC1339A into a customer
application, the performance of the LTC2302
can be evaluated directly in that circuit.
Design files for this circuit board are
available. Call the LTC factory.
LTC is a trademark of Linear Technology Corporation
Figure 1. DC1339A Connection Diagram

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
2
DC890B QUICK START PROCEDURE
Connect DC1339A to a DC890B USB High
Speed Data Collection Board using connector
J2. Connect DC890B to a host PC with a
standard USB A/B cable. Apply 6V-9V DC to
the 6V-9V and GND terminals. Apply a low
jitter signal source to IN+ on connector J1.
Apply a low jitter clock with a maximum
frequency of 40MHz to connector J3. The clock
can be a sine wave or square wave with
maximum amplitude of 14dBm. Note that J3
has a 50Ωtermination resistor to ground,
which will prevent most logic from driving this
pin directly. Run the Fast DAACS software
(Pscope.exe version K51 or later) supplied with
DC890B or download it from www.linear.com.
Complete software documentation is available
from the Help menu. Updates can be
downloaded from the Tools menu. Check for
updates periodically as new features may be
added.
PSCOPE SOFTWARE CONFIGURATION
The Pscope software will recognize DC1339A
and configure itself automatically. The default
configuration is for IN+ with respect to IN- in
unipolar mode. Make sure that the jumpers are
set as shown in Figure 2. If bipolar mode is
desired, it will be necessary to change the
Pscope ADC configuration setting as well as
jumpers JP3 and JP5. From the front page of
the software select ADC Configuration from
the Configure menu. Select 12-Bits,
Alignment 12, FPGA Ld Serial 2308 Class, 1-
Channel. Do not check Positive Edge Clk.
Check Bipolar if the JP5 UNI jumper is set to
GND. An example of the ADC configuration
menu is shown in Figure 3. JP3 should be
changed from GND to VREF/2 in bipolar
mode, so that the minus input is biased
halfway between ground and Vref.
Click the Collect button (See Figure 4) to
begin acquiring data. Depending on which
board was previously used by Pscope it may
be necessary to press Collect a second time.
The Collect button then changes to Pause,
which can be used to pause data acquisition.
Figure 2. Jumper Settings Figure 3. User Configure Menu

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
3
DC590B QUICK START PROCEDURE
Connect DC1339A to a DC590 USB serial
controller using the supplied 14-conductor
ribbon cable. Connect DC590 to a host PC
with a standard USB A/B cable. Run the
evaluation software supplied with DC590 or
download it from www.linear.com. The correct
control panel will be loaded automatically.
Version K73 of QuikEval or higher should be
used for this board. Click the COLLECT button
to begin reading the ADC. Change the range
(unipolar or bipolar) by right clicking over the
range indicator in the display. See Figure 5.
HARDWARE SET UP
SIGNAL CONNECTIONS
J1 SMA connector for IN+. Limit input swings
to 0V-4.096V. For optimum performance, the
input should be band limited to the frequencies
of interest. See schematic for details.
J2 FastDAACS interface to DC890B. Do not
use J4 at the same time.
J3 Conversion Clock Input. This input has a
50Ωtermination resistor, and is intended to be
driven by a 14dBm sine or square wave. To
achieve full AC performance of this part, the
clock jitter should be kept under 20ps. This
input is capacitively coupled to a clock buffer
so that level shifting is not required. To run at
maximum conversion rate, apply a 40MHz
signal to this connector. J3 is used only for
DC890B. DC590B generates its own clock
signal.
J4 Quick Eval interface to DC590B. Do not use
J2 at the same time. This connector can also
be used to drive the ADC directly. See
schematic for details.
JUMPERS
JP1 (OVDD) connects the OVDD pin of the
ADC to 5V or to an external voltage. The SDO
pin swings from ground to OVDD.
JP2 contains CONV, SDI, SCK and a buffered
SDO signal. This connector is intended to
monitor these signals. For for those who want
to drive the ADC directly use J4.
JP3 (IN-) selects whether the IN- pin of the
ADC is to be cleanly grounded near the ADC or
connected to VREF/2.
JP4 (VREF) selects onboard or external
reference for the ADC
JP5 (DIN Word) selects the channel
configuration and unipolar/bipolar settings of
the ADC. (JP5 is used by the DC890B only. It
is ignored by the DC590B.)
GROUNDING AND POWER CONNECTION
Connect a 6V to 9V power supply to the 6-
9VDC and GND posts when using DC890B. If
the DC590B is used it will provide power to the
DC1339.

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
4
Figure 4. DC1339A Pscope Screenshot

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
5
Figure 5. DC1339A QuikEval Screen Shot

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
6
C14
1uF
C33
0.1uF
R5
3.01K
1%
5V
E10
GND
R3
49.9
1%
(Opt)
5V
E8
5V
U6
LT1790ACS6 4.096
6
12
4
35
VOUT
GNDGND
VIN
DNCDNC
C34
0.1uF
U3
SN74AHCT1G04DCKT
42
5
3
C6
0.1uF
CONV_AT_ADC
E7
2.5V
C12
1uF
J1
IN+
0V 4.096V
C8
1uF
16V
E4
VREF
R8
10
C1
10uF
6.3V
MUX
EXPOSED
CONVST
SDO
SCK
SDI
VREF
GND
OVDD
VDD
PAD
IN+
IN
LTC2302CDD
U1
2
1
9
8
4
5
103
6711
U4
LT1761ES5 2.5
1
2
43
5
IN
GND
ADJSHDN
OUT
2.5V
5V
JP1
EXT
OVDD
5V
1
3
2
E2
IN+
5V
JP4
EXT REF
VREF
4.096V
1
3
2
R1
100
C15
47uF
10V
E5
VREF/2
R7
4.99K
1%
C16
1uF
16V
E6
EXT REF
U2
NC7SVU04P5X
42
5
3
SDO_AT_590
JP2
DO
CLK
CNV
DI
1
3
2
4
65
7 8
E1
OVDD
E9
6V 9V
E3
IN
R4
100
C11
0.01uF
SCK_AT_ADC
C17
10uF
C7
10uF
6.3V
5V
U5
LT1761ES5 5
1
2
43
5
IN
GND
ADJSHDN
OUT
SDI_AT_ADC
C4
47pF
SDO_AT_BUF
C2
0.1uF
JP3
GND
IN
VREF/2
1
3
2
C13
0.01uF
C10
0.1uF
C5
47pF
2.5V
C3
0.1uF
R2
301 1%
C9
10uF
6.3V
R6
4.99K
1%

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339
LOW NOISE, 500KSPS, 12-BIT ADC
7
5V
C27
0.1uF
SHDN#
R11
49.9
1%
+
-
U13
LT1719CS6
3
1
5
4
26
+
-
U11
LT1719CS6
3
1
5
4
26
R20
4.99K
1%
7V
R21
4.99K
1%
SHDN
+
-
U12
LT1719CS6
3
1
5
4
26
R12
1K
R24
2.49K
1%
5V
SHDN
R13
33
J2
EDGE CON 100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
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60
62
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66
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70
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78
80
82
84
86
88
90
92
94
96
98
100
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
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59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
SHDN
E17
SCK
C22
0.1uF
U8
NC7SVU04P5X
42
5
3
OE
AB
U9
NC7SZ66P5X
1
3 5
2
4
CONV_AT_ADC
C19
0.1uF
C24
0.1uF
R23
2.49K
1%
SDI_AT_ADC
2.5V
C23
0.1uF
R14
33
E12
CNVCLK
R19
4.99K
1%
1.25V E13
MISO
R10
33
MISO
E16
CNVST
CONV_AT_ADC
C28
0.1uF
UNI
5V
E15
LATCH
5V
C31
0.1uF
E11
CONV
VCC_IN
R9
1K
C30
0.1uF
C18
0.1uF
SHDN#
E14
MOSI
CLK_IN
OS
R16
4.7K
2.5V
SDO_AT_590
Array
EEPROM
U16
24LC025 I /ST
5
8
1
2
3
4
7
6
SDA
VCC
A0
A1
A2
VSS
WP
SCL
7V C29
0.1uF
J4
87831 1420
Molex
7 9 1 2 6 4 10 5 11
12
14
3
13
8
MOSI/SDA
EESDA
VUNREG
5V CS
SCK/SCL
EEVCC
MISO
EESCL
EEGND
NC
GND
GND
GND
SHDN
SDI_AT_ADC
R15
33
C26
0.1uF
1.25V
C25
0.1uF
U14
NC7SZ04P5X_NL
42
5
3
C20
0.1uF
1.25V
5V
SDO_AT_590
JP5
1
3
5
6
4
7
9
11
13
8
10
12
14
2
15
24
16
17
20
18
19
21
22
23
5V
SHDN
SCK_AT_ADC
SCK_AT_ADC
1.25V
LATCH
U15
NC7SZ04P5X_NL
42
5
3
R22
4.99K
1%
R18
2.00K
1%
5V
J3
CONV
R17
33
U10
NL17SZ74USG
2
1
5
3
8 7
4 6
D
CP
Q
Q
VCC
PR
GND CLR
5V
5V
MOSI
U7
NC7SZ04P5X_NL
42
5
3
C32
2.2uF
16V
2.5V
CNVST
C21
0.1uF
SDO_AT_BUF
2.5V