Loongson Godson 3A1000 User manual

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Godson 3A1000 Processor User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.15
2015 Nian 09 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice
The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual
No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
Page 3
Reading guide
"Godson 3A1000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A1000 Processor User Manual" is divided into two parts, the first part (Chapter 1 ~ Chapter 10) introduces Loongson
3A1000 multi-core processor architecture and register description, on chip system architecture, function and configuration of main modules, registers
Lists and bit fields are explained in detail; the second part (Chapter 11 ~ Chapter 16) is the system software programming guide
Special presentations on common problems in the operating system development process.
The second volume of the "Loongson 3A1000 Processor User Manual" introduces in detail the adoption of Loongson 3A1000 from the perspective of system software developers
GS464 high-performance processor core.

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revise history
Document update record
Document name: Godson 3A1000 Processor User Manual
--volume One
version number V1.15
founder: R & D Center
Creation Date: 2015-09-11
Update history
Serial numberUpdated version number update content
1 2009-10-30 V1.0 Increase the definition of DDR related parameters; modify the base address of UART and SPI
2 2009-11-13 V1.1 Add definition of PCI_CONFIG to configuration pins
3 2010-06-25 V1.2
Add the second part of the manual, including the configuration and use of interrupts, serial port configuration and
Use, EJTAG debugging instructions, address window configuration conversion, system memory space
Distributed design and memory allocation of X system
4 2010-06-29 V1.3 Revised Chapter 1 Overview, Chapter 2 Address Distribution
5 2010-07-20 V1.4 Corrected some text errors in the HT configuration register
6 2010-07-28 V1.5 Added Chip Config and Chip Sample register definitions in Section 10.5
7 2010-12-17 V1.6 Revise the definition of DDR related parameters

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8 2011-11-24 V1.7 Edit cover
9 2012-02-14 V1.8 Increase CLKSEL setting limit
10 2012-02-23 V1.9 Add DDR configuration register interrupt vector description
11
2012-04-25 V1.10 Add detailed description of chip configuration register
Add detailed description of HT diagnostic register
12
2012-08-23 V1.11 revised DDR parameter definition
Add the definition of HT register supported by LS3A1000E
13 2012-10-30 V1.12 Added matrix handling register supported by LS3A1000E
14 2014-04-02 V1.13 According to the chip naming rules, Loongson 3A processor was renamed Loongson 3A1000
Organizer
15 2014-07-24 V1.14 Add industrial-grade chip content
16 2015-09-11 V1.15 Revise the description of GPIO configuration register
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Godson 3A1000 processor user manual directory
Manual feedback: [email protected]

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Godson 3A1000 processor user manual directory
table of Contents
Godson 3A1000 Processor User Manual .................................................. .................................... I
first part................................................ .................................................. ..................... 1
Multi-core processor architecture, register description ....................................... .................................... 1
1 Overview................................................ .................................................. .......................... 2
1.1 Introduction to Loongson series processors ............................................ ........................................... 2
1.2 Introduction to Godson 3A1000 ................................................. ................................................... 3
1.3 Description of Loongson 3A1000 Commercial and Industrial Chips ................................................ ................. 5
2 System Configuration and Control ....................................... .................................................. ......... 6
2.1 Chip working mode ................................................ .................................................. ... 6
2.2 Description of control pins ....................................... .................................................. .... 6
2.3 Cache consistency ................................................. .................................................. .... 8
2.4 Physical address space distribution at the node level of the system ... .......................... 8
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 10
2.6 Chip Configuration and Sampling Register .................................................. ............................... 16
3 GS464 processor core ................................................ .................................................. ........ 19
4 Secondary Cache ................................................. .................................................. ............... twenty one
5 Matrix processing accelerator ................................................. .................................................. ...... twenty three
6 Interruption and communication between processor cores .................................... .................................... 26
7 I / O interrupt ................................................ .................................................. .................... 28
8 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 31
8.1 Overview of DDR2 / 3 SDRAM controller functions .................................................. ..................... 31
8.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 31
8.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 32
8.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 32
9 HyperTransport Controller ................................................... ..................................... 76
9.1 HyperTransport hardware setup and initialization .................................................. ................ 76
9.2 HyperTransport protocol support ................................................. ........................ 78
9.3 HyperTransport interrupt support ................................................. ........................ 79
9.4 HyperTransport Address Window ............................................. ........................ 80
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9.4.1 HyperTransport space ................................................ ........................ 80
9.4.2 Internal window configuration of HyperTransport controller ................................................ ... 80
9.5 Configuration Register ................................................. .................................................. .... 81
9.5.1 Bridge Control ............................................. ................................. 83
9.5.2 Capability Registers ............................................. ..................... 83
9.5.3 User-defined register ................................................ ...................................... 85
9.5.4 Receive Diagnostic Register ............................................ ................................. 86
9.5.5 Interrupt routing mode selection register (LS3A1000E and above) ..................... 87
9.5.6 Receive buffer initial register (LS3A1000E and above) ......................... 87
9.5.7 Receive Address Window Configuration Register .......................................... .................... 87
9.5.8 Interrupt Vector Register ............................................ ................................. 89
9.5.9 Interrupt enable register ........................................... ....................................... 91
9.5.10 Interrupt Discovery & Configuration .................................. 92
9.5.11 POST address window configuration register .......................................... ....................... 93
9.5.12 Prefetch address window configuration register ........................................... ...................... 94
9.5.13 UNCACHE address window configuration register .......................................... ................. 95
9.5.14 HyperTransport bus configuration space access method .............................................. ... 96
9.6 HyperTransport multiprocessor support .................................................. .................. 96
10 Low speed IO controller configuration ............................................ .................................................. 99
10.1 PCI / PCI-X controller .......................................... ............................................. 99
10.2 LPC Controller ................................................. .................................................. .. 103
10.3 UART Controller ................................................. .................................................. 105
10.3.1 Data Register (DAT) ................................................ .......................... 105
10.3.2 Interrupt Enable Register (IER) .............................................. ...................... 105
10.3.3 Interrupt Identification Register (IIR) ............................................... ...................... 105
10.3.4 FIFO Control Register (FCR) ............................................... ......................... 106
10.3.5 Line Control Register (LCR) .................................................... ................... 107
10.3.6 MODEM Control Register (MCR) .................................................... ................. 108
10.3.7 Line Status Register (LSR) ............................................... .................... 108
10.3.8 MODEM Status Register (MSR) ............................................... ......... 110
10.3.9 Frequency Division Latch .......................................... .................................... 110
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10.4 SPI controller ................................................. .................................................. .. 110
10.4.1 Control Register (SPCR) ................................................ ........................ 111
10.4.2 Status Register (SPSR) ................................................ ......................... 111
10.4.3 Data Register (TxFIFO) ................................................ ..................... 112
10.4.4 External register (SPER) ................................................ ......................... 112
10.5 IO controller configuration .......................................... ................................................... 113
the second part............................................... .................................................. ............ 118
System Software Programming Guide ................................................ ........................................... 118
11 Interrupt configuration and use ................................................ .................................................. 119

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11.1 Interrupted flow ............................................. .................................................. . 119
11.2 Interrupt routing and interrupt enable ........................................... ................................ 119
11.2.1 Interrupt routing ....................................... ........................................... 120
11.2.2 Interrupt enable ................................................ .................................................. 122
11.3 Interruption of distribution ...................................................... .................................................. .... 123
12 Serial Port Configuration and Use .................................................. .................................................. 125
12.1 Optional serial port ................................................ .................................... 125
12.2 Serial configuration of PMON ................................................ ..................................... 125
12.3 Serial Port Configuration of Linux Kernel .................................................. ................................. 126
13 EJTAG debugging ................................................... .................................................. ..... 128
13.1 Introduction to EJTAG ................................................. .................................................. . 128
13.2 Use of EJTAG tools ................................................. ...................................... 129
13.2.1 Environmental preparation .......................................... ........................................... 129
13.2.2 PC Sampling ............................................. .................................................. .. 129
13.2.3 Read and write memory ............................................ .................................................. 129
13.2.4 Implementation instructions ................................................ ........................................... 129
13.2.5 Online GDB debugging ................................................. ................................. 133
14 Address window configuration conversion .......................................... ........................................... 134
14.1 How to configure the address window of the first and second level crossbar ........................................... ................. 134
14.2 Address window of primary crossbar ........................................... ................................. 134
14.3 Timing of configuring the address window of the first-level crossbar .................................................. .................... 136
14.4 Address window of secondary crossbar switch ........................................... ................................. 136
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14.5 Special treatment for address window configuration .......................................... ..................... 137
14.6 HyperTransport Address Window ................................................... .......................... 138
14.6.1 External access window of processor core ........................................... ...................... 138
14.6.2 DMA access address window of external device to processor chip memory .............................. 139
14.6.3 Low-speed device address window ........................................... ............................. 140
14.7 Example Analysis of Address Space Configuration ............................................ ........................... 140
14.7.1 Example 1 of primary crossbar ............................................... ................................. 141
14.7.2 Example 1 of the first-level crossbar .............................................. ................................. 142
14.7.3 Example of a two-level crossbar 1 ............................................. ................................. 143
14.7.4 Example 2 of a two-level crossbar ......................................... ................................. 144
15 System memory space distribution design ............................................ .................................... 146
15.1 System memory space ................................................. ............................................. 146
15.2 Mapping relationship between system memory space and peripheral DMA space .......................................... .......... 149
15.3 Other mapping methods of system memory space .......................................... ................. 150
16 X system memory allocation ................................................ .................................................. . 151

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IV
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Loongson 3A1000 processor user manual map directory
Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ .................................................. . 2
Figure 1-2 Loongson No. 3 node structure ............................................ .................................................. . 3
Figure 1-3 Godson 3A1000 chip structure .......................................... ........................................... 4
Figure 3-1 GS464 structure diagram .......................................... .................................................. ..... 20
Figure 7-1 Loongson 3A1000 processor interrupt routing diagram .......................................... ..................... 28
Figure 8-1 DDR2 SDRAM row and column address and CPU physical address conversion .......................................... ........ 31
Figure 8-2 DDR2 SDRAM read operation protocol .................................................. ................................. 32
Figure 8-3 DDR2 SDRAM write operation protocol .................................................. ................................. 32
Figure 9-1 HT protocol configuration access in Loongson No. 3 .......................................... ........................ 96
Figure 9-2 Four-piece Loongson No. 3 interconnection structure .......................................... ..................................... 97
Figure 9-3 Two-chip Loongson No. 3 8-bit interconnection structure ........................................... ............................... 97
Figure 9-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ............................. 98
Figure 10-1 Configure the read and write bus address generation ........................................... ............................... 103
Figure 11-1 3A-690e Interruption Flow Chart ........................................... ..................................... 119
Figure 11-2 Schematic diagram of Loongson 3A1000 processor interrupt routing .......................................... ............... 120
Figure 13-1 EJTAG debugging system ........................................... ....................................... 128
Figure 16-1 The graphics card processing image display process ................................................. ................................. 151

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Godson 3A1000 processor user manual table entry
Table directory
Table 2-1 Control pin description .................................... .................................................. ....... 6
Table 2-2 Node-level system global address distribution .......................................... .................................... 8
Table 2-3 Address distribution in nodes ............................................ .................................................. 9
Table 2-4 Address distribution in nodes ............................................ .................................................. 9
Table 2-5 First-level crossbar address window register table .......................................... ..................... 10
Table 2-6 Correspondence between the labels and the modules at level 2 XBAR ....................................... ............... 13
Table 2-7 The space access attributes corresponding to the MMAP field ...................................... ......................... 13
Table 2-8 Secondary XBAR address window conversion register table ............................................ .......................... 14
Table 2-9 Secondary XBAR default address configuration .......................................... ....................................... 16
Table 2-10 Chip Configuration Register (Physical Address 0x1fe00180) ........................................... ......... 16
Table 2-11 Chip sampling register (physical address 0x1fe00190) ............................................ ........ 17
Table 4-1 Secondary Cache Lock Window Register Configuration .......................................... .............................. twenty two
Table 5-1 Matrix processing programming interface description ............................................ ........................................ twenty three
Table 5-2 Matrix processing register address description ............................................ .................................... twenty three
Table 5-3 Explanation of the trans_ctrl register .................................................. ........................... twenty four
Table 5-4 Explanations of the trans_status registers .................................................. ....................... 25
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 26
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................ 26
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. ............. 26
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... ............. 27
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. ............. 27
Table 7-1 Interrupt Control Register ........................................... .................................................. . 29
Table 7-2 IO Control Register Address .................................... ............................................. 29
Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 29
Table 7-4 Interrupt Routing Register Address .................................... ...................................... 30
Table 8-1 DDR2 SDRAM Configuration Parameter Register Format ........................................... .................. 33
Table 9-1 HyperTransport bus related pin signals ................................................. .................. 76
Table 9-2 Commands that the HyperTransport receiver can receive .......................................... ..................... 78
Table 9-3 Commands to be sent out in two modes .................................... ........................... 79
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Godson 3A1000 processor user manual table entry
Table 9-4 Addresses of the default 4 HyperTransport address windows ..................................... ......... 80
Table 9-5 Address window distribution of HyperTransport interface of Loongson No. 3 processor ............................... 80
Table 9-6 Address window provided in the HyperTransport interface of Loongson No. 3 processor ........................... 81
Table 9-7 All software visible registers in this module .......................................... ......................... 82
Table 10-1 PCIX Controller Configuration Header ............................................ ....................................... 99
Table 10-2 PCI Control Register ........................................... .......................................... 100
Table 10-3 PCI / PCIX bus request and response line allocation ..................................... .................. 103
Table 10-4 LPC Controller Address Space Distribution ........................................... ................................. 103
Table 10-5 Meaning of LPC Configuration Register .......................................... ................................. 104
Table 10-6 IO Control Register ........................................... .................................................. 113
Table 10-7 Detailed description of registers ........................................... ............................................. 114
Table 11-1 Description of Interrupt Routing Register ............................................ ............................... 120
Table 11-2 Interrupt Routing Register Address .................................... ................................. 121
Table 11-3 Interrupt control bit connection and attribute configuration .................................... ......................... 122
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first part
Multi-core processor architecture, register description
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Godson 3A1000 Processor User Manual Part 1
1 Overview
1.1 Introduction to Loongson series processors
Loongson processor mainly includes three series. Loongson No. 1 processor and its IP series are mainly for embedded applications.
Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service
Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded
Yes, some low-end Loongson 3 can also be used for some desktop applications. The above three series will be developed in parallel.
Loongson No. 3 multi-core series processor is based on a scalable multi-core interconnect architecture design, integrating multiple high-end on a single chip
Performance processor core and a large number of level 2 caches, and also realize the interconnection of multiple chips through high-speed I / O interface to form a larger
Modular system.
The scalable interconnection structure adopted by Loongson 3 is as followsPicture 1-1 As shown. Both the on-chip and multi-chip systems of Godson No. 3 adopt two
Dimension mesh interconnection structure, where each node is composed of 8 * 8 crossbars, each crossbar is connected to four processor cores
And four secondary caches, and interconnect with other nodes in the four directions of east (E) south (N) west (W) north (N). therefore,
2 * 2 meshes can be connected to 16 processor cores, and 4 * 4 meshes can be connected to 64 processor cores.

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Figure 1-1 Loongson No. 3 system structure
The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and two levels
Cache, memory controller and IO controller. Among them, the first level AXI crossbar switch (called X1 Switch, referred to as X1)
Connect the processor and secondary cache. The second-level crossbar switch (called X2 Switch, referred to as X2 for short) connects the second-level cache and
Memory controller.
(B)(A)
8x8 switch
P0 P1 P2 P3
L2 L2 L2
E
S
W
N
E
S
W
N
(C)
L2
Loongson No. 3 node and two-dimensional interconnection structure, (a) node structure, (b) 2 * 2 mesh network connected to 16 processors, (c)
The 4 * 4 mesh network connects 64 processors.
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Figure 1-2 Loongson No. 3 node structure
In each node, up to 8 * 8 X1 crossbars are connected to four GS464 processor cores through four Master ports
(P0, P1, P2, P3 in the figure), connect four interleave secondary caches that are addressed by four slave ports
Block (S0, S1, S2, S3 in the figure), connected to the four directions of east, south, west and north through four pairs of Master / Slave
Other nodes or IO nodes (EM / ES, SM / SS, WM / WS, NM / NS in the figure).
The X2 crossbar is connected to four secondary caches through four Master ports, and one is connected to at least one Slave port
Memory controller, at least one Slave port connected to a crossbar configuration module (Xconf) is used to configure this node
The X1 and X2 address windows, etc. You can also connect more memory controllers and IO ports as needed.
The interconnection system of Loongson 3 only defines the upper layer protocol, and will not make specific provisions on the implementation of the transmission protocol,
Therefore, the interconnection between the nodes can be implemented using an on-chip network, or multiple chips can be implemented through the I / O control link
Interconnection. In a 4-node 16-core system as an example, it can be composed of 4 4-core chips or 2 8
Core chip, or based on a single chip 4 node 16 core chip. Since the physical implementation of the interconnected system is transparent to the software,
The above three configurations of the system can run the same operating system.
1.2 Introduction to Godson 3A1000
EM
X1 Switch
S0
P0 P1 P2 P3
S1 S2 S3
WM
WS
NM
SM
NS
ES
SS
m0 m1 m2 m3 m4 m5 m6 m7
s0 s1 s2 s3 s4 s5 s6 s7
MA0 MA1 MA2 MA3
X2 Switch
MCXconf

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Loongson 3A1000 is the first product in Loongson No. 3 multi-core processor series. It is a single-node 4-core configuration.
The processor is manufactured with 65nm process and the highest working frequency is 1GHz. The main technical characteristics are as follows:
•Four 64-bit super-scalar GS464 high-performance processor cores are integrated on-chip;
•On-chip integrated 4 MB split shared secondary cache (composed of 4 individual modules, each with a capacity of 1MB);
• Maintain the cache consistency of multi-core and I / O DMA access through the directory protocol;
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• Two 64-bit 400MHz DDR2 / 3 controllers are integrated on-chip;
•Two 16-bit 800MHz HyperTransport controllers are integrated on-chip;
• Each 16-bit HT port is split into two 8-way HT ports for use.
• On-chip integrated 32-bit 100MHz PCIX / 66MHz PCI;
•Integrate 1 LPC, 2 UART, 1 SPI, 16 GPIO interfaces on-chip;
The overall architecture of Loongson 3A1000 chip is based on two-level interconnection. The structure is shown in Figure 1-3 below.
# 0 L2
Cache
Level-1 Interconnection
Level-2 Interconnection
Memory
Controller Low-end I / O
Controller
Enhance
d
HT1.0
Controlle
r
CORE
0
16B
16B
CORE
1
16B
16B
CORE
2
16B
16B
CORE
3
16B
16B
16B
16B
2B
2B
Enhance
d
HT1.0
Controlle
r
2B
2B
16B
16B
16B
16B
16B
16B
16B
16B
16B
# 1 L2
Cache # 2 L2
Cache
# 3 L2
Cache
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
Memory
Controller Config
Register
Test
Controlle
r
EJTAG
TAP
Controlle
r
Test Interface
JTAG
Interface
Inter-chip Link
SouthBridge
I / O Link
DDR2 / 3
SDRAM Low-end I / O
Interface
Inter-chip Link
SouthBridge
I / O Link
16B
RDMA
Maxtrix
Transpositio
n
16B
16B
16B
NODE
Figure 1-3 Godson 3A1000 chip structure
The first level interconnection uses a 6x6 crossbar switch, which is used to connect four CPUs (as the main device) and four second level caches
Module (as a slave), and two IO ports (each port uses a Master and a Slave). First class
Each IO port connected to the interconnect switch is connected to a 16-bit HT controller, and each 16-bit HT port can also be used as
Two 8-bit HT ports are used. The HT controller is connected to the primary interconnection switch via a DMA controller. The DMA controller
Responsible for DMA DMA control and responsible for maintaining consistency between slices. The DMA controller of Godson 3 can also be realized through configuration
Prefetch and matrix transposition or relocation.
The second level interconnection uses a 5x4 crossbar switch, connecting 4 second level cache modules (as the main device), two DDR2
Memory controller, low-speed high-speed I / O (including PCI, LPC, SPI, etc.) and the control register module inside the chip.
The above two-level interconnect switches all use separate data channels for reading and writing. The width of the data channel is 128 bits.
The processor core has the same frequency to provide high-speed on-chip data transmission.
Based on Loongson No. 3 scalable interconnection architecture, 4 quad-core Loongson 3A1000 can be connected through HT port to form 4 chips
16-core SMP structure.
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1.3 Description of Loongson 3A1000 Commercial and Industrial Chips
Loongson 3A1000 chips are available in both industrial and commercial grades. Their main features are as follows:
Configuration Commercial grade Industrial grade
Operating temperature 0 ℃ ～ 70 ℃-40 ℃ ～ 85 ℃
Whether to filter — √
Whether the quality consistency test— √
Quality consistency test standard — GB 4937-1995
The Loongson 3A chip, like most semiconductor devices, has a failure rate that conforms to the bathtub curve model. Loongson 3A industrial grade chip
In order to ensure longer-term, stable, and reliable operation, and to be able to adapt to more demanding environmental temperature requirements, the chip
Reliability screening was conducted to eliminate early failure chips. This reliability screening is a 100% test, passed the screening
To meet the requirements of industrial grade chips
The main contents of the Godson 3A screening test are as follows:
Filter items Methods and conditions (Summary) Claim
1. Visual inspection The logo is clear, no contamination, no solder ball oxidation, and the chip is intact100%
2. Stability baking 125 ℃, 24h 100%
3. Rapid temperature changes 10 cycles at maximum and minimum storage temperature 100%
4. Serial number 100%
5. Intermediate (before aging) electrical testing 100%
6, veteran TC = 85 ℃, 160h 100%
7. Intermediate (after aging) electrical test at room temperature 100%
8. Permitted non-conforming product rate (PDA)
Calculation
PDA≤5%, normal temperature, when 5% ＜ PDA≤10%, it can be
Newly submitted and refined, but only allowed once
All batches
9. End point electrical test Three temperature, record all test data 100%
10. External visual inspection The logo is clear, no contamination, no solder ball oxidation, and the chip is intact100%
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2 System configuration and control
2.1 Chip working mode
According to the structure of the system, Loongson 3A1000 has two working modes:
● Single chip mode. The system only integrates one piece of Godson 3A1000, which is a symmetric multiprocessor system (SMP).

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● Multi-chip interconnect mode. The system contains 2 pieces or 4 pieces Godson 3A1000, through the HT end of Godson 3A1000
It is a non-uniform memory access multiprocessor system (CC-NUMA).
2.2 Description of control pins
The control pins of Loongson 3A1000 include DO_TEST, ICCC_EN, NODE_ID [1: 0], CLKSEL [15: 0],
PCI_CONFIG.
Table 2-1 Control pin description
signal Up and down effect
DO_TEST pull up 1'b1 means function mode
1'b0 means test mode
ICCC_EN drop down
1'b1 means multi-chip consistent interconnect mode
1'b0 means single chip mode
NODE_ID [1: 0] Indicates the processor number in multi-chip consistent interconnect mode
CLKSEL [15: 0]
Power-on clock control
HT clock control
signal effect
CLKSEL [15]
1'b1 means use internal reference voltage
1'b0 means use external reference voltage
CLKSEL [14]
1'b1 means HT PLL uses differential clock input
1'b0 means HT PLL uses normal clock input
CLKSEL [13:12]
2'b00 means the PHY clock is 1.6GHZ / 1
2'b01 means the PHY clock is 3.2GHZ / 2
2'b10 indicates that the PHY clock is a normal input clock
2'b11 indicates that the PHY clock is a differential input clock
CLKSEL [11:10]
2'b00 means HT controller clock 200MHz
2'b01 means HT controller clock 400MHz
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2'b1x means that the HT controller clock is a normal input clock
MEM clock control
signal effect
CLKSEL [9: 5]
5'b11111 means MEM clock directly uses memclk
In other cases, the MEM clock is
memclk * (clksel [8: 5] +30) / (clksel [9] +3)
Note:
memclk * (clksel [8: 5] +30) must be 600MHz ~ 1.36GHz
memclk must be 10 ~ 40MHz
CORE clock control
signal effect
CLKSEL [4: 0]
5'b11111 indicates that the CORE clock directly uses sysclk
In other cases, the CORE clock is
sysclk * (clksel [3: 0] +30) / (clksel [4] +1)
Note:
sysclk * (clksel [3: 0] +30) must be 600MHz ~ 1.36GHz
sysclk must be 10 ~ 40MHz

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PCI_CONFIG [7: 0]
IO configuration control
7 HT control signal pin voltage control bit 1 *
6: 5 PCIX bus speed selection *
4 PCIX bus mode selection
3 PCI master mode
2 The system starts from the PCI space
1 Use external PCI arbitration
0 HT control signal pin voltage control bit 0 *
Note*:
6 4 PCIX bus mode
0 0 PCI 33/66
0 1 1 PCI-X 66
1 0 1 PCI-X 10
1 1 1 PCI-X 133
Note*:
7 0 HT control signal pin voltage, these signals include HT_8x2, HT_Mode,
HT_Powerok, HT_Rstn, HT_Ldt_Stopn, HT_Ldt_Reqn
0 0 1.8v
0 1 Reserved
1 0 2.5v
1 1 3.3v
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2.3 Cache consistency
Loongson 3A1000 maintains the cache consistency between the processor and the I / O accessed through the HT port by hardware, but
The hardware does not maintain the cache consistency of I / O devices connected to the system through PCI. During driver development,
When PCI access devices perform DMA (Direct Memory Access) transmission, the software needs to perform Cache consistency
maintain.
2.4 Distribution of physical address space at the node level of the system
The system physical address distribution of Loongson No. 3 series processors adopts a globally accessible hierarchical addressing design to
System development is compatible with expansion. The physical address width of the entire system is 48 bits. According to the upper 4 bits of the address, the entire address is empt
Time is evenly distributed to 16 nodes, that is, each node is allocated 44-bit address space.
Loongson 3A1000 uses a single node 4 core configuration, so Loongson 3A1000 chip integrated DDR memory controller, HT
The corresponding addresses of the bus and PCI bus are contained in the 44-bit field from 0x0 (inclusive) to 0x1000_0000_0000 (not included)
In the address space, please refer to the subsequent chapters for the specific address distribution of each device.
Table 2-2 Node-level system global address distribution
Node number Address [47:44] bits starting address End address
0 0 0x0000_0000_0000 0x1000_0000_0000
1 1 0x1000_0000_0000 0x2000_0000_0000
2 2 0x2000_0000_0000 0x3000_0000_0000
3 3 0x3000_0000_0000 0x4000_0000_0000
4 4 0x4000_0000_0000 0x5000_0000_0000
5 5 0x5000_0000_0000 0x6000_0000_0000
6 6 0x6000_0000_0000 0x7000_0000_0000
7 7 0x7000_0000_0000 0x8000_0000_0000
8 8 0x8000_0000_0000 0x9000_0000_0000

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9 9 0x9000_0000_0000 0xa000_0000_0000
10 0xa 0xa000_0000_0000 0xb000_0000_0000
11 0xb 0xb000_0000_0000 0xc000_0000_0000
12 0xc 0xc000_0000_0000 0xd000_0000_0000
13 0xd 0xd000_0000_0000 0xe000_0000_0000
14 0xe 0xe000_0000_0000 0xf000_0000_0000
15 0xf 0xf000_0000_0000 0x1_0000_0000_0000
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Within each node, the 44-bit address space is further evenly distributed to a maximum of 8 devices that may be connected within the node
Prepare. Among them, the lower 43 bits of addresses are owned by 4 level 2 cache modules, and the higher 43 bits of addresses are further according to the address [43:42]
Bits are distributed to devices connected to the 4 directional ports. According to the different configuration of chip and system structure, if a port
If no slave device is connected, the corresponding address space is reserved address space, and access is not allowed.
Table 2-3 Address distribution in nodes
device Address [43:41] Start address within the node Node end address
Level 2 Cache 0,1,2,3 0x000_0000_0000 0x800_0000_0000
east 4 0x800_0000_0000 0xa00_0000_0000
south 5 0xa00_0000_0000 0xc00_0000_0000
oo 6 0xc00_0000_0000 0xe00_0000_0000
north 7 0xe00_0000_0000 0x1000_0000_0000
For example, the base address of the east port device of node 0 is 0x0800_0000_0000, and the base address of the east port device of node 1
0x1800_0000_0000, and so on.
Unlike the mapping relationship of direction ports, Loongson 3A1000 can determine the second level according to the actual application access behavior
Cache cross-addressing mode. The four Level 2 Cache modules in the node correspond to a total of 43 bits of address space, and each 2
The address space corresponding to the level module is determined according to one of the two selection bits of the address bit, and can be dynamically configured by software
modify. The configuration register named SCID_SEL is set in the system to determine the address selection bits, as shown in the following table. In default
In this case, it is distributed by means of [6: 5] status hash, that is, two bits of address [6: 5] determine the corresponding level 2 cache number.
The register address is 0x3FF00400.
Table 2-4 Address distribution in nodes
SCID_SEL Address bit selection SCID_SEL Address bit selection
4'h0 6: 5 4'h8 23:22
4'h1 9: 8 4'h9 25:24
4'h2 11:10 4'ha 27:26
4'h3 13:12 4'hb 29:28
4'h4 15:14 4'hc 31:30
4'h5 17:16 4'hd 33:32
4'h6 19:18 4'he 35:34
4'h7 21:20 4'hf 37:36
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2.5 Address Routing Distribution and Configuration
The routing of Loongson 3A1000 is mainly realized through the two-stage crossbar of the system. One-level crossbar can
The master port receives requests for routing configuration. Each master port has 8 address windows, which can be completed
Target routing in 8 address windows. Each address window consists of three 64-bit registers BASE, MASK and MMAP,
BASE is aligned in K bytes; MASK adopts a format similar to the high bit of the netmask; the lower three bits of MMAP indicate the corresponding target
Slave port number, MMAP [4] means to allow instruction fetch, MMAP [5] means to allow block read, MMAP [7] means window enable
can.
Window hit formula: (IN_ADDR & MASK) == BASE
Since Loongson 3 uses fixed routing by default, the configuration window is closed when the power is turned on.
System software is required to enable and configure it.
The address window conversion register is shown in the table below.
Table 2-5 Primary Crossbar Address Window Register Table
address register address register
0x3ff0_2000 CORE0_WIN0_BASE 0x3ff0_2100 CORE1_WIN0_BASE
0x3ff0_2008 CORE0_WIN1_BASE 0x3ff0_2108 CORE1_WIN1_BASE
0x3ff0_2010 CORE0_WIN2_BASE 0x3ff0_2110 CORE1_WIN2_BASE
0x3ff0_2018 CORE0_WIN3_BASE 0x3ff0_2118 CORE1_WIN3_BASE
0x3ff0_2020 CORE0_WIN4_BASE 0x3ff0_2120 CORE1_WIN4_BASE
0x3ff0_2028 CORE0_WIN5_BASE 0x3ff0_2128 CORE1_WIN5_BASE
0x3ff0_2030 CORE0_WIN6_BASE 0x3ff0_2130 CORE1_WIN6_BASE
0x3ff0_2038 CORE0_WIN7_BASE 0x3ff0_2138 CORE1_WIN7_BASE
0x3ff0_2040 CORE0_WIN0_MASK 0x3ff0_2140 CORE1_WIN0_MASK
0x3ff0_2048 CORE0_WIN1_MASK 0x3ff0_2148 CORE1_WIN1_MASK
0x3ff0_2050 CORE0_WIN2_MASK 0x3ff0_2150 CORE1_WIN2_MASK
0x3ff0_2058 CORE0_WIN3_MASK 0x3ff0_2158 CORE1_WIN3_MASK
0x3ff0_2060 CORE0_WIN4_MASK 0x3ff0_2160 CORE1_WIN4_MASK
0x3ff0_2068 CORE0_WIN5_MASK 0x3ff0_2168 CORE1_WIN5_MASK
0x3ff0_2070 CORE0_WIN6_MASK 0x3ff0_2170 CORE1_WIN6_MASK
0x3ff0_2078 CORE0_WIN7_MASK 0x3ff0_2178 CORE1_WIN7_MASK
0x3ff0_2080 CORE0_WIN0_MMAP 0x3ff0_2180 CORE1_WIN0_MMAP
0x3ff0_2088 CORE0_WIN1_MMAP 0x3ff0_2188 CORE1_WIN1_MMAP
0x3ff0_2090 CORE0_WIN2_MMAP 0x3ff0_2190 CORE1_WIN2_MMAP
0x3ff0_2098 CORE0_WIN3_MMAP 0x3ff0_2198 CORE1_WIN3_MMAP
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0x3ff0_20a0 CORE0_WIN4_MMAP 0x3ff0_21a0 CORE1_WIN4_MMAP
0x3ff0_20a8 CORE0_WIN5_MMAP 0x3ff0_21a8 CORE1_WIN5_MMAP
0x3ff0_20b0 CORE0_WIN6_MMAP 0x3ff0_21b0 CORE1_WIN6_MMAP
0x3ff0_20b8 CORE0_WIN7_MMAP 0x3ff0_21b8 CORE1_WIN7_MMAP

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0x3ff0_2200 CORE2_WIN0_BASE 0x3ff0_2300 CORE3_WIN0_BASE
0x3ff0_2208 CORE2_WIN1_BASE 0x3ff0_2308 CORE3_WIN1_BASE
0x3ff0_2210 CORE2_WIN2_BASE 0x3ff0_2310 CORE3_WIN2_BASE
0x3ff0_2218 CORE2_WIN3_BASE 0x3ff0_2318 CORE3_WIN3_BASE
0x3ff0_2220 CORE2_WIN4_BASE 0x3ff0_2320 CORE3_WIN4_BASE
0x3ff0_2228 CORE2_WIN5_BASE 0x3ff0_2328 CORE3_WIN5_BASE
0x3ff0_2230 CORE2_WIN6_BASE 0x3ff0_2330 CORE3_WIN6_BASE
0x3ff0_2238 CORE2_WIN7_BASE 0x3ff0_2338 CORE3_WIN7_BASE
0x3ff0_2240 CORE2_WIN0_MASK 0x3ff0_2340 CORE3_WIN0_MASK
0x3ff0_2248 CORE2_WIN1_MASK 0x3ff0_2348 CORE3_WIN1_MASK
0x3ff0_2250 CORE2_WIN2_MASK 0x3ff0_2350 CORE3_WIN2_MASK
0x3ff0_2258 CORE2_WIN3_MASK 0x3ff0_2358 CORE3_WIN3_MASK
0x3ff0_2260 CORE2_WIN4_MASK 0x3ff0_2360 CORE3_WIN4_MASK
0x3ff0_2268 CORE2_WIN5_MASK 0x3ff0_2368 CORE3_WIN5_MASK
0x3ff0_2270 CORE2_WIN6_MASK 0x3ff0_2370 CORE3_WIN6_MASK
0x3ff0_2278 CORE2_WIN7_MASK 0x3ff0_2378 CORE3_WIN7_MASK
0x3ff0_2280 CORE2_WIN0_MMAP 0x3ff0_2380 CORE3_WIN0_MMAP
0x3ff0_2288 CORE2_WIN1_MMAP 0x3ff0_2388 CORE3_WIN1_MMAP
0x3ff0_2290 CORE2_WIN2_MMAP 0x3ff0_2390 CORE3_WIN2_MMAP
0x3ff0_2298 CORE2_WIN3_MMAP 0x3ff0_2398 CORE3_WIN3_MMAP
0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff0_23a0 CORE3_WIN4_MMAP
0x3ff0_22a8 CORE2_WIN5_MMAP 0x3ff0_23a8 CORE3_WIN5_MMAP
0x3ff0_22b0 CORE2_WIN6_MMAP 0x3ff0_23b0 CORE3_WIN6_MMAP
0x3ff0_22b8 CORE2_WIN7_MMAP 0x3ff0_23b8 CORE3_WIN7_MMAP
0x3ff0_2400 EAST_WIN0_BASE 0x3ff0_2500 SOUTH_WIN0_BASE
0x3ff0_2408 EAST_WIN1_BASE 0x3ff0_2508 SOUTH_WIN1_BASE
0x3ff0_2410 EAST_WIN2_BASE 0x3ff0_2510 SOUTH_WIN2_BASE
0x3ff0_2418 EAST_WIN3_BASE 0x3ff0_2518 SOUTH_WIN3_BASE
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0x3ff0_2420 EAST_WIN4_BASE 0x3ff0_2520 SOUTH_WIN4_BASE
0x3ff0_2428 EAST_WIN5_BASE 0x3ff0_2528 SOUTH_WIN5_BASE
0x3ff0_2430 EAST_WIN6_BASE 0x3ff0_2530 SOUTH_WIN6_BASE
0x3ff0_2438 EAST_WIN7_BASE 0x3ff0_2538 SOUTH_WIN7_BASE
0x3ff0_2440 EAST_WIN0_MASK 0x3ff0_2540 SOUTH_WIN0_MASK
0x3ff0_2448 EAST_WIN1_MASK 0x3ff0_2548 SOUTH_WIN1_MASK
0x3ff0_2450 EAST_WIN2_MASK 0x3ff0_2550 SOUTH_WIN2_MASK
0x3ff0_2458 EAST_WIN3_MASK 0x3ff0_2558 SOUTH_WIN3_MASK
0x3ff0_2460 EAST_WIN4_MASK 0x3ff0_2560 SOUTH_WIN4_MASK
0x3ff0_2468 EAST_WIN5_MASK 0x3ff0_2568 SOUTH_WIN5_MASK
0x3ff0_2470 EAST_WIN6_MASK 0x3ff0_2570 SOUTH_WIN6_MASK
0x3ff0_2478 EAST_WIN7_MASK 0x3ff0_2578 SOUTH_WIN7_MASK
0x3ff0_2480 EAST_WIN0_MMAP 0x3ff0_2580 SOUTH_WIN0_MMAP
0x3ff0_2488 EAST_WIN1_MMAP 0x3ff0_2588 SOUTH_WIN1_MMAP
0x3ff0_2490 EAST_WIN2_MMAP 0x3ff0_2590 SOUTH_WIN2_MMAP

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0x3ff0_2498 EAST_WIN3_MMAP 0x3ff0_2598 SOUTH_WIN3_MMAP
0x3ff0_24a0 EAST_WIN4_MMAP 0x3ff0_25a0 SOUTH_WIN4_MMAP
0x3ff0_24a8 EAST_WIN5_MMAP 0x3ff0_25a8 SOUTH_WIN5_MMAP
0x3ff0_24b0 EAST_WIN6_MMAP 0x3ff0_25b0 SOUTH_WIN6_MMAP
0x3ff0_24b8 EAST_WIN7_MMAP 0x3ff0_25b8 SOUTH_WIN7_MMAP
0x3ff0_2600 WEST_WIN0_BASE 0x3ff0_2700 NORTH_WIN0_BASE
0x3ff0_2608 WEST_WIN1_BASE 0x3ff0_2708 NORTH_WIN1_BASE
0x3ff0_2610 WEST_WIN2_BASE 0x3ff0_2710 NORTH_WIN2_BASE
0x3ff0_2618 WEST_WIN3_BASE 0x3ff0_2718 NORTH_WIN3_BASE
0x3ff0_2620 WEST_WIN4_BASE 0x3ff0_2720 NORTH_WIN4_BASE
0x3ff0_2628 WEST_WIN5_BASE 0x3ff0_2728 NORTH_WIN5_BASE
0x3ff0_2630 WEST_WIN6_BASE 0x3ff0_2730 NORTH_WIN6_BASE
0x3ff0_2638 WEST_WIN7_BASE 0x3ff0_2738 NORTH_WIN7_BASE
0x3ff0_2640 WEST_WIN0_MASK 0x3ff0_2740 NORTH_WIN0_MASK
0x3ff0_2648 WEST_WIN1_MASK 0x3ff0_2748 NORTH_WIN1_MASK
0x3ff0_2650 WEST_WIN2_MASK 0x3ff0_2750 NORTH_WIN2_MASK
0x3ff0_2658 WEST_WIN3_MASK 0x3ff0_2758 NORTH_WIN3_MASK
0x3ff0_2660 WEST_WIN4_MASK 0x3ff0_2760 NORTH_WIN4_MASK
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0x3ff0_2668 WEST_WIN5_MASK 0x3ff0_2768 NORTH_WIN5_MASK
0x3ff0_2670 WEST_WIN6_MASK 0x3ff0_2770 NORTH_WIN6_MASK
0x3ff0_2678 WEST_WIN7_MASK 0x3ff0_2778 NORTH_WIN7_MASK
0x3ff0_2680 WEST_WIN0_MMAP 0x3ff0_2780 NORTH_WIN0_MMAP
0x3ff0_2688 WEST_WIN1_MMAP 0x3ff0_2788 NORTH_WIN1_MMAP
0x3ff0_2690 WEST_WIN2_MMAP 0x3ff0_2790 NORTH_WIN2_MMAP
0x3ff0_2698 WEST_WIN3_MMAP 0x3ff0_2798 NORTH_WIN3_MMAP
0x3ff0_26a0 WEST_WIN4_MMAP 0x3ff0_27a0 NORTH_WIN4_MMAP
0x3ff0_26a8 WEST_WIN5_MMAP 0x3ff0_27a8 NORTH_WIN5_MMAP
0x3ff0_26b0 WEST_WIN6_MMAP 0x3ff0_27b0 NORTH_WIN6_MMAP
0x3ff0_26b8 WEST_WIN7_MMAP 0x3ff0_27b8 NORTH_WIN7_MMAP
In the second-level XBAR of Godson 3, there are CPU address space (including HT space), DDR2 address space, and PCI
The address space has three IP-related address spaces. The address window is for CPU and PCI-DMA with two Master functions
IP is set for routing and address translation. Both CPU and PCI-DMA have 8 address windows, you can finish
The selection of the target address space and the conversion from the source address space to the target address space. Each address window consists of BASE,
MASK and MMAP are composed of three 64-bit registers, BASE is aligned with K bytes, and MASK adopts a similar netmask high bit as 1.
, The lower three digits of MMAP are routing.
At level 2 XBAR, the correspondence between the label and the module is as follows: the number corresponding to the new address space (two of which
The number of each DDR2 is 0 and 1, the PCI / Local IO number is 2, and the configuration register module is connected to port 3).
Table 2-6 Correspondence between the labels and the modules at level 2 XBAR
Label Default value
0 No. 0 DDR2 / 3 controller
1 No. 1 DDR2 / 3 controller
2Low-speed I / O (PCI, LPC, etc.)