Loongson Godson 3A1000 User manual

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Godson 3A1000 Processor User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.15
2015 Nian 09 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice
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No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
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Reading guide
"Godson 3A1000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A1000 Processor User Manual" is divided into two parts, the first part (Chapter 1 ~ Chapter 10) introduces Loongson
3A1000 multi-core processor architecture and register description, on chip system architecture, function and configuration of main modules, registers
Lists and bit fields are explained in detail; the second part (Chapter 11 ~ Chapter 16) is the system software programming guide
Special presentations on common problems in the operating system development process.
The second volume of the "Loongson 3A1000 Processor User Manual" introduces in detail the adoption of Loongson 3A1000 from the perspective of system software developers
GS464 high-performance processor core.

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revise history
Document update record
Document name: Godson 3A1000 Processor User Manual
--volume One
version number V1.15
founder: R & D Center
Creation Date: 2015-09-11
Update history
Serial numberUpdated version number update content
1 2009-10-30 V1.0 Increase the definition of DDR related parameters; modify the base address of UART and SPI
2 2009-11-13 V1.1 Add definition of PCI_CONFIG to configuration pins
3 2010-06-25 V1.2
Add the second part of the manual, including the configuration and use of interrupts, serial port configuration and
Use, EJTAG debugging instructions, address window configuration conversion, system memory space
Distributed design and memory allocation of X system
4 2010-06-29 V1.3 Revised Chapter 1 Overview, Chapter 2 Address Distribution
5 2010-07-20 V1.4 Corrected some text errors in the HT configuration register
6 2010-07-28 V1.5 Added Chip Config and Chip Sample register definitions in Section 10.5
7 2010-12-17 V1.6 Revise the definition of DDR related parameters

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8 2011-11-24 V1.7 Edit cover
9 2012-02-14 V1.8 Increase CLKSEL setting limit
10 2012-02-23 V1.9 Add DDR configuration register interrupt vector description
11
2012-04-25 V1.10 Add detailed description of chip configuration register
Add detailed description of HT diagnostic register
12
2012-08-23 V1.11 revised DDR parameter definition
Add the definition of HT register supported by LS3A1000E
13 2012-10-30 V1.12 Added matrix handling register supported by LS3A1000E
14 2014-04-02 V1.13 According to the chip naming rules, Loongson 3A processor was renamed Loongson 3A1000
Organizer
15 2014-07-24 V1.14 Add industrial-grade chip content
16 2015-09-11 V1.15 Revise the description of GPIO configuration register
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Godson 3A1000 processor user manual directory
Manual feedback: [email protected]

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Godson 3A1000 processor user manual directory
table of Contents
Godson 3A1000 Processor User Manual .................................................. .................................... I
first part................................................ .................................................. ..................... 1
Multi-core processor architecture, register description ....................................... .................................... 1
1 Overview................................................ .................................................. .......................... 2
1.1 Introduction to Loongson series processors ............................................ ........................................... 2
1.2 Introduction to Godson 3A1000 ................................................. ................................................... 3
1.3 Description of Loongson 3A1000 Commercial and Industrial Chips ................................................ ................. 5
2 System Configuration and Control ....................................... .................................................. ......... 6
2.1 Chip working mode ................................................ .................................................. ... 6
2.2 Description of control pins ....................................... .................................................. .... 6
2.3 Cache consistency ................................................. .................................................. .... 8
2.4 Physical address space distribution at the node level of the system ... .......................... 8
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 10
2.6 Chip Configuration and Sampling Register .................................................. ............................... 16
3 GS464 processor core ................................................ .................................................. ........ 19
4 Secondary Cache ................................................. .................................................. ............... twenty one
5 Matrix processing accelerator ................................................. .................................................. ...... twenty three
6 Interruption and communication between processor cores .................................... .................................... 26
7 I / O interrupt ................................................ .................................................. .................... 28
8 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 31
8.1 Overview of DDR2 / 3 SDRAM controller functions .................................................. ..................... 31
8.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 31
8.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 32
8.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 32
9 HyperTransport Controller ................................................... ..................................... 76
9.1 HyperTransport hardware setup and initialization .................................................. ................ 76
9.2 HyperTransport protocol support ................................................. ........................ 78
9.3 HyperTransport interrupt support ................................................. ........................ 79
9.4 HyperTransport Address Window ............................................. ........................ 80
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9.4.1 HyperTransport space ................................................ ........................ 80
9.4.2 Internal window configuration of HyperTransport controller ................................................ ... 80
9.5 Configuration Register ................................................. .................................................. .... 81
9.5.1 Bridge Control ............................................. ................................. 83
9.5.2 Capability Registers ............................................. ..................... 83
9.5.3 User-defined register ................................................ ...................................... 85
9.5.4 Receive Diagnostic Register ............................................ ................................. 86
9.5.5 Interrupt routing mode selection register (LS3A1000E and above) ..................... 87
9.5.6 Receive buffer initial register (LS3A1000E and above) ......................... 87
9.5.7 Receive Address Window Configuration Register .......................................... .................... 87
9.5.8 Interrupt Vector Register ............................................ ................................. 89
9.5.9 Interrupt enable register ........................................... ....................................... 91
9.5.10 Interrupt Discovery & Configuration .................................. 92
9.5.11 POST address window configuration register .......................................... ....................... 93
9.5.12 Prefetch address window configuration register ........................................... ...................... 94
9.5.13 UNCACHE address window configuration register .......................................... ................. 95
9.5.14 HyperTransport bus configuration space access method .............................................. ... 96
9.6 HyperTransport multiprocessor support .................................................. .................. 96
10 Low speed IO controller configuration ............................................ .................................................. 99
10.1 PCI / PCI-X controller .......................................... ............................................. 99
10.2 LPC Controller ................................................. .................................................. .. 103
10.3 UART Controller ................................................. .................................................. 105
10.3.1 Data Register (DAT) ................................................ .......................... 105
10.3.2 Interrupt Enable Register (IER) .............................................. ...................... 105
10.3.3 Interrupt Identification Register (IIR) ............................................... ...................... 105
10.3.4 FIFO Control Register (FCR) ............................................... ......................... 106
10.3.5 Line Control Register (LCR) .................................................... ................... 107
10.3.6 MODEM Control Register (MCR) .................................................... ................. 108
10.3.7 Line Status Register (LSR) ............................................... .................... 108
10.3.8 MODEM Status Register (MSR) ............................................... ......... 110
10.3.9 Frequency Division Latch .......................................... .................................... 110
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10.4 SPI controller ................................................. .................................................. .. 110
10.4.1 Control Register (SPCR) ................................................ ........................ 111
10.4.2 Status Register (SPSR) ................................................ ......................... 111
10.4.3 Data Register (TxFIFO) ................................................ ..................... 112
10.4.4 External register (SPER) ................................................ ......................... 112
10.5 IO controller configuration .......................................... ................................................... 113
the second part............................................... .................................................. ............ 118
System Software Programming Guide ................................................ ........................................... 118
11 Interrupt configuration and use ................................................ .................................................. 119

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11.1 Interrupted flow ............................................. .................................................. . 119
11.2 Interrupt routing and interrupt enable ........................................... ................................ 119
11.2.1 Interrupt routing ....................................... ........................................... 120
11.2.2 Interrupt enable ................................................ .................................................. 122
11.3 Interruption of distribution ...................................................... .................................................. .... 123
12 Serial Port Configuration and Use .................................................. .................................................. 125
12.1 Optional serial port ................................................ .................................... 125
12.2 Serial configuration of PMON ................................................ ..................................... 125
12.3 Serial Port Configuration of Linux Kernel .................................................. ................................. 126
13 EJTAG debugging ................................................... .................................................. ..... 128
13.1 Introduction to EJTAG ................................................. .................................................. . 128
13.2 Use of EJTAG tools ................................................. ...................................... 129
13.2.1 Environmental preparation .......................................... ........................................... 129
13.2.2 PC Sampling ............................................. .................................................. .. 129
13.2.3 Read and write memory ............................................ .................................................. 129
13.2.4 Implementation instructions ................................................ ........................................... 129
13.2.5 Online GDB debugging ................................................. ................................. 133
14 Address window configuration conversion .......................................... ........................................... 134
14.1 How to configure the address window of the first and second level crossbar ........................................... ................. 134
14.2 Address window of primary crossbar ........................................... ................................. 134
14.3 Timing of configuring the address window of the first-level crossbar .................................................. .................... 136
14.4 Address window of secondary crossbar switch ........................................... ................................. 136
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14.5 Special treatment for address window configuration .......................................... ..................... 137
14.6 HyperTransport Address Window ................................................... .......................... 138
14.6.1 External access window of processor core ........................................... ...................... 138
14.6.2 DMA access address window of external device to processor chip memory .............................. 139
14.6.3 Low-speed device address window ........................................... ............................. 140
14.7 Example Analysis of Address Space Configuration ............................................ ........................... 140
14.7.1 Example 1 of primary crossbar ............................................... ................................. 141
14.7.2 Example 1 of the first-level crossbar .............................................. ................................. 142
14.7.3 Example of a two-level crossbar 1 ............................................. ................................. 143
14.7.4 Example 2 of a two-level crossbar ......................................... ................................. 144
15 System memory space distribution design ............................................ .................................... 146
15.1 System memory space ................................................. ............................................. 146
15.2 Mapping relationship between system memory space and peripheral DMA space .......................................... .......... 149
15.3 Other mapping methods of system memory space .......................................... ................. 150
16 X system memory allocation ................................................ .................................................. . 151

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Loongson 3A1000 processor user manual map directory
Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ .................................................. . 2
Figure 1-2 Loongson No. 3 node structure ............................................ .................................................. . 3
Figure 1-3 Godson 3A1000 chip structure .......................................... ........................................... 4
Figure 3-1 GS464 structure diagram .......................................... .................................................. ..... 20
Figure 7-1 Loongson 3A1000 processor interrupt routing diagram .......................................... ..................... 28
Figure 8-1 DDR2 SDRAM row and column address and CPU physical address conversion .......................................... ........ 31
Figure 8-2 DDR2 SDRAM read operation protocol .................................................. ................................. 32
Figure 8-3 DDR2 SDRAM write operation protocol .................................................. ................................. 32
Figure 9-1 HT protocol configuration access in Loongson No. 3 .......................................... ........................ 96
Figure 9-2 Four-piece Loongson No. 3 interconnection structure .......................................... ..................................... 97
Figure 9-3 Two-chip Loongson No. 3 8-bit interconnection structure ........................................... ............................... 97
Figure 9-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ............................. 98
Figure 10-1 Configure the read and write bus address generation ........................................... ............................... 103
Figure 11-1 3A-690e Interruption Flow Chart ........................................... ..................................... 119
Figure 11-2 Schematic diagram of Loongson 3A1000 processor interrupt routing .......................................... ............... 120
Figure 13-1 EJTAG debugging system ........................................... ....................................... 128
Figure 16-1 The graphics card processing image display process ................................................. ................................. 151

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Godson 3A1000 processor user manual table entry
Table directory
Table 2-1 Control pin description .................................... .................................................. ....... 6
Table 2-2 Node-level system global address distribution .......................................... .................................... 8
Table 2-3 Address distribution in nodes ............................................ .................................................. 9
Table 2-4 Address distribution in nodes ............................................ .................................................. 9
Table 2-5 First-level crossbar address window register table .......................................... ..................... 10
Table 2-6 Correspondence between the labels and the modules at level 2 XBAR ....................................... ............... 13
Table 2-7 The space access attributes corresponding to the MMAP field ...................................... ......................... 13
Table 2-8 Secondary XBAR address window conversion register table ............................................ .......................... 14
Table 2-9 Secondary XBAR default address configuration .......................................... ....................................... 16
Table 2-10 Chip Configuration Register (Physical Address 0x1fe00180) ........................................... ......... 16
Table 2-11 Chip sampling register (physical address 0x1fe00190) ............................................ ........ 17
Table 4-1 Secondary Cache Lock Window Register Configuration .......................................... .............................. twenty two
Table 5-1 Matrix processing programming interface description ............................................ ........................................ twenty three
Table 5-2 Matrix processing register address description ............................................ .................................... twenty three
Table 5-3 Explanation of the trans_ctrl register .................................................. ........................... twenty four
Table 5-4 Explanations of the trans_status registers .................................................. ....................... 25
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 26
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................ 26
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. ............. 26
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... ............. 27
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. ............. 27
Table 7-1 Interrupt Control Register ........................................... .................................................. . 29
Table 7-2 IO Control Register Address .................................... ............................................. 29
Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 29
Table 7-4 Interrupt Routing Register Address .................................... ...................................... 30
Table 8-1 DDR2 SDRAM Configuration Parameter Register Format ........................................... .................. 33
Table 9-1 HyperTransport bus related pin signals ................................................. .................. 76
Table 9-2 Commands that the HyperTransport receiver can receive .......................................... ..................... 78
Table 9-3 Commands to be sent out in two modes .................................... ........................... 79
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Godson 3A1000 processor user manual table entry
Table 9-4 Addresses of the default 4 HyperTransport address windows ..................................... ......... 80
Table 9-5 Address window distribution of HyperTransport interface of Loongson No. 3 processor ............................... 80
Table 9-6 Address window provided in the HyperTransport interface of Loongson No. 3 processor ........................... 81
Table 9-7 All software visible registers in this module .......................................... ......................... 82
Table 10-1 PCIX Controller Configuration Header ............................................ ....................................... 99
Table 10-2 PCI Control Register ........................................... .......................................... 100
Table 10-3 PCI / PCIX bus request and response line allocation ..................................... .................. 103
Table 10-4 LPC Controller Address Space Distribution ........................................... ................................. 103
Table 10-5 Meaning of LPC Configuration Register .......................................... ................................. 104
Table 10-6 IO Control Register ........................................... .................................................. 113
Table 10-7 Detailed description of registers ........................................... ............................................. 114
Table 11-1 Description of Interrupt Routing Register ............................................ ............................... 120
Table 11-2 Interrupt Routing Register Address .................................... ................................. 121
Table 11-3 Interrupt control bit connection and attribute configuration .................................... ......................... 122
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