Loongson 3A2000 User manual

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Loongson 3A2000 / 3B2000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.7
2017 Nian 02 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice

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The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual
No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
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Reading guide
"Godson 3A2000 / 3B2000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A2000 / 3B2000 Processor User Manual" is divided into two parts, the first part introduces Loongson 3A2000 / 3B2000
Multi-core processor architecture and register descriptions, on-chip system architecture, main module functions and configuration, register list and
The domain is described in detail.
"Loongson 3A2000 / 3B2000 Processor User Manual" volume II, detailed introduction of Loongson from the perspective of system software developers
GS464e high-performance processor core used in 3A2000 / 3B2000.

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revise history
Document update record
Document name: Godson 3A2000 / 3B2000 Processor User Manual
--volume One
version number V1.7
founder: Chip R & D Department
Creation Date: 2017-02-14
Update history
Serial numberUpdated version number update content
1 2015-03-31 V1.0 initial version
2 2015-05-27 V1.1 Add a section of software and hardware changes
3 2015-07-17 V1.2 Supplemental register description
4 2016-02-23 V1.3 Fix some register description errors, modify "software and hardware modification instructions"
5 2016-04-13 V1.4 Revise the description of HT receiving window, modify the "software and hardware modification instructions"
6 2016-06-21 V1.5 Correct CLKSEL [15] description
7 2016-10-10 V1.6 Added software configuration HT frequency description
8 2017-02-14 V1.7 Modify the "Software and Hardware Changes Instructions" to add SPI address space instructions
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Manual information feedback: [email protected]
You can also use the problem feedback website http://bugs.loongnix.org/Submit the use process of chip products to our company
Problems and obtain technical support.
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Godson 3A2000 / 3B2000 processor user manual directory
table of Contents
Loongson 3A2000 / 3B2000 processor ...................................................... ........................................... I
User Manual ................................................ .................................................. ...................... I
1 Overview................................................ .................................................. ........................ 11
1.1 Introduction to Loongson series processors ............................................ ....................................... 11
1.2 Introduction to Godson 3A2000 / 3B2000 ....................................................... ........................... 12
1.3 Description of Loongson 3A2000 Commercial and Industrial Chips ................................................. ............... 14
2 System Configuration and Control ....................................... .................................................. ....... 16
2.1 Chip working mode ................................................ .................................................. . 16
2.2 Description of control pins ....................................... .................................................. .. 16
2.3 Cache consistency ................................................. .................................................. .. 18
2.4 Physical address space distribution at the node level of the system ............................................ .................. 18
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 19
2.6 Chip Configuration and Sampling Register .................................................. ............................... 25
3 GS464e processor core ................................................ .................................................. ... 30
4 Shared Cache (SCache) ................................................. ............................................. 32
5 Matrix processing accelerator ................................................. .................................................. ... 34
6 Interruption and communication between processor cores .................................... .......................................... 37
7 I / O interrupt ................................................ .................................................. .................... 40
8 Temperature sensor ................................................ .................................................. ............. 43
8.1 Real-time temperature sampling ............................................. .................................................. . 43
8.2 High and low temperature interrupt trigger ................................................ .......................................... 43
8.3 High temperature automatic frequency reduction setting ............................................ ....................................... 44
9 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 46
9.1 DDR2 / 3 SDRAM Controller Function Overview .................................................. ..................... 46
9.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 46
9.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 47
9.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 48
9.5 Software Programming Guide ................................................. .................................................. . 51

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9.5.1 Initialization ............................................. ................................................... 51
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9.5.2 Control of reset pin .......................................... .................................... 51
9.5.3 Leveling .............................................. .................................................. 53
9.5.3.1 Write Leveling ................................................ ........................... 53
9.5.3.2 Gate Leveling ............................................. ............................. 54
9.5.4 Initiate MRS commands separately ........................................... ............................... 55
9.5.5 Arbitrary operation control bus .......................................... ............................... 56
9.5.6 Self-loop test mode control .......................................... ................................. 56
9.5.7 ECC function usage control .......................................... ................................ 57
10 HyperTransport Controller ............................................. ....................................... 58
10.1 HyperTransport hardware setup and initialization .................................................. .............. 58
10.2 HyperTransport protocol support ................................................. ............................ 61
10.3 HyperTransport interrupt support ................................................. ........................... 62
10.4 HyperTransport Address Window ................................................... ........................... 62
10.4.1 HyperTransport Space ............................................. ........................... 62
10.4.2 Internal window configuration of HyperTransport controller .................................................. .... 63
10.5 Configuration Register ................................................. .................................................. .. 64
10.5.1 Bridge Control ............................................. ............................... 66
10.5.2 Capability Registers ............................................. ................... 66
10.5.3 User-defined register ................................................ .................................... 69
10.5.4 Receive diagnostic register .................................................. ..................................... 70
10.5.5 Interrupt routing mode selection register .......................................... .................. 71
10.5.6 Receive buffer initial register .......................................... ............................ 71
10.5.7 Receive Address Window Configuration Register .......................................... .................. 71
10.5.8 Interrupt Vector Register ............................................ ................................ 74
10.5.9 Interrupt Enable Register ........................................... ................................. 77
10.5.10 Interrupt Discovery & Configuration ...................................... 80
10.5.11 POST address window configuration register .......................................... ............... 81
10.5.12 Prefetchable address window configuration register ....................................... .............. 82
10.5.13 UNCACHE Address Window Configuration Register .......................................... ............... 84
10.5.14 P2P Address Window Configuration Register .......................................... ....................... 86
10.5.15 Command send buffer size register .......................................... ...................... 88
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10.5.16 Data transmission buffer size register .......................................... ...................... 88
10.5.17 Send buffer debug register ........................................... ............................. 88
10.5.18 PHY impedance matching control register .......................................... ....................... 89
10.5.19 Revision ID Register ................................................. ............................ 90
10.5.20 Error Retry Control Register ........................................... ............... 90
10.5.21 Retry Count Register ................................................. ............................ 90
10.5.22 Link Train Register .................................................. ........................ 91
10.5.23 Training 0 Timeout Short Timer Register ................................................. ............. 92
10.5.24 Training 0 Time-out timer register .................................................. ............. 92
10.5.25 Training 1 Count Register ................................................. ....................... 92
10.5.26 Training 2 Count Register ........................................... ....................... 93
10.5.27 Training 3 Count Register ........................................... ....................... 93
10.5.28 Software Frequency Configuration Register ........................................... ............................. 93
10.5.29 PHY Configuration Register ................................................. .............................. 95
10.5.30 Link initialization debug register .......................................... .......................... 95
10.5.31 LDT debug register .................................................. ............................... 96
10.6 Access method of HyperTransport bus configuration space .......................................... .... 96
10.7 HyperTransport bus frequency software configuration method ................................................. ....... 97
10.8 HyperTransport multiprocessor support .................................................. ...................... 98
11 Low speed IO controller configuration ............................................ .......................................... 100
11.1 PCI Controller ................................................. .................................................. .. 100
11.2 LPC Controller ................................................. .................................................. .. 105
11.3 UART Controller .............................................. .................................................. 106
11.3.1 Data Register (DAT) .......................................... .......................... 107
11.3.2 Interrupt Enable Register (IER) .............................................. ........................... 107
11.3.3 Interrupt Identification Register (IIR) ............................................... ........................... 107
11.3.4 FIFO Control Register (FCR) ............................................... ................... 108
11.3.5 Line Control Register (LCR) .................................................... ................... 108
11.3.6 MODEM Control Register (MCR) ............................................... ................. 110
11.3.7 Line Status Register (LSR) ............................................... .................... 110
11.3.8 MODEM Status Register (MSR) ............................................... ............... 112
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11.3.9 Frequency Division Latch .......................................... .......................................... 112
11.4 SPI Controller .............................................. .................................................. .. 113
11.4.1 Control Register (SPCR) .......................................... ........................ 113
11.4.2 Status Register (SPSR) ................................................ ......................... 114
11.4.3 Data Register (TxFIFO) ................................................ ..................... 114
11.4.4 External Register (SPER) ................................................ ......................... 114
11.4.5 Parameter control register (SFC_PARAM) ................................................... .......... 115
11.4.6 Chip Select Control Register (SFC_SOFTCS) .............................................. .......... 115
11.4.7 Timing Control Register (SFC_TIMING) ............................................... .......... 116

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11.5 IO Controller Configuration ....................................... ............................................. 117
12 Chip Configuration Register List .......................................... ................................. 121
13 Software and Hardware Design Guidelines ................................................ .................................................. ... 161
13.1 Hardware modification guide ................................................. ............................................. 161
13.2 Description of Frequency Setting ............................................. ............................................. 162
13.3 PMON Change Guide ................................................ ............................................. 162
13.4 Guidelines for kernel changes ............................................. ............................................. 163
13.5 Description of other changes ................................................ ............................................. 164
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Loongson 3A2000 / 3B2000 processor user manual picture directory
Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ ........................................... 11
Figure 1-2 Loongson No. 3 node structure ............................................ ........................................... 12
Figure 1-3 Godson 3A2000 chip structure .......................................... ....................................... 13
Figure 3-1 GS464e structure diagram .......................................... .................................................. ... 31
Figure 7-1 Loongson 3A2000 processor interrupt routing diagram .......................................... .................... 40
Figure 9-1 DDR2 SDRAM read operation protocol .................................................. ............................. 47
Figure 9-2 DDR2 SDRAM write operation protocol .................................................. ............................. 47
Figure 10-1 HT protocol configuration access in Loongson 3A2000 ........................................... ................... 97
Figure 10-2 Four-piece Loongson No. 3 interconnection structure .......................................... ....................................... 98
Figure 10-3 Two-chip Loongson No. 3 8-bit interconnection structure ..................................... ............................. 99
Figure 10-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ........................... 99
Figure 11-1 Configure the read and write bus address generation ........................................... ............................... 104

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Godson 3A2000 / 3B2000 Processor User Manual Table List
Table directory
Table 2-1 Control pin description .................................... .................................................. ..... 16
Table 2-2 Node-level system global address distribution .......................................... ................................. 18
Table 2-3 Address distribution in nodes ............................................ .......................................... 19
Table 2-4 Address distribution in nodes ............................................ .......................................... 19
Table 2-5 The space access attributes corresponding to the MMAP field ...................................... ....................... 20
Table 2-6 Primary Crossbar Address Window Register Table .......................................... ..................... 20
Table 2-7 Correspondence between the slave device number and the module at the secondary XBAR ..................................... ..... twenty three
Table 2-8 The space access attributes corresponding to the MMAP field ............................................ ....................... twenty three
Table 2-9 Secondary XBAR address window conversion register table ............................................ ....................... twenty three
Table 2-10 Secondary XBAR default address configuration .......................................... .............................. 25
Table 2-11 Chip Configuration Register (Physical Address 0x1fe00180) ............................................ ......... 26
Table 2-12 Chip sampling register (physical address 0x1fe00190) ............................................ ......... 26
Table 2-13 Chip Node and Processor Core Software Frequency Multiplication Setting Register (Physical Address 0x1fe001b0) ... 27
Table 2-14 Chip memory and HT clock software frequency multiplication setting register (physical address 0x1fe001c0) ... 28
Table 2-15 Chip processor core software frequency division setting register (physical address 0x1fe001d0) ............... 29
Table 4-1 Shared Cache Lock Window Register Configuration ........................................... ............................. 33
Table 5-1 Matrix processing programming interface description ............................................ ................................. 34
Table 5-2 Matrix processing register address description ............................................ .............................. 35
Table 5-3 Trans_ctrl register description ................................................ ..................................... 35
Table 5-4 Trans_status register description ................................................. ................................. 36
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 37
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................. 37
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. .............. 38
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... .............. 38
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. .............. 38
Table 7-1 Interrupt Control Register ........................................... .................................................. . 41
Table 7-2 IO Control Register Address .................................... ................................................... 41

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Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 42
Table 7-4 Interrupt Routing Register Address .................................... ........................................... 42
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Table 8-1 Temperature sampling register description .................................... ........................................... 43
Table 8-2 High and low temperature interrupt register description ............................................ ....................................... 44
Table 8-3 Description of high-temperature down-frequency control register ........................................... ................................ 45
Table 10-1 HyperTransport bus related pin signals ................................................. ...................... 58
Table 10-2 Commands that the HyperTransport receiver can receive .......................................... ............. 61
Table 10-3 Commands to be sent out in two modes .................................... .......................... 61
Table 10-4 The default address window distribution of the four HyperTransport interfaces .................................... 62
Table 10-5 Address window distribution inside HyperTransport interface of Loongson 3 processor .................... 63
Table 10-6 Address window provided in HyperTransport interface of Loongson 3A2000 processor 63
Table 10-7 Software visible register list .......................................... ....................................... 64
Table 10-8 Bus Reset Control Register Definition ............................................ ............................. 66
Table 10-9 Definition of Command, Capabilities Pointer, Capability ID registers ..................... 66
Table 10-10 Link Config, Link Control register definition .......................................... .............. 67
Table 10-11 Definitions of Revision ID, Link Freq, Link Error, Link Freq Cap Registers ... 68
Table 10-12 Definition of Feature Capability Register .................................... ......................... 69
Table 10-13 MISC register definition ........................................... ........................................... 69
Table 10-14 Receive Diagnostic Register ........................................... ................................................... 70
Table 10-15 Interrupt Routing Selection Register ............................................ ........................... 71
Table 10-16 Receive buffer initial register ............................................ ............................... 71
Table 10-17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ........................ 72
Table 10-18 HT bus receive address window 0 base address (external access) register definition ........................ 72
Table 10-19 HT bus receive address window 1 enable (external access) register definition ........................ 72
Table 10-20 HT bus receive address window 1 base address (external access) register definition ........................ 73
Table 10-21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition ........................ 73
Table 10-22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition ........................ 73
Table 10-23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition ........................ 73
Table 10-24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ........................ 74
Table 10-25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ........................ 74
Table 10-26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition ........................ 74
Table 10-27 HT Bus Interrupt Vector Register Definition (1) ........................................... ..................... 75
Table 10-28 HT Bus Interrupt Vector Register Definition (2) ........................................... ............... 76
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Godson 3A2000 / 3B2000 Processor User Manual Table List
Table 10-29 HT Bus Interrupt Vector Register Definition (3) ........................................... ............... 76
Table 10-30 HT Bus Interrupt Vector Register Definition (4) ........................................... ............... 76
Table 10-31 Definition of HT Bus Interrupt Vector Register (6) ........................................... ..................... 77
Table 10-32 Definition of HT Bus Interrupt Vector Register (7) ........................................... ..................... 77
Table 10-33 HT Bus Interrupt Vector Register Definition (8) ........................................... ..................... 77
Table 10-34 HT Bus Interrupt Enable Register Definition (1) .................................... ...................... 78
Table 10-35 Definition of HT Bus Interrupt Enable Register (2) .................................... ...................... 78
Table 10-36 HT Bus Interrupt Enable Register Definition (3) .......................................... ................ 79
Table 10-37 Definition of HT Bus Interrupt Enable Register (4) .................................... ................ 79
Table 10-38 HT Bus Interrupt Enable Register Definition (5) .......................................... ................ 79
Table 10-39 Definition of HT Bus Interrupt Enable Register (6) .......................................... ................ 79
Table 10-40 HT Bus Interrupt Enable Register Definition (7) .......................................... ................ 79
Table 10-41 HT Bus Interrupt Enable Register Definition (8) .......................................... ...................... 80
Table 10-42 Interrupt Capability Register Definition .......................................... .................. 80
Table 10-43 Dataport register definition ........................................... ................................. 80
Table 10-44 IntrInfo register definition (1) .............................................. ............................. 80
Table 10-45 IntrInfo register definition (2) .............................................. ............................. 81
Table 10-46 HT Bus POST Address Window 0 Enable (Internal Access) .................................. ... 81
Table 10-47 HT Bus POST Address Window 0 Base Address (Internal Access) ........................................ ... 82
Table 10-48 HT Bus POST Address Window 1 Enable (Internal Access) ........................................ ... 82
Table 10-49 HT Bus POST Address Window 1 Base Address (Internal Access) ........................................ ... 82
Table 10-50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ...................................... ........ 83
Table 10-51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ...................................... ........ 83
Table 10-52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ...................................... ........ 83
Table 10-53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ...................................... ........ 83
Table 10-54 HT Bus Uncache Address Window 0 Enable (Internal Access) ........................................ .. 84
Table 10-55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........................................ .. 84
Table 10-56 HT Bus Uncache Address Window 1 Enable (Internal Access) ........................................ .. 85
Table 10-57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........................................ .. 85
Table 10-58 HT Bus Uncache Address Window 2 Enable (Internal Access) ........................................ .. 85
Table 10-59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........................................ .. 85
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Table 10-60 HT Bus Uncache Address Window 3 Enable (Internal Access) ........................................ .. 86
Table 10-61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........................................ .. 86
Table 10-62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ....................... 87
Table 10-63 HT bus P2P address window 0 base address (external access) register definition .......................... 87
Table 10-64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition .......................... 87
Table 10-65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition ....................... 87
Table 10-66 Command Send Buffer Size Register ................................................. .......................... 88
Table 10-67 Data transmission buffer size register .................................................. .......................... 88