Loongson 3A2000 User manual

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Loongson 3A2000 / 3B2000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.7
2017 Nian 02 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice

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The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual
No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
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Reading guide
"Godson 3A2000 / 3B2000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A2000 / 3B2000 Processor User Manual" is divided into two parts, the first part introduces Loongson 3A2000 / 3B2000
Multi-core processor architecture and register descriptions, on-chip system architecture, main module functions and configuration, register list and
The domain is described in detail.
"Loongson 3A2000 / 3B2000 Processor User Manual" volume II, detailed introduction of Loongson from the perspective of system software developers
GS464e high-performance processor core used in 3A2000 / 3B2000.

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revise history
Document update record
Document name: Godson 3A2000 / 3B2000 Processor User Manual
--volume One
version number V1.7
founder: Chip R & D Department
Creation Date: 2017-02-14
Update history
Serial numberUpdated version number update content
1 2015-03-31 V1.0 initial version
2 2015-05-27 V1.1 Add a section of software and hardware changes
3 2015-07-17 V1.2 Supplemental register description
4 2016-02-23 V1.3 Fix some register description errors, modify "software and hardware modification instructions"
5 2016-04-13 V1.4 Revise the description of HT receiving window, modify the "software and hardware modification instructions"
6 2016-06-21 V1.5 Correct CLKSEL [15] description
7 2016-10-10 V1.6 Added software configuration HT frequency description
8 2017-02-14 V1.7 Modify the "Software and Hardware Changes Instructions" to add SPI address space instructions
9

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Manual information feedback: [email protected]
You can also use the problem feedback website http://bugs.loongnix.org/Submit the use process of chip products to our company
Problems and obtain technical support.
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Godson 3A2000 / 3B2000 processor user manual directory
table of Contents
Loongson 3A2000 / 3B2000 processor ...................................................... ........................................... I
User Manual ................................................ .................................................. ...................... I
1 Overview................................................ .................................................. ........................ 11
1.1 Introduction to Loongson series processors ............................................ ....................................... 11
1.2 Introduction to Godson 3A2000 / 3B2000 ....................................................... ........................... 12
1.3 Description of Loongson 3A2000 Commercial and Industrial Chips ................................................. ............... 14
2 System Configuration and Control ....................................... .................................................. ....... 16
2.1 Chip working mode ................................................ .................................................. . 16
2.2 Description of control pins ....................................... .................................................. .. 16
2.3 Cache consistency ................................................. .................................................. .. 18
2.4 Physical address space distribution at the node level of the system ............................................ .................. 18
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 19
2.6 Chip Configuration and Sampling Register .................................................. ............................... 25
3 GS464e processor core ................................................ .................................................. ... 30
4 Shared Cache (SCache) ................................................. ............................................. 32
5 Matrix processing accelerator ................................................. .................................................. ... 34
6 Interruption and communication between processor cores .................................... .......................................... 37
7 I / O interrupt ................................................ .................................................. .................... 40
8 Temperature sensor ................................................ .................................................. ............. 43
8.1 Real-time temperature sampling ............................................. .................................................. . 43
8.2 High and low temperature interrupt trigger ................................................ .......................................... 43
8.3 High temperature automatic frequency reduction setting ............................................ ....................................... 44
9 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 46
9.1 DDR2 / 3 SDRAM Controller Function Overview .................................................. ..................... 46
9.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 46
9.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 47
9.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 48
9.5 Software Programming Guide ................................................. .................................................. . 51

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9.5.1 Initialization ............................................. ................................................... 51
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9.5.2 Control of reset pin .......................................... .................................... 51
9.5.3 Leveling .............................................. .................................................. 53
9.5.3.1 Write Leveling ................................................ ........................... 53
9.5.3.2 Gate Leveling ............................................. ............................. 54
9.5.4 Initiate MRS commands separately ........................................... ............................... 55
9.5.5 Arbitrary operation control bus .......................................... ............................... 56
9.5.6 Self-loop test mode control .......................................... ................................. 56
9.5.7 ECC function usage control .......................................... ................................ 57
10 HyperTransport Controller ............................................. ....................................... 58
10.1 HyperTransport hardware setup and initialization .................................................. .............. 58
10.2 HyperTransport protocol support ................................................. ............................ 61
10.3 HyperTransport interrupt support ................................................. ........................... 62
10.4 HyperTransport Address Window ................................................... ........................... 62
10.4.1 HyperTransport Space ............................................. ........................... 62
10.4.2 Internal window configuration of HyperTransport controller .................................................. .... 63
10.5 Configuration Register ................................................. .................................................. .. 64
10.5.1 Bridge Control ............................................. ............................... 66
10.5.2 Capability Registers ............................................. ................... 66
10.5.3 User-defined register ................................................ .................................... 69
10.5.4 Receive diagnostic register .................................................. ..................................... 70
10.5.5 Interrupt routing mode selection register .......................................... .................. 71
10.5.6 Receive buffer initial register .......................................... ............................ 71
10.5.7 Receive Address Window Configuration Register .......................................... .................. 71
10.5.8 Interrupt Vector Register ............................................ ................................ 74
10.5.9 Interrupt Enable Register ........................................... ................................. 77
10.5.10 Interrupt Discovery & Configuration ...................................... 80
10.5.11 POST address window configuration register .......................................... ............... 81
10.5.12 Prefetchable address window configuration register ....................................... .............. 82
10.5.13 UNCACHE Address Window Configuration Register .......................................... ............... 84
10.5.14 P2P Address Window Configuration Register .......................................... ....................... 86
10.5.15 Command send buffer size register .......................................... ...................... 88
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10.5.16 Data transmission buffer size register .......................................... ...................... 88
10.5.17 Send buffer debug register ........................................... ............................. 88
10.5.18 PHY impedance matching control register .......................................... ....................... 89
10.5.19 Revision ID Register ................................................. ............................ 90
10.5.20 Error Retry Control Register ........................................... ............... 90
10.5.21 Retry Count Register ................................................. ............................ 90
10.5.22 Link Train Register .................................................. ........................ 91
10.5.23 Training 0 Timeout Short Timer Register ................................................. ............. 92
10.5.24 Training 0 Time-out timer register .................................................. ............. 92
10.5.25 Training 1 Count Register ................................................. ....................... 92
10.5.26 Training 2 Count Register ........................................... ....................... 93
10.5.27 Training 3 Count Register ........................................... ....................... 93
10.5.28 Software Frequency Configuration Register ........................................... ............................. 93
10.5.29 PHY Configuration Register ................................................. .............................. 95
10.5.30 Link initialization debug register .......................................... .......................... 95
10.5.31 LDT debug register .................................................. ............................... 96
10.6 Access method of HyperTransport bus configuration space .......................................... .... 96
10.7 HyperTransport bus frequency software configuration method ................................................. ....... 97
10.8 HyperTransport multiprocessor support .................................................. ...................... 98
11 Low speed IO controller configuration ............................................ .......................................... 100
11.1 PCI Controller ................................................. .................................................. .. 100
11.2 LPC Controller ................................................. .................................................. .. 105
11.3 UART Controller .............................................. .................................................. 106
11.3.1 Data Register (DAT) .......................................... .......................... 107
11.3.2 Interrupt Enable Register (IER) .............................................. ........................... 107
11.3.3 Interrupt Identification Register (IIR) ............................................... ........................... 107
11.3.4 FIFO Control Register (FCR) ............................................... ................... 108
11.3.5 Line Control Register (LCR) .................................................... ................... 108
11.3.6 MODEM Control Register (MCR) ............................................... ................. 110
11.3.7 Line Status Register (LSR) ............................................... .................... 110
11.3.8 MODEM Status Register (MSR) ............................................... ............... 112
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11.3.9 Frequency Division Latch .......................................... .......................................... 112
11.4 SPI Controller .............................................. .................................................. .. 113
11.4.1 Control Register (SPCR) .......................................... ........................ 113
11.4.2 Status Register (SPSR) ................................................ ......................... 114
11.4.3 Data Register (TxFIFO) ................................................ ..................... 114
11.4.4 External Register (SPER) ................................................ ......................... 114
11.4.5 Parameter control register (SFC_PARAM) ................................................... .......... 115
11.4.6 Chip Select Control Register (SFC_SOFTCS) .............................................. .......... 115
11.4.7 Timing Control Register (SFC_TIMING) ............................................... .......... 116

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11.5 IO Controller Configuration ....................................... ............................................. 117
12 Chip Configuration Register List .......................................... ................................. 121
13 Software and Hardware Design Guidelines ................................................ .................................................. ... 161
13.1 Hardware modification guide ................................................. ............................................. 161
13.2 Description of Frequency Setting ............................................. ............................................. 162
13.3 PMON Change Guide ................................................ ............................................. 162
13.4 Guidelines for kernel changes ............................................. ............................................. 163
13.5 Description of other changes ................................................ ............................................. 164
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Loongson 3A2000 / 3B2000 processor user manual picture directory
Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ ........................................... 11
Figure 1-2 Loongson No. 3 node structure ............................................ ........................................... 12
Figure 1-3 Godson 3A2000 chip structure .......................................... ....................................... 13
Figure 3-1 GS464e structure diagram .......................................... .................................................. ... 31
Figure 7-1 Loongson 3A2000 processor interrupt routing diagram .......................................... .................... 40
Figure 9-1 DDR2 SDRAM read operation protocol .................................................. ............................. 47
Figure 9-2 DDR2 SDRAM write operation protocol .................................................. ............................. 47
Figure 10-1 HT protocol configuration access in Loongson 3A2000 ........................................... ................... 97
Figure 10-2 Four-piece Loongson No. 3 interconnection structure .......................................... ....................................... 98
Figure 10-3 Two-chip Loongson No. 3 8-bit interconnection structure ..................................... ............................. 99
Figure 10-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ........................... 99
Figure 11-1 Configure the read and write bus address generation ........................................... ............................... 104

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Godson 3A2000 / 3B2000 Processor User Manual Table List
Table directory
Table 2-1 Control pin description .................................... .................................................. ..... 16
Table 2-2 Node-level system global address distribution .......................................... ................................. 18
Table 2-3 Address distribution in nodes ............................................ .......................................... 19
Table 2-4 Address distribution in nodes ............................................ .......................................... 19
Table 2-5 The space access attributes corresponding to the MMAP field ...................................... ....................... 20
Table 2-6 Primary Crossbar Address Window Register Table .......................................... ..................... 20
Table 2-7 Correspondence between the slave device number and the module at the secondary XBAR ..................................... ..... twenty three
Table 2-8 The space access attributes corresponding to the MMAP field ............................................ ....................... twenty three
Table 2-9 Secondary XBAR address window conversion register table ............................................ ....................... twenty three
Table 2-10 Secondary XBAR default address configuration .......................................... .............................. 25
Table 2-11 Chip Configuration Register (Physical Address 0x1fe00180) ............................................ ......... 26
Table 2-12 Chip sampling register (physical address 0x1fe00190) ............................................ ......... 26
Table 2-13 Chip Node and Processor Core Software Frequency Multiplication Setting Register (Physical Address 0x1fe001b0) ... 27
Table 2-14 Chip memory and HT clock software frequency multiplication setting register (physical address 0x1fe001c0) ... 28
Table 2-15 Chip processor core software frequency division setting register (physical address 0x1fe001d0) ............... 29
Table 4-1 Shared Cache Lock Window Register Configuration ........................................... ............................. 33
Table 5-1 Matrix processing programming interface description ............................................ ................................. 34
Table 5-2 Matrix processing register address description ............................................ .............................. 35
Table 5-3 Trans_ctrl register description ................................................ ..................................... 35
Table 5-4 Trans_status register description ................................................. ................................. 36
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 37
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................. 37
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. .............. 38
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... .............. 38
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. .............. 38
Table 7-1 Interrupt Control Register ........................................... .................................................. . 41
Table 7-2 IO Control Register Address .................................... ................................................... 41

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Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 42
Table 7-4 Interrupt Routing Register Address .................................... ........................................... 42
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Table 8-1 Temperature sampling register description .................................... ........................................... 43
Table 8-2 High and low temperature interrupt register description ............................................ ....................................... 44
Table 8-3 Description of high-temperature down-frequency control register ........................................... ................................ 45
Table 10-1 HyperTransport bus related pin signals ................................................. ...................... 58
Table 10-2 Commands that the HyperTransport receiver can receive .......................................... ............. 61
Table 10-3 Commands to be sent out in two modes .................................... .......................... 61
Table 10-4 The default address window distribution of the four HyperTransport interfaces .................................... 62
Table 10-5 Address window distribution inside HyperTransport interface of Loongson 3 processor .................... 63
Table 10-6 Address window provided in HyperTransport interface of Loongson 3A2000 processor 63
Table 10-7 Software visible register list .......................................... ....................................... 64
Table 10-8 Bus Reset Control Register Definition ............................................ ............................. 66
Table 10-9 Definition of Command, Capabilities Pointer, Capability ID registers ..................... 66
Table 10-10 Link Config, Link Control register definition .......................................... .............. 67
Table 10-11 Definitions of Revision ID, Link Freq, Link Error, Link Freq Cap Registers ... 68
Table 10-12 Definition of Feature Capability Register .................................... ......................... 69
Table 10-13 MISC register definition ........................................... ........................................... 69
Table 10-14 Receive Diagnostic Register ........................................... ................................................... 70
Table 10-15 Interrupt Routing Selection Register ............................................ ........................... 71
Table 10-16 Receive buffer initial register ............................................ ............................... 71
Table 10-17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ........................ 72
Table 10-18 HT bus receive address window 0 base address (external access) register definition ........................ 72
Table 10-19 HT bus receive address window 1 enable (external access) register definition ........................ 72
Table 10-20 HT bus receive address window 1 base address (external access) register definition ........................ 73
Table 10-21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition ........................ 73
Table 10-22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition ........................ 73
Table 10-23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition ........................ 73
Table 10-24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ........................ 74
Table 10-25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ........................ 74
Table 10-26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition ........................ 74
Table 10-27 HT Bus Interrupt Vector Register Definition (1) ........................................... ..................... 75
Table 10-28 HT Bus Interrupt Vector Register Definition (2) ........................................... ............... 76
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Godson 3A2000 / 3B2000 Processor User Manual Table List
Table 10-29 HT Bus Interrupt Vector Register Definition (3) ........................................... ............... 76
Table 10-30 HT Bus Interrupt Vector Register Definition (4) ........................................... ............... 76
Table 10-31 Definition of HT Bus Interrupt Vector Register (6) ........................................... ..................... 77
Table 10-32 Definition of HT Bus Interrupt Vector Register (7) ........................................... ..................... 77
Table 10-33 HT Bus Interrupt Vector Register Definition (8) ........................................... ..................... 77
Table 10-34 HT Bus Interrupt Enable Register Definition (1) .................................... ...................... 78
Table 10-35 Definition of HT Bus Interrupt Enable Register (2) .................................... ...................... 78
Table 10-36 HT Bus Interrupt Enable Register Definition (3) .......................................... ................ 79
Table 10-37 Definition of HT Bus Interrupt Enable Register (4) .................................... ................ 79
Table 10-38 HT Bus Interrupt Enable Register Definition (5) .......................................... ................ 79
Table 10-39 Definition of HT Bus Interrupt Enable Register (6) .......................................... ................ 79
Table 10-40 HT Bus Interrupt Enable Register Definition (7) .......................................... ................ 79
Table 10-41 HT Bus Interrupt Enable Register Definition (8) .......................................... ...................... 80
Table 10-42 Interrupt Capability Register Definition .......................................... .................. 80
Table 10-43 Dataport register definition ........................................... ................................. 80
Table 10-44 IntrInfo register definition (1) .............................................. ............................. 80
Table 10-45 IntrInfo register definition (2) .............................................. ............................. 81
Table 10-46 HT Bus POST Address Window 0 Enable (Internal Access) .................................. ... 81
Table 10-47 HT Bus POST Address Window 0 Base Address (Internal Access) ........................................ ... 82
Table 10-48 HT Bus POST Address Window 1 Enable (Internal Access) ........................................ ... 82
Table 10-49 HT Bus POST Address Window 1 Base Address (Internal Access) ........................................ ... 82
Table 10-50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ...................................... ........ 83
Table 10-51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ...................................... ........ 83
Table 10-52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ...................................... ........ 83
Table 10-53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ...................................... ........ 83
Table 10-54 HT Bus Uncache Address Window 0 Enable (Internal Access) ........................................ .. 84
Table 10-55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........................................ .. 84
Table 10-56 HT Bus Uncache Address Window 1 Enable (Internal Access) ........................................ .. 85
Table 10-57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........................................ .. 85
Table 10-58 HT Bus Uncache Address Window 2 Enable (Internal Access) ........................................ .. 85
Table 10-59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........................................ .. 85
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Table 10-60 HT Bus Uncache Address Window 3 Enable (Internal Access) ........................................ .. 86
Table 10-61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........................................ .. 86
Table 10-62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ....................... 87
Table 10-63 HT bus P2P address window 0 base address (external access) register definition .......................... 87
Table 10-64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition .......................... 87
Table 10-65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition ....................... 87
Table 10-66 Command Send Buffer Size Register ................................................. .......................... 88
Table 10-67 Data transmission buffer size register .................................................. .......................... 88

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Table 10-68 Send Buffer Debug Register .................................... ................................. 89
Table 10-69 Impedance Matching Control Register .................................... ................................. 89
Table 10-70 Revision ID Register ........................................... ..................................... 90
Table 10-71 Error Retry Control Register .................................... .............................. 90
Table 10-72 Retry Count Register ........................................... ..................................... 91
Table 10-73 Link Train Register ........................................... ....................................... 91
Table 10-74 Training 0 Timeout Short Timer Register ........................................... ...................... 92
Table 10-75 Training 0 Timeout Long Count Register ........................................... ...................... 92
Table 10-76 Training 1 Count Register .......................................... ................................ 93
Table 10-77 Training 2 Count Register .......................................... ................................ 93
Table 10-78 Training 3 Count Register .......................................... ................................ 93
Table 10-79 Software Frequency Configuration Register .......................................... ................................. 94
Table 10-80 PHY Configuration Register ........................................... ....................................... 95
Table 10-81 Link Initialization Debug Register ................................................. .............................. 96
Table 10-82 LDT debug registers ........................................... ....................................... 96
Table 11-1 PCI Controller Configuration Header ............................................ ............................................. 100
Table 11-2 PCI Control Register .......................................... .......................................... 101
Table 11-3 PCI / PCIX bus request and response line allocation ..................................... .................. 104
Table 11-4 LPC Controller Address Space Distribution ........................................... ........................... 105
Table 11-5 Meaning of LPC Configuration Register .......................................... ................................. 105
Table 11-6 SPI controller address space distribution ........................................... .............................. 113
Table 11-6 IO Control Register ........................................... .................................................. 117
Table 11-7 Detailed description of registers ........................................... ................................................... 118
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
1 Overview
1.1 Introduction to Loongson series processors
Loongson processor mainly includes three series. Loongson No. 1 processor and its IP series are mainly for embedded applications.
Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service
Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded
Yes, some low-end Loongson 3 can also be used for some desktop applications. The above three series will be developed in parallel.
Loongson No. 3 multi-core series processor is based on a scalable multi-core interconnect architecture design, integrating multiple high-end on a single chip
Performance processor core and a large number of level 2 caches, and also realize the interconnection of multiple chips through high-speed I / O interface to form a larger
Modular system.
The scalable interconnection structure adopted by Loongson 3 is as followsPicture 1-1 As shown. Both the on-chip and multi-chip systems of Godson No. 3 adopt two
Dimension mesh interconnection structure, where each node is composed of 8 * 8 crossbars, each crossbar is connected to four processor cores
And four shared caches, and interconnect with other nodes in four directions of east (E) south (N) west (W) north (N). therefore,
2 * 2 meshes can be connected to 16 processor cores, and 4 * 4 meshes can be connected to 64 processor cores.
(B)(A)
8x8 switch
P0 P1 P2 P3
L2 L2 L2
E
S
W
N
E
S
W
N
(C)
L2
Loongson No. 3 node and two-dimensional interconnection structure, (a) node structure, (b) 2 * 2 mesh network connected to 16 processors, (c)
The 4 * 4 mesh network connects 64 processors.

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Figure 1-1 Loongson No. 3 system structure
The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and shared
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Cache, memory controller and IO controller. Among them, the first level AXI crossbar switch (called X1 Switch, referred to as X1)
Connect the processor and shared cache. The second level crossbar switch (called X2 Switch, referred to as X2 for short) is connected to share Cache and
Memory controller.
Figure 1-2 Loongson No. 3 node structure
In each node, up to 8 * 8 X1 crossbars are connected to four GS464 processor cores through four Master ports
(P0, P1, P2, P3 in the figure), connected to four interleave shared caches with four slave ports through four slave ports
Block (S0, S1, S2, S3 in the figure), connected to the four directions of east, south, west and north through four pairs of Master / Slave
Other nodes or IO nodes (EM / ES, SM / SS, WM / WS, NM / NS in the figure).
The X2 crossbar is connected to four shared caches through four Master ports, and one is connected to at least one Slave port
Memory controller, at least one Slave port connected to a crossbar configuration module (Xconf) is used to configure this node
The X1 and X2 address windows, etc. You can also connect more memory controllers and IO ports as needed.
1.2 Introduction to Godson 3A2000 / 3B2000
Loongson 3A2000 / 3B2000 is a micro-structured upgraded version of Loongson 3A1000 quad-core processor. The package pins and Loongson
3A1000 compatible. Loongson 3A2000 / 3B2000 is a single-node 4-core processor, using 40nm process technology
The main frequency is 800MHz-1GHz, and the main technical characteristics are as follows:
• Four 64-bit super-scalar GS464e high-performance processor cores are integrated on-chip;
•On-chip integrated 4 MB split shared three-level cache (composed of 4 individual modules, each module has a capacity of 1MB);
EM
X1 Switch
S0
P0 P1 P2 P3
S1 S2 S3
WM
WS
NM
SM
NS
ES
SS
m0 m1 m2 m3 m4 m5 m6 m7
s0 s1 s2 s3 s4 s5 s6 s7
MA0 MA1 MA2 MA3
X2 Switch
MCXconf
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
• Maintain the cache consistency of multi-core and I / O DMA access through the directory protocol;
•Two 64-bit DDR2 / 3 controllers with ECC and 667MHz are integrated on-chip;
• 3B2000 integrates two 16-bit 1.6GHz HyperTransport controllers (hereinafter referred to as HT);
• 3A2000 on-chip HT1 is a 16-bit 1.6GHz HT controller, HT0 is not available;
•Each 16-bit HT port is split into two 8-way HT ports for use.
• On-chip integrated 32-bit 33MHz PCI;
•Integrate 1 LPC, 2 UARTs, 1 SPI, 16 GPIO interfaces on-chip.
Compared with Loongson 3A1000, the main improvements are as follows:
• Comprehensive upgrade of the processor core microstructure;
•The memory controller structure and frequency are fully upgraded;
•HT controller structure and frequency are fully upgraded;
• The internal interconnection structure is fully upgraded;
•The external expansion interconnection structure is fully upgraded;
•Support SPI start function;
• Support full chip software frequency configuration;
•The performance of the whole chip is optimized and improved.
Godson 3A2000 Chip architecture is based on two integrally interconnected to achieve the following structure in FIG 1-3 FIG.
# 0 LL
Cache
Level-1 Interconnection
Level-2 Interconnection
Memory
Controller Low-end I / O
Controller
Enhanced
HT3.0
Controller
CORE0
16B
16B
CORE1
16B
16B
CORE2
16B
16B
CORE3
16B
16B
16B
16B
2B
2B
Enhanced
HT3.0
Controller
2B
2B
16B
16B
16B
16B
16B
16B
16B
16B
16B
# 1 LL
Cache
# 2 LL
Cache
# 3 LL
Cache
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
16B
Memory
Controller Config
Register
Test
Controller
EJTAG
TAP
Controller
Test Interface
JTAG Interface
Inter-chip Link
SouthBridge
I / O Link
DDR2 / 3
SDRAM UART
Inter-chip Link
SouthBridge
I / O Link
16B
RDMA
Maxtrix
Transposition
16B
16B
16B
NODE
LPC
SPI
PCI
Figure 1-3 Godson 3A2000 chip structure
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The first level interconnection uses a 6x6 crossbar switch, which is used to connect four GS464e cores (as a master device) and four shares
Cache module (as a slave device), and two IO ports (each port uses a Master and a Slave).
Each IO port connected to the first-level interconnect switch is connected to a 16-bit HT controller, and each 16-bit HT port can also
Used as two 8-bit HT ports. The HT controller is connected to the first-level interconnect switch through a DMA controller. The DMA controller
The controller is responsible for the DMA control of the IO and the maintenance of the consistency between the slices. The DMA controller of Godson 3 can also be configured
Realize prefetching and matrix transposition or transfer.
The second level interconnection uses a 5x4 crossbar switch, connecting 4 shared Cache modules (as the main device), two DDR2 / 3

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Memory controller, low-speed high-speed I / O (including PCI, LPC, SPI, etc.) and configuration register module inside the chip.
The above two-level interconnect switches all use separate data channels for reading and writing. The width of the data channel is 128 bits.
The processor core has the same frequency to provide high-speed on-chip data transmission.
The difference between 3B2000 and 3A2000 processors is that 3B2000 supports the use of HT0 as a consistent interconnect interface.
Based on Loongson No. 3 scalable interconnect architecture, 4 quad-core Loongson 3B2000 can be connected via HT port to form 4 chip 16
The NUMA structure of the core. The 3A2000 processor only supports the IO use of the HT1 controller.
In the following, there will be no difference between 3B2000 and 3A2000, referred to as Loongson 3A2000.
1.3 Description of Loongson 3A2000 Commercial and Industrial Chips
Loongson 3A2000 chips are available in both industrial and commercial grades. Their main features are as follows:
Configuration Commercial grade Industrial grade
Operating temperature 0 ℃ ～ 70 ℃-40 ℃ ～ 85 ℃
Whether to filter — √
Whether the quality consistency test— √
Quality consistency test standard — GB 4937-1995
The Loongson 3A chip, like most semiconductor devices, has a failure rate that conforms to the bathtub curve model. Loongson 3A industrial grade chip
In order to ensure longer-term, stable, and reliable operation, and to be able to adapt to more demanding environmental temperature requirements, the chip
Reliability screening was conducted to eliminate early failure chips. This reliability screening is a 100% test, passed the screening
To meet the requirements of industrial grade chips.
The operating voltage of 3A2000 commercial grade and industrial grade chips is slightly different. Industrial-grade chips require an operating voltage of 1.15V,
The power supply jitter is less than 50mV; the commercial-grade chip requires an operating voltage of 1.25V, and the power supply jitter is less than 50mV.
The main contents of the Godson 3A screening test are as follows:
Filter items Methods and conditions (Summary) Claim
1. Visual inspection The logo is clear, no contamination, no solder ball oxidation, and the chip is intact100%
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2. Stability baking 125 ℃, 24h 100%
3. Rapid temperature changes 10 cycles at maximum and minimum storage temperature 100%
4. Serial number 100%
5. Intermediate (before aging) electrical testing 100%
6, veteran TC = 85 ℃, 160h 100%
7. Intermediate (after aging) electrical test at room temperature 100%
8. Permitted non-conforming product rate (PDA)
Calculation
PDA≤5%, normal temperature, when 5% ＜ PDA≤10%, it can be
Newly submitted and refined, but only allowed once
All batches
9. End point electrical test Three temperature, record all test data 100%
10. External visual inspection The logo is clear, no contamination, no solder ball oxidation, and the chip is intact100%

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2 System configuration and control
2.1 Chip working mode
According to the structure of the system, Loongson 3A2000 mainly includes three working modes:
● Single chip mode. The system only contains one Loongson 3A2000, which is a symmetric multiprocessor system (SMP);
● Multi-chip interconnect mode. The system contains 2 pieces or 4 pieces Godson 3A2000, through the HT end of Godson 3A2000
It is a non-uniform memory access multiprocessor system (CC-NUMA);
● Large-scale interconnection model. Large-scale multi-chip expansion interconnection through dedicated expansion bridges, forming a large-scale non-uniform
Uniform access to multi-processor systems (CC-NUMA).
2.2 Description of control pins
The main control pins include DO_TEST, ICCC_EN, NODE_ID [1: 0], CLKSEL [15: 0], PCI_CONFIG.
Table 2-1 Control pin description
signal Up and down effect
DO_TEST pull up 1'b1 means function mode
1'b0 means test mode
ICCC_EN drop down 1'b1 means multi-chip consistent interconnect mode
1'b0 means single chip mode
NODE_ID [1: 0] Indicates the processor number in multi-chip consistent interconnect mode
HT clock control
signal effect
CLKSEL [15]
1'b1 means the HT PLL frequency is only set by hardware
1'b0 means HT PLL frequency can be set by software
1'b1 means HT PLL uses normal clock input

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CLKSEL [15: 0] CLKSEL [14] 1'b0 means HT PLL uses differential clock input
CLKSEL [13:12]
2'b00 means the PHY clock is 1.6GHZ
2'b01 indicates that the PHY clock is 3.2GHZ
2'b10 means the PHY clock is 1.2GHz
2'b11 means the PHY clock is 2.4GHz
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CLKSEL [11:10]
2'b00 indicates that the HT controller clock is divided by 8 of the PHY clock
2'b01 indicates that the HT controller clock is divided by 4 of the PHY clock
2'b10 means the HT controller clock is divided by 2 of the PHY clock
2'b11 indicates that the HT controller clock is SYSCLOCK
Note: When CLKSEL [13:10] == 4'b1111, the HT controller clock is in bypass mode and used directly
External input 100MHz reference clock
MEM clock control
signal effect
CLKSEL [9: 5]
5'b11111 means MEM clock directly uses memclk
5'b01111 indicates that the MEM clock is set by software. For the setting method, see
2.6 Description
In other cases, the MEM clock is
memclk * (clksel [8: 5] +30) / (clksel [9] +3)
Note:
memclk * (clksel [8: 5] +30) must be 1.2GHz ~ 3.2GHz
memclk is the input reference clock, which must be 20 ~ 40MHz
CORE clock control
signal effect
CLKSEL [4: 0]
5'b11111 indicates that the CORE clock directly uses sysclk
5'b011xx indicates that the CORE clock is set by software. For the setting method, see
Instructions in Section 2.6 .
5'b01111 is normal working mode, otherwise it is debugging mode
5'b0110x means FIFO depth is set to 2
5'b011x0 means DCDL control mode
In other cases, the CORE clock is
sysclk * (clksel [3: 0] +30) / (clksel [4] +1)
Note:
sysclk * (clksel [3: 0] +30) must be 1.2GHz ~ 3.2GHz
sysclk is the input reference clock, which must be 20 ~ 40MHz
PCI_CONFIG [7: 0]
IO configuration control
7 HT bus cold start is forced to 1.0 mode
6: 4 needs to be set to 000
3 PCI master mode
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2 needs to be set to 0
1 Use external PCI arbitration
0 Use SPI boot function
2.3 Cache consistency
Loongson 3A2000 maintains the cache consistency between the processor and the I / O accessed through the HT port by hardware, but
The hardware does not maintain the cache consistency of I / O devices connected to the system through PCI. During driver development,
When PCI access devices perform DMA (Direct Memory Access) transmission, the software needs to perform Cache consistency
maintain.
2.4 Distribution of physical address space at the node level of the system
The system physical address distribution of Loongson No. 3 series processors adopts a globally accessible hierarchical addressing design to
System development is compatible with expansion. The physical address width of the entire system is 48 bits. According to the upper 4 bits of the address, the entire address is empt
Time is evenly distributed to 16 nodes, that is, each node is allocated 44-bit address space.
Loongson 3A2000 processor can directly use 4-chip direct connection to build CC-NUMA system, the processor number of each chip
Determined by the pin NODEID, the address space of each chip is distributed as follows:
Table 2-2 Node-level system global address distribution
Chip node number (NODEID) Address [47:44] bits starting address End address
0 0 0x0000_0000_0000 0x0FFF_FFFF_FFFF
1 1 0x1000_0000_0000 0x1FFF_FFFF_FFFF
2 2 0x2000_0000_0000 0x2FFF_FFFF_FFFF
3 3 0x3000_0000_0000 0x3FFF_FFFF_FFFF
Loongson 3A2000 uses a single node 4-core configuration, so Loongson 3A2000 chip integrated DDR memory controller, HT
The corresponding addresses of the bus and PCI bus are contained in the 44-bit field from 0x0 (inclusive) to 0x1000_0000_0000 (not included)
Within each node, the 44-bit address space is further evenly distributed to a maximum of 8 devices that may be connected within the node.
Among them, the lower 43 bits of addresses are owned by 4 shared cache modules, and the higher 43 bits of addresses are further according to the address [43:42] bits
Distribute to devices connected to 4 directional ports. According to the different configuration of the chip and system structure, if there is no
If there is a connected slave device, the corresponding address space is reserved address space, and access is not allowed.
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The slave devices corresponding to the address space of the first-level crossbar in the Loongson 3A2000 chip are as follows:
Table 2-3 Address distribution in nodes
device Address [43:41] Start address within the node Node end address
Shared Cache 0,1,2,3 0x000_0000_0000 0x7FF_FFFF_FFFF
HT0 controller 6 0xC00_0000_0000 0xDFF_FFFF_FFFF

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HT1 controller 7 0xE00_0000_0000 0xFFF_FFFF_FFFF
Unlike the mapping relationship of direction ports, Loongson 3A2000 can decide to share based on the actual application access behavior
Cache cross-addressing mode. The 4 shared Cache modules in the node correspond to a total of 43 bits of address space, and each module
The address space corresponding to the block is determined according to one of the two selection bits of the address bit, and can be dynamically configured and repaired by software
change. The configuration register named SCID_SEL is set in the system to determine the address selection bits, as shown in the following table. By default
In the case of [7: 6] status hash distribution, that is, the two addresses [7: 6] determine the corresponding shared cache number.
The register address is 0x3FF00400.
Table 2-4 Address distribution in nodes
SCID_SEL Address bit selection SCID_SEL Address bit selection
4'h0 7: 6 4'h8 23:22
4'h1 9: 8 4'h9 25:24
4'h2 11:10 4'ha 27:26
4'h3 13:12 4'hb 29:28
4'h4 15:14 4'hc 31:30
4'h5 17:16 4'hd 33:32
4'h6 19:18 4'he 35:34
4'h7 21:20 4'hf 37:36
2.5 Address Routing Distribution and Configuration
The routing of Loongson 3A2000 is mainly realized through the two-stage crossbar of the system. One-level crossbar can
The master port receives requests for routing configuration. Each master port has 8 address windows, which can be completed
Target routing in 8 address windows. Each address window consists of three 64-bit registers BASE, MASK and MMAP,
BASE is aligned in K bytes; MASK adopts a format similar to the high bit of the netmask; the lower three bits of MMAP indicate the corresponding target
Slave port number, MMAP [4] means to allow instruction fetch, MMAP [5] means to allow block read, MMAP [6] means to allow pair
Scache's interleaved access is enabled, MMAP [7] indicates that the window is enabled.
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Table 2-5 The space access attributes corresponding to the MMAP field
[7] [6] [5] [4]
Window enable allows interleaved access to SCACHE. It is valid when the slave number is 0, according to the above
A section of SCID_SEL configuration routes requests that hit window addresses
Allow block read, allow instruction fetch
Window hit formula: (IN_ADDR & MASK) == BASE
Since Loongson 3 uses fixed routing by default, the configuration window is closed when the power is turned on.
System software is required to enable and configure it.
The address window conversion register is shown in the table below.
Table 2-6 First-level crossbar address window register table
address register address register
0x3ff0_2000 CORE0_WIN0_BASE 0x3ff0_2100 CORE1_WIN0_BASE
0x3ff0_2008 CORE0_WIN1_BASE 0x3ff0_2108 CORE1_WIN1_BASE
0x3ff0_2010 CORE0_WIN2_BASE 0x3ff0_2110 CORE1_WIN2_BASE
0x3ff0_2018 CORE0_WIN3_BASE 0x3ff0_2118 CORE1_WIN3_BASE
0x3ff0_2020 CORE0_WIN4_BASE 0x3ff0_2120 CORE1_WIN4_BASE
0x3ff0_2028 CORE0_WIN5_BASE 0x3ff0_2128 CORE1_WIN5_BASE

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0x3ff0_2030 CORE0_WIN6_BASE 0x3ff0_2130 CORE1_WIN6_BASE
0x3ff0_2038 CORE0_WIN7_BASE 0x3ff0_2138 CORE1_WIN7_BASE
0x3ff0_2040 CORE0_WIN0_MASK 0x3ff0_2140 CORE1_WIN0_MASK
0x3ff0_2048 CORE0_WIN1_MASK 0x3ff0_2148 CORE1_WIN1_MASK
0x3ff0_2050 CORE0_WIN2_MASK 0x3ff0_2150 CORE1_WIN2_MASK
0x3ff0_2058 CORE0_WIN3_MASK 0x3ff0_2158 CORE1_WIN3_MASK
0x3ff0_2060 CORE0_WIN4_MASK 0x3ff0_2160 CORE1_WIN4_MASK
0x3ff0_2068 CORE0_WIN5_MASK 0x3ff0_2168 CORE1_WIN5_MASK
0x3ff0_2070 CORE0_WIN6_MASK 0x3ff0_2170 CORE1_WIN6_MASK
0x3ff0_2078 CORE0_WIN7_MASK 0x3ff0_2178 CORE1_WIN7_MASK
0x3ff0_2080 CORE0_WIN0_MMAP 0x3ff0_2180 CORE1_WIN0_MMAP
0x3ff0_2088 CORE0_WIN1_MMAP 0x3ff0_2188 CORE1_WIN1_MMAP
0x3ff0_2090 CORE0_WIN2_MMAP 0x3ff0_2190 CORE1_WIN2_MMAP
0x3ff0_2098 CORE0_WIN3_MMAP 0x3ff0_2198 CORE1_WIN3_MMAP
0x3ff0_20a0 CORE0_WIN4_MMAP 0x3ff0_21a0 CORE1_WIN4_MMAP
0x3ff0_20a8 CORE0_WIN5_MMAP 0x3ff0_21a8 CORE1_WIN5_MMAP
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0x3ff0_20b0 CORE0_WIN6_MMAP 0x3ff0_21b0 CORE1_WIN6_MMAP
0x3ff0_20b8 CORE0_WIN7_MMAP 0x3ff0_21b8 CORE1_WIN7_MMAP
0x3ff0_2200 CORE2_WIN0_BASE 0x3ff0_2300 CORE3_WIN0_BASE
0x3ff0_2208 CORE2_WIN1_BASE 0x3ff0_2308 CORE3_WIN1_BASE
0x3ff0_2210 CORE2_WIN2_BASE 0x3ff0_2310 CORE3_WIN2_BASE
0x3ff0_2218 CORE2_WIN3_BASE 0x3ff0_2318 CORE3_WIN3_BASE
0x3ff0_2220 CORE2_WIN4_BASE 0x3ff0_2320 CORE3_WIN4_BASE
0x3ff0_2228 CORE2_WIN5_BASE 0x3ff0_2328 CORE3_WIN5_BASE
0x3ff0_2230 CORE2_WIN6_BASE 0x3ff0_2330 CORE3_WIN6_BASE
0x3ff0_2238 CORE2_WIN7_BASE 0x3ff0_2338 CORE3_WIN7_BASE
0x3ff0_2240 CORE2_WIN0_MASK 0x3ff0_2340 CORE3_WIN0_MASK
0x3ff0_2248 CORE2_WIN1_MASK 0x3ff0_2348 CORE3_WIN1_MASK
0x3ff0_2250 CORE2_WIN2_MASK 0x3ff0_2350 CORE3_WIN2_MASK
0x3ff0_2258 CORE2_WIN3_MASK 0x3ff0_2358 CORE3_WIN3_MASK
0x3ff0_2260 CORE2_WIN4_MASK 0x3ff0_2360 CORE3_WIN4_MASK
0x3ff0_2268 CORE2_WIN5_MASK 0x3ff0_2368 CORE3_WIN5_MASK
0x3ff0_2270 CORE2_WIN6_MASK 0x3ff0_2370 CORE3_WIN6_MASK
0x3ff0_2278 CORE2_WIN7_MASK 0x3ff0_2378 CORE3_WIN7_MASK
0x3ff0_2280 CORE2_WIN0_MMAP 0x3ff0_2380 CORE3_WIN0_MMAP
0x3ff0_2288 CORE2_WIN1_MMAP 0x3ff0_2388 CORE3_WIN1_MMAP
0x3ff0_2290 CORE2_WIN2_MMAP 0x3ff0_2390 CORE3_WIN2_MMAP
0x3ff0_2298 CORE2_WIN3_MMAP 0x3ff0_2398 CORE3_WIN3_MMAP
0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff0_23a0 CORE3_WIN4_MMAP
0x3ff0_22a8 CORE2_WIN5_MMAP 0x3ff0_23a8 CORE3_WIN5_MMAP