Loongson 3A3000 User manual

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Loongson 3A3000 / 3B3000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.3
2017 Nian 4 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice

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The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual
No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
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Reading guide
"Godson 3A3000 / 3B3000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A3000 / 3B3000 Processor User Manual" is divided into two parts, the first part introduces Loongson 3A3000 / 3B3000
Multi-core processor architecture and register descriptions, on-chip system architecture, main module functions and configuration, register list and
The domain is described in detail.
Volume 2 of the "Loongson 3A3000 / 3B3000 Processor User Manual" introduces Loongson in detail from the perspective of system software developers
3A3000 / 3B3000 uses the GS464e high-performance processor core.

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revise history
Document update record
Document name: Loongson 3A3000 / 3B3000 Processor User Manual
--volume One
version number V1.3
founder: Chip R & D Department
Creation Date: 2017-04-13
Update history
Serial numberUpdated version number update content
1 2016-06-14 V1.0 initial version
2 2016-09-14 V1.1 Updated some PLL configuration register descriptions, updated software and hardware changes descriptions
3 2016-11-25 V1.2 Add register description of BBGEN section
4 2017-04-13 V1.3 Add SPI address space description
Manual feedback: [email protected]
You can also submit chip production to our company through the problem feedback website http://bugs.loongnix.org/
Problems in the use of products, and obtain technical support.

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table of Contents
1 Overview................................................ .................................................. ........................ 11
1.1 Introduction to Loongson series processors ............................................ ....................................... 11
1.2 Introduction to Godson 3A3000 / 3B3000 ....................................................... ................................. 12
2 System Configuration and Control ....................................... .................................................. ....... 15
2.1 Chip working mode ................................................ .................................................. .15
2.2 Description of control pins ....................................... .................................................. ..15
2.3 Cache consistency ................................................. .................................................. ..17
2.4 Physical address space distribution at the node level of the system ............................................ ........................ 17
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 19
2.6 Chip Configuration and Sampling Register .................................................. ............................... 25
3 GS464e processor core ................................................ .................................................. ... 30
4 Shared Cache (SCache) ................................................. ................................................... 32
5 Matrix processing accelerator ................................................. .................................................. ... 34
6 Interruption and communication between processor cores .................................... .......................................... 37
7 I / O interrupt ................................................ .................................................. .................... 40
8 Temperature sensor ................................................ .................................................. ............. 43
8.1 Real-time temperature sampling ............................................. .................................................. .43
8.2 High and low temperature interrupt trigger ................................................ ................................................ 43
8.3 High temperature automatic frequency reduction setting ............................................ ....................................... 44
9 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 46
9.1 DDR2 / 3 SDRAM Controller Function Overview .................................................. ..................... 46
9.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 46
9.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 47
9.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 47
9.5 Software Programming Guide ................................................. .................................................. .51
9.5.1 Initialization ............................................. ................................................... 51
9.5.2 Control of reset pin .......................................... .................................... 51
9.5.3 Leveling ................................................. .................................................. 53

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9.5.3.1 Write Leveling ................................................ ........................... 53
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9.5.3.2 Gate Leveling ............................................. ................................... 54
9.5.4 Initiate MRS commands separately ........................................... ............................... 55
9.5.5 Arbitrary operation control bus .......................................... ............................... 56
9.5.6 Self-loop test mode control .......................................... ................................. 56
9.5.7 ECC function usage control .......................................... ................................ 57
10 HyperTransport Controller ............................................. ....................................... 58
10.1 HyperTransport hardware setup and initialization .................................................. .............. 58
10.2 HyperTransport protocol support ................................................. ........................... 61
10.3 HyperTransport interrupt support ................................................. ...................... 62
10.4 HyperTransport Address Window ................................................... ...................... 62
10.4.1 HyperTransport Space ............................................. ........................... 62
10.4.2 Internal window configuration of HyperTransport controller .................................................. .... 63
10.5 Configuration Register ................................................. .................................................. ..64
10.5.1 Bridge Control ............................................. ............................... 66
10.5.2 Capability Registers ................................................ ................... 66
10.5.3 User-defined register ................................................ .................................... 69
10.5.4 Receive diagnostic register .................................................. ................................ 71
10.5.5 Interrupt routing mode selection register .......................................... .................. 71
10.5.6 Receive buffer initial register .......................................... ............................ 71
10.5.7 Receive Address Window Configuration Register .......................................... .................. 72
10.5.8 Interrupt Vector Register ............................................ ................................ 75
10.5.9 Interrupt Enable Register ........................................... ................................. 78
10.5.10 Interrupt Discovery & Configuration ...................................... 81
10.5.11 POST address window configuration register .......................................... ..................... 82
10.5.12 Prefetchable address window configuration register ........................................... .................... 83
10.5.13 UNCACHE Address Window Configuration Register .......................................... ............... 84
10.5.14 P2P Address Window Configuration Register .......................................... ....................... 87
10.5.15 Command send buffer size register .......................................... ...................... 89
10.5.16 Data transmission buffer size register .......................................... ...................... 89
10.5.17 Send buffer debug register ........................................... ....................... 89
10.5.18 PHY impedance matching control register .......................................... ....................... 90
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10.5.19 Revision ID Register ................................................. ............................ 91
10.5.20 Error Retry Control Register ........................................... ..................... 91
10.5.21 Retry Count Register ................................................. ...................... 92
10.5.22 Link Train Register .................................................. ........................ 92
10.5.23 Training 0 Timeout Short Timer Register ................................................. ............. 93
10.5.24 Training 0 Time-out timer register .................................................. ............. 94
10.5.25 Training 1 Count Register ................................................. ....................... 94
10.5.26 Training 2 Count Register ........................................... ....................... 94
10.5.27 Training 3 Count Register ........................................... ....................... 94
10.5.28 Software Frequency Configuration Register ........................................... ............................. 95
10.5.29 PHY Configuration Register ................................................. .............................. 96
10.5.30 Link initialization debug register .......................................... .......................... 97
10.5.31 LDT debug register .................................................. ............................... 97
10.6 Access method of HyperTransport bus configuration space .......................................... .... 98
10.7 HyperTransport multiprocessor support .................................................. ...................... 98
11 Low speed IO controller configuration ............................................ .......................................... 101
11.1 PCI Controller ................................................. .................................................. ..101
11.2 LPC Controller ................................................. .................................................. ..106
11.3 UART Controller .............................................. .................................................. 107
11.3.1 Data Register (DAT) ................................................ ........................... 108
11.3.2 Interrupt Enable Register (IER) ................................................. ........................... 108
11.3.3 Interrupt Identification Register (IIR) .................................................. ........................... 108
11.3.4 FIFO Control Register (FCR) .................................................. ................... 109
11.3.5 Line Control Register (LCR) .................................................. .................... 109
11.3.6 MODEM Control Register (MCR) .................................................. .................. 111
11.3.7 Line Status Register (LSR) .................................................. .................... 111
11.3.8 MODEM Status Register (MSR) ...................................................... ................ 113
11.3.9 Frequency Division Latch .......................................... ........................................... 113
11.4 SPI Controller .............................................. .................................................. ..114
11.4.1 Control Register (SPCR) ................................................ ......................... 114
11.4.2 Status Register (SPSR) .......................................... ......................... 115
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11.4.3 Data Register (TxFIFO) ................................................ ............................ 115
11.4.4 External Register (SPER) ................................................ ......................... 115
11.4.5 Parameter control register (SFC_PARAM) ................................................. ........... 116
11.4.6 Chip Select Control Register (SFC_SOFTCS) ................................................. ........... 116
11.4.7 Timing control register (SFC_TIMING) .................................................. .......... 117
11.5 IO Controller Configuration ....................................... ................................................... 118
12 Chip Configuration Register List .......................................... ................................. 122
13 Software and Hardware Design Guidelines ................................................ .................................................. ... 162
13.1 Hardware modification guide ................................................. ............................................. 162

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13.2 Description of Frequency Setting ............................................. ............................................. 163
13.3 PMON Change Guide ................................................ ....................................... 163
13.4 Guidelines for kernel changes ............................................. ............................................. 164
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Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ ................................................. 11
Figure 1-2 Loongson No. 3 node structure ............................................ ........................................... 12
Figure 1-3 Godson 3A3000 / 3B3000 chip structure ........................................... ............................. 13
Figure 3-1 GS464e structure diagram .......................................... .................................................. ... 31
Figure 7-1 Loongson 3A3000 / 3B3000 processor interrupt routing diagram ..................................... ........ 40
Figure 9-1 DDR2 SDRAM read operation protocol .................................................. ................................. 47
Figure 9-2 DDR2 SDRAM write operation protocol .................................................. ................................. 47
Figure 10-1 HT protocol configuration access in Loongson 3A3000 / 3B3000 .................................... ....... 98
Figure 10-2 Four-piece Loongson No. 3 interconnection structure .......................................... ....................................... 99
Figure 10-3 Two-chip Loongson No. 3 8-bit interconnection structure ..................................... ........................... 100
Figure 10-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ............................... 100
Figure 11-1 Configure the read and write bus address generation ........................................... ............................... 105

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Table directory
Table 2-1 Control pin description .................................... .................................................. ..... 15
Table 2-2 Node-level system global address distribution .......................................... ................................. 17
Table 2-3 Address distribution in nodes ............................................ .......................................... 18
Table 2-4 Address distribution in nodes ............................................ .......................................... 18
Table 2-5 The space access attributes corresponding to the MMAP field ...................................... ....................... 19
Table 2-6 Primary Crossbar Address Window Register Table .......................................... ..................... 19
Table 2-7 Correspondence between the slave device number and the module at the secondary XBAR ..................................... .....twenty two
Table 2-8 The space access attributes corresponding to the MMAP field ............................................ .......................twenty two
Table 2-9 Secondary XBAR address window conversion register table ............................................ .......................twenty two
Table 2-10 Secondary XBAR default address configuration .......................................... .............................. 25
Table 2-11 Chip Configuration Register (Physical Address 0x1fe00180) ........................................... ......... 25
Table 2-12 Chip sampling register (physical address 0x1fe00190) ........................................... ......... 25
Table 2-13 Chip node and processor core software frequency multiplication setting register (physical address 0x1fe001b0) ... 27
Table 2-14 Chip memory and HT clock software frequency multiplier setting register (physical address 0x1fe001c0) ... 28
Table 2-15 Chip processor core software frequency division setting register (physical address 0x1fe001d0) ... 28
Table 4-1 Shared Cache Lock Window Register Configuration ........................................... ............................. 33
Table 5-1 Matrix processing programming interface description ............................................ ................................. 34
Table 5-2 Matrix processing register address description ............................................ .............................. 35
Table 5-3 Trans_ctrl register description ................................................ ..................................... 35
Table 5-4 Trans_status register description ................................................. ................................. 36
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 37
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................. 37
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. .............. 38
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... .............. 38
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. .............. 38
Table 7-1 Interrupt Control Register ........................................... .................................................. .41
Table 7-2 IO Control Register Address .................................... ................................................... 41

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Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 42
Table 7-4 Interrupt Routing Register Address .................................... ........................................... 42
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Table 8-1 Temperature sampling register description .................................... ........................................... 43
Table 8-2 High and low temperature interrupt register description ............................................ ....................................... 44
Table 8-3 Description of high-temperature down-frequency control register ........................................... ................................ 45
Table 10-1 HyperTransport bus related pin signals ................................................. ............... 58
Table 10-2 Commands that the HyperTransport receiver can receive .......................................... .................. 61
Table 10-3 Commands to be sent out in two modes .................................... ......................... 61
Table 10-4 Default Address Window Distribution of the Four HyperTransport Interfaces ................................. 62
Table 10-5 Address window distribution inside HyperTransport interface of Loongson No. 3 processor ................... 63
Table 10-6 Address window provided in HyperTransport interface of Loongson 3A3000 / 3B3000 processor ... 63
Table 10-7 Software visible register list .......................................... ....................................... 64
Table 10-8 Bus Reset Control Register Definition ............................................ ...................... 66
Table 10-9 Definition of Command, Capabilities Pointer, Capability ID registers ..................... 66
Table 10-10 Link Config, Link Control register definition .......................................... ............. 67
Table 10-11 Definition of Revision ID, Link Freq, Link Error, Link Freq Cap Registers ............ 68
Table 10-12 Definition of Feature Capability Register .................................... ................... 69
Table 10-13 MISC register definition ........................................... ........................................... 69
Table 10-14 Receive Diagnostic Register ........................................... ............................................. 71
Table 10-15 Interrupt Routing Selection Register ............................................ ........................... 71
Table 10-16 Receive buffer initial register ............................................ ............................... 71
Table 10-17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ....................... 72
Table 10-18 HT Bus Receive Address Window 0 Base Address (External Access) Register Definition ....................... 72
Table 10-19 HT Bus Receive Address Window 1 Enable (External Access) Register Definition .......................... 73
Table 10-20 HT Bus Receive Address Window 1 Base Address (External Access) Register Definition .......................... 73
Table 10-21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition .......................... 73
Table 10-22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition .......................... 74
Table 10-23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition .......................... 74
Table 10-24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ....................... 74
Table 10-25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ....................... 75
Table 10-26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition .......................... 75
Table 10-27 HT Bus Interrupt Vector Register Definition (1) ........................................... .................... 76
Table 10-28 Definition of HT Bus Interrupt Vector Register (2) ........................................... .................... 76
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Table 10-29 HT Bus Interrupt Vector Register Definition (3) ........................................... .................... 77
Table 10-30 HT Bus Interrupt Vector Register Definition (4) ........................................... .................... 77
Table 10-31 HT Bus Interrupt Vector Register Definition (6) ........................................... .................... 77
Table 10-32 HT Bus Interrupt Vector Register Definition (7) ........................................... .................... 77
Table 10-33 Definition of HT Bus Interrupt Vector Register (8) ........................................... .............. 78
Table 10-34 HT Bus Interrupt Enable Register Definition (1) .................................... ............... 79
Table 10-35 HT Bus Interrupt Enable Register Definition (2) .......................................... ............... 79
Table 10-36 HT Bus Interrupt Enable Register Definition (3) .......................................... ............... 79
Table 10-37 HT Bus Interrupt Enable Register Definition (4) .......................................... ............... 79
Table 10-38 HT Bus Interrupt Enable Register Definition (5) .......................................... ............... 80
Table 10-39 HT Bus Interrupt Enable Register Definition (6) .......................................... ............... 80
Table 10-40 HT Bus Interrupt Enable Register Definition (7) .......................................... ............... 80
Table 10-41 HT Bus Interrupt Enable Register Definition (8) .......................................... ............... 80
Table 10-42 Interrupt Capability Register Definition .......................................... ....................... 81
Table 10-43 Dataport register definition ........................................... ....................................... 81
Table 10-44 IntrInfo register definition (1) ........................................... ................................. 81
Table 10-45 IntrInfo register definition (2) ................................................. ................................. 81
Table 10-46 HT Bus POST Address Window 0 Enable (Internal Access) ........................................... ... 82
Table 10-47 HT Bus POST Address Window 0 Base Address (Internal Access) ....................................... ... 82
Table 10-48 HT Bus POST Address Window 1 Enable (Internal Access) ........................................... ... 83
Table 10-49 HT Bus POST Address Window 1 Base Address (Internal Access) ........................................... ... 83
Table 10-50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ..................................... ....... 83
Table 10-51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ................................ ....... 84
Table 10-52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ...................................... ....... 84
Table 10-53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ...................................... ....... 84
Table 10-54 HT Bus Uncache Address Window 0 Enable (Internal Access) ........................................... . 85
Table 10-55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........................................... . 85
Table 10-56 HT Bus Uncache Address Window 1 Enable (Internal Access) ........................................... . 85
Table 10-57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........................................... . 86
Table 10-58 HT Bus Uncache Address Window 2 Enable (Internal Access) ........................................... . 86
Table 10-59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........................................ . 86
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Table 10-60 HT Bus Uncache Address Window 3 Enable (Internal Access) ........................................... . 87
Table 10-61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........................................... . 87
Table 10-62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ....................... 87
Table 10-63 HT Bus P2P Address Window 0 Base Address (External Access) Register Definition .......................... 88
Table 10-64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition .......................... 88
Table 10-65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition .......................... 88
Table 10-66 Command Send Buffer Size Register ................................................. .......................... 89
Table 10-67 Data transmission buffer size register .................................................. .......................... 89

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Table 10-68 Send Buffer Debug Register .................................... ................................. 90
Table 10-69 Impedance Matching Control Register .................................... ................................. 91
Table 10-70 Revision ID Register ........................................... .................................... 91
Table 10-71 Error Retry Control Register .................................... ............................. 91
Table 10-72 Retry Count Register ........................................... .................................... 92
Table 10-73 Link Train Register ........................................... ....................................... 92
Table 10-74 Training 0 Timeout Short Timer Register ........................................... ..................... 93
Table 10-75 Training 0 Timeout Long Count Register ........................................... ..................... 94
Table 10-76 Training 1 Count Register .......................................... ............................... 94
Table 10-77 Training 2 Count Register .......................................... ............................... 94
Table 10-78 Training 3 Count Register .......................................... ............................... 95
Table 10-79 Software Frequency Configuration Register .......................................... ................................. 95
Table 10-80 PHY Configuration Register ........................................... ....................................... 96
Table 10-81 Link Initialization Debug Register ................................................. .............................. 97
Table 10-82 LDT debug registers ........................................... ............................................. 98
Table 11-1 PCI Controller Configuration Header ............................................ ............................................. 101
Table 11-2 PCI Control Register .......................................... .......................................... 102
Table 11-3 PCI / PCIX bus request and response line allocation ..................................... ....................... 105
Table 11-4 LPC Controller Address Space Distribution ........................................... ................................. 106
Table 11-5 Meaning of LPC Configuration Register .......................................... ....................................... 106
Table 11-6 SPI controller address space distribution ........................................... ............................. 114
Table 11-7 IO Control Register ........................................... .................................................. 118
Table 11-8 Detailed description of registers ........................................... ............................................. 119
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
1 Overview
1.1 Introduction to Loongson series processors
Loongson processor mainly includes three series. Loongson No. 1 processor and its IP series are mainly for embedded applications.
Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service
Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded applications,
Some low-end Loongson 3 can also be used for some desktop applications. The above three series will be developed in parallel.
Loongson 3 multi-core series processors are based on a scalable multi-core interconnect architecture design, integrating multiple high-performance on a single chip
The processor core and a large number of level 2 caches, and the interconnection of multiple chips through high-speed I / O interfaces to form a larger scale
system.
The scalable interconnection structure adopted by Godson 3 is shown in Figure 1-1 below. Both the on-chip and multi-chip systems of Godson No. 3 adopt two
Dimension mesh interconnection structure, where each node is composed of 8 * 8 crossbars, each crossbar is connected to four processor cores
And four shared caches, and interconnect with other nodes in four directions of east (E) south (N) west (W) north (N). therefore,
2 * 2 meshes can be connected to 16 processor cores, and 4 * 4 meshes can be connected to 64 processor cores.
(B)(A)
8x8 switch
P0 P1 P2 P3
L2 L2 L2
E
S
W
N
E
S
W
N
(C)
L2
Loongson No. 3 node and two-dimensional interconnection structure, (a) node structure, (b) 2 * 2 mesh network connected to 16 processors, (c)
The 4 * 4 mesh network connects 64 processors.

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Figure 1-1 Loongson No. 3 system structure
The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and shared
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Cache, memory controller and IO controller. Among them, the first level AXI crossbar switch (called X1 Switch, referred to as X1)
Connect the processor and shared cache. The second level crossbar switch (called X2 Switch, referred to as X2 for short) is connected to share Cache and
Memory controller.
Figure 1-2 Loongson No. 3 node structure
In each node, up to 8 * 8 X1 crossbars are connected to four GS464 processor cores through four Master ports
(P0, P1, P2, P3 in the figure), connected to four interleave shared caches with four slave ports through four slave ports
Block (S0, S1, S2, S3 in the figure), connected to the four directions of east, south, west and north through four pairs of Master / Slave
Other nodes or IO nodes (EM / ES, SM / SS, WM / WS, NM / NS in the figure).
The X2 crossbar is connected to four shared caches through four Master ports, and one is connected to at least one Slave port
Memory controller, at least one Slave port connected to a crossbar configuration module (Xconf) is used to configure this node
The X1 and X2 address windows, etc. You can also connect more memory controllers and IO ports as needed.
1.2 Introduction to Godson 3A3000 / 3B3000
Loongson 3A3000 / 3B3000 is a process upgrade version of Loongson 3A2000 / 3B2000 quad-core processor.
Compared with the core 3A1000, PLL_AVDD is changed from 2.5V to 1.8V, which is more used than the Loongson 3A2000 / 3B2000
PLL_AVDD. Loongson 3A3000 / 3B3000 is a single-node 4-core processor, manufactured using 28nm process,
The main frequency is 1.2GHz-1.5GHz, and the main technical characteristics are as follows:
EM
X1 Switch
S0
P0 P1 P2 P3
S1 S2 S3
WM
WS
NM
SM
NS
ES
SS
m0 m1 m2 m3 m4 m5 m6 m7
s0 s1 s2 s3 s4 s5 s6 s7
MA0 MA1 MA2 MA3
X2 Switch
MCXconf

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• Four 64-bit super-scalar GS464e high-performance processor cores are integrated on-chip;
•On-chip integrated 8MB split shared three-level cache (composed of 4 individual modules, each module has a capacity of 2MB);
•Maintain the cache consistency of multi-core and I / O DMA access through the directory protocol;
• Two 64-bit DDR2 / 3 controllers with ECC and 667MHz are integrated on-chip;
•3B3000 integrates two 16-bit 1.6GHz HyperTransport controllers (hereinafter referred to as HT);
• 3A3000 on-chip HT1 is a 16-bit 1.6GHz HT controller, HT0 is not available;
• Each 16-bit HT port is split into two 8-way HT ports for use.
•On-chip integrated 32-bit 33MHz PCI;
• Integrate 1 LPC, 2 UARTs, 1 SPI, 16 GPIO interfaces on-chip.
Compared with Loongson 3A2000 / 3B2000, the main improvements are as follows:
•Processor core microstructure upgrade;
• Memory controller structure and frequency upgrade;
•HT controller structure and frequency upgrade;
•The performance of the whole chip is optimized and improved.
The overall architecture of Loongson 3A3000 / 3B3000 chip is based on two-level interconnection. The structure is shown in Figures 1-3 below.
Figure 1-3 Loongson 3A3000 / 3B3000 chip structure
The first level interconnection uses a 6x6 crossbar switch, which is used to connect four GS464e cores (as a master device) and four shares
Cache module (as a slave device), and two IO ports (each port uses a Master and a Slave).
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Each IO port connected to the first-level interconnect switch is connected to a 16-bit HT controller, and each 16-bit HT port can also
Used as two 8-bit HT ports. The HT controller is connected to the first-level interconnect switch through a DMA controller. The DMA controller
The controller is responsible for the DMA control of the IO and the maintenance of the consistency between the slices. The DMA controller of Godson 3 can also be configured
Realize prefetching and matrix transposition or transfer.
The second level interconnection uses a 5x4 crossbar switch to connect 4 shared Cache modules (as the master device), two DDR2 / 3
Memory controller, low-speed high-speed I / O (including PCI, LPC, SPI, etc.) and configuration register module inside the chip.
The above two-level interconnect switches all use separate data channels for reading and writing. The width of the data channel is 128 bits.

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The processor core has the same frequency to provide high-speed on-chip data transmission.
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2 System configuration and control
2.1 Chip working mode
According to the structure of the system, Loongson 3A3000 / 3B3000 mainly includes three working modes:
● Single chip mode. The system contains only one Loongson 3A3000 / 3B3000, which is a symmetric multiprocessor system (SMP);
● Multi-chip interconnect mode. The system contains 2 or 4 Loongson 3A3000 / 3B3000, through Loongson
The HT ports of 3A3000 / 3B3000 are interconnected, which is a non-uniform memory multiprocessor system (CC-NUMA)
●Large-scale interconnection model. Large-scale multi-chip expansion interconnection through dedicated expansion bridges, forming a large-scale non-uniform
Uniform access to multi-processor systems (CC-NUMA).
2.2 Description of control pins
The main control pins include DO_TEST, ICCC_EN, NODE_ID [1: 0], CLKSEL [15: 0], PCI_CONFIG.
Table 2- 1 Control pin description
signal Up and down effect

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DO_TEST pull up
1'b1 means function mode
1'b0 means test mode
ICCC_EN drop down
1'b1 means multi-chip consistent interconnect mode
1'b0 means single chip mode
NODE_ID [1: 0] Indicates the processor number in multi-chip consistent interconnect mode
CLKSEL [15: 0]
HT clock control
signal effect
CLKSEL [15]
1'b1 means the HT controller frequency is only set by hardware
1'b0 means HT controller frequency can be set by software
CLKSEL [14]
1'b1 means HT PLL uses normal clock input
1'b0 means HT PLL uses differential clock input
CLKSEL [13:12]
2'b00 means the PHY clock is 1.6GHZ
2'b01 indicates that the PHY clock is 3.2GHZ
2'b10 means the PHY clock is 1.2GHz
2'b11 means the PHY clock is 2.4GHz
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CLKSEL [11:10]
2'b00 indicates that the HT controller clock is divided by 8 of the PHY clock
2'b01 indicates that the HT controller clock is divided by 4 of the PHY clock
2'b10 means the HT controller clock is divided by 2 of the PHY clock
2'b11 indicates that the HT controller clock is SYSCLOCK
Note: When CLKSEL [13:10] == 4'b1111, the HT controller clock is in bypass mode and used directly
External input 100MHz reference clock
MEM clock control
signal effect
CLKSEL [9: 5]
5'b11111 means MEM clock directly uses memclk
5'b01111 indicates that the MEM clock is set by software. For the setting method, see
Section 2.6
In other cases, the MEM clock is
memclk * (clksel [8: 5] +30) / (clksel [9] +3)
Note:
memclk * (clksel [8: 5] +30) must be 1.2GHz ~ 3.2GHz
memclk is the input reference clock, which must be 20 ~ 40MHz
CORE clock control
signal effect
CLKSEL [4: 0]
5'b11111 indicates that the CORE clock directly uses sysclk
5'b011xx indicates that the CORE clock is set by software. For the setting method, see
Instructions in Section 2.6.
5'b01111 is normal working mode, otherwise it is debugging mode
5'b0110x indicates that the processor interface is in asynchronous mode
5'b011x0 means delayed debug control mode
In other cases, the CORE clock is
sysclk * (clksel [3: 0] +30) / (clksel [4] +1)
Note:

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sysclk * (clksel [3: 0] +30) must be 1.2GHz ~ 3.2GHz
sysclk is the input reference clock, which must be 20 ~ 40MHz
PCI_CONFIG [7: 0]
IO configuration control
7 HT bus cold start is forced to 1.0 mode
6: 4 needs to be set to 000
3 PCI master mode
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2Need to be set to 0
1Use external PCI arbitration
0Use SPI boot function
2.3 Cache consistency
Loongson 3A3000 / 3B3000 maintains the cache between the processor and the I / O accessed through the HT port
It is consistent, but the hardware does not maintain the cache consistency of the I / O devices connected to the system through PCI. During driver development,
When DMA (Direct Memory Access) transmission is performed on a device connected via PCI, the software needs to perform Cache
Consistency maintenance.
2.4 Distribution of physical address space at the node level of the system
The system physical address distribution of Loongson No. 3 series processors adopts a globally accessible hierarchical addressing design
The extensions developed by the system are compatible. The physical address width of the entire system is 48 bits. According to the upper 4 bits of the address, the entire address sp
It is evenly distributed to 16 nodes, that is, each node is allocated 44-bit address space.
Loongson 3A3000 / 3B3000 processor can directly use 4 chips to connect directly to build CC-NUMA system.
The processor number is determined by the pin NODEID, and the address space of each chip is distributed as follows:
Table 2-2 Node-level system global address distribution
Chip node number (NODEID) Address [47:44] bits starting address End address
0 0 0x0000_0000_0000 0x0FFF_FFFF_FFFF
1 1 0x1000_0000_0000 0x1FFF_FFFF_FFFF
2 2 0x2000_0000_0000 0x2FFF_FFFF_FFFF
3 3 0x3000_0000_0000 0x3FFF_FFFF_FFFF
Loongson 3A3000 / 3B3000 uses a single-node 4-core configuration, so Loongson 3A3000 / 3B3000 chip integrated DDR
The corresponding addresses of the memory controller, HT bus, and PCI bus are included from 0x0 (inclusive) to 0x1000_0000_0000 (not
The 44-bit address is in each node, and the 44-bit address space is further evenly distributed to the most likely connection within the node.
8 more devices. The lower 43 bits of addresses are owned by 4 shared cache modules, and the higher 43 bits of addresses are further
The [43:42] bits are distributed to devices connected to the 4 directional ports. According to the different configuration of chip and system structure, if
If there is no slave device connected to a port, the corresponding address space is reserved address space, and access is not allowed.

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The slave devices corresponding to the address space of the first-level crossbar in Loongson 3A3000 / 3B3000 are as follows:
Table 2-3 Address distribution in nodes
device Address [43:41] Start address within the node Node end address
Shared Cache 0,1,2,3 0x000_0000_0000 0x7FF_FFFF_FFFF
HT0 controller 6 0xC00_0000_0000 0xDFF_FFFF_FFFF
HT1 controller 7 0xE00_0000_0000 0xFFF_FFFF_FFFF
Unlike the mapping relationship of direction ports, Loongson 3A3000 / 3B3000 can be determined according to the actual application access behavior
Set the cross-addressing mode of shared cache. The 4 shared Cache modules in the node correspond to a total of 43 address spaces, and
The address space corresponding to each module is determined according to one of the two selection bits of the address bit, and can be dynamically configured by software
modify. The configuration register named SCID_SEL is set in the system to determine the address selection bits, as shown in the following table. In default
In this case, it is distributed by means of [7: 6] status hash, that is, two bits of address [7: 6] determine the corresponding shared cache number.
The register address is 0x3FF00400.
Table 2-4 Address distribution in nodes
SCID_SEL Address bit selection SCID_SEL Address bit selection
4'h0 7: 6 4'h8 23:22
4'h1 9: 8 4'h9 25:24
4'h2 11:10 4'ha 27:26
4'h3 13:12 4'hb 29:28
4'h4 15:14 4'hc 31:30
4'h5 17:16 4'hd 33:32
4'h6 19:18 4'he 35:34
4'h7 21:20 4'hf 37:36
2.5 Distribution of physical address space within a node
The default distribution of the internal 44-bit physical address of each node of Loongson 3A3000 / 3B3000 processor is shown in the following table:
Table 2-2 44-bit physical address distribution in the node
starting address End address name Explanation
0x0000_0000_0000 0x0000_0FFF_FFFF RAM Need to use two-level crossbar for mapping
0x0000_1000_0000 0x0000_1FFF_FFFF Low speed IO Need to use two-level crossbar for mapping
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0x2000_0000_0000 0x2FFF_FFFF_FFFF 2 2
0x3000_0000_0000 0x3FFF_FFFF_FFFF 3 3
Loongson 3A3000 / 3B3000 uses a single-node 4-core configuration, so Loongson 3A3000 / 3B3000 chip integrated DDR
2.6 Address Routing Distribution and Configuration

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The routing of Loongson 3A3000 / 3B3000 is mainly realized through the two-stage crossbar of the system. First-level crossbar can
Each Master port receives requests for routing configuration, each Master port has 8 address windows, you can
Complete target routing in 8 address windows. Each address window consists of three 64-bit registers BASE, MASK and MMAP
Composed, BASE is aligned in K bytes; MASK adopts a format similar to the high bit of the netmask; the lower three bits of MMAP indicate the pair
According to the number of the target Slave port, MMAP [4] means to allow instruction fetch, MMAP [5] means to allow block read, MMAP [6] means
Allow interleaved access to Scache to be enabled, MMAP [7] means window is enabled.
Table 2-5 The space access attributes corresponding to the MMAP field
[7] [6] [5] [4]
Window enableAllow interleaved access to SCACHE, valid when the slave number is 0, according to the above
A section of SCID_SEL configuration routes requests that hit window addresses
Block read Allow fetching
Window hit formula: (IN_ADDR & MASK) == BASE
Since Loongson 3 uses fixed routing by default, the configuration window is closed when the power is turned on.
System software is required to enable and configure it.
The address window conversion register is shown in the table below.
Table 2-6 Register Table of Address Window of Primary Crossbar
address register address register
0x3ff0_2000 CORE0_WIN0_BASE 0x3ff0_2100 CORE1_WIN0_BASE
0x3ff0_2008 CORE0_WIN1_BASE 0x3ff0_2108 CORE1_WIN1_BASE
0x3ff0_2010 CORE0_WIN2_BASE 0x3ff0_2110 CORE1_WIN2_BASE
0x3ff0_2018 CORE0_WIN3_BASE 0x3ff0_2118 CORE1_WIN3_BASE
0x3ff0_2020 CORE0_WIN4_BASE 0x3ff0_2120 CORE1_WIN4_BASE
0x3ff0_2028 CORE0_WIN5_BASE 0x3ff0_2128 CORE1_WIN5_BASE
0x3ff0_2030 CORE0_WIN6_BASE 0x3ff0_2130 CORE1_WIN6_BASE
0x3ff0_2038 CORE0_WIN7_BASE 0x3ff0_2138 CORE1_WIN7_BASE
0x3ff0_2040 CORE0_WIN0_MASK 0x3ff0_2140 CORE1_WIN0_MASK
0x3ff0_2048 CORE0_WIN1_MASK 0x3ff0_2148 CORE1_WIN1_MASK
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0x3ff0_2050 CORE0_WIN2_MASK 0x3ff0_2150 CORE1_WIN2_MASK
0x3ff0_2058 CORE0_WIN3_MASK 0x3ff0_2158 CORE1_WIN3_MASK
0x3ff0_2060 CORE0_WIN4_MASK 0x3ff0_2160 CORE1_WIN4_MASK
0x3ff0_2068 CORE0_WIN5_MASK 0x3ff0_2168 CORE1_WIN5_MASK
0x3ff0_2070 CORE0_WIN6_MASK 0x3ff0_2170 CORE1_WIN6_MASK
0x3ff0_2078 CORE0_WIN7_MASK 0x3ff0_2178 CORE1_WIN7_MASK
0x3ff0_2080 CORE0_WIN0_MMAP 0x3ff0_2180 CORE1_WIN0_MMAP
0x3ff0_2088 CORE0_WIN1_MMAP 0x3ff0_2188 CORE1_WIN1_MMAP
0x3ff0_2090 CORE0_WIN2_MMAP 0x3ff0_2190 CORE1_WIN2_MMAP
0x3ff0_2098 CORE0_WIN3_MMAP 0x3ff0_2198 CORE1_WIN3_MMAP
0x3ff0_20a0 CORE0_WIN4_MMAP 0x3ff0_21a0 CORE1_WIN4_MMAP
0x3ff0_20a8 CORE0_WIN5_MMAP 0x3ff0_21a8 CORE1_WIN5_MMAP
0x3ff0_20b0 CORE0_WIN6_MMAP 0x3ff0_21b0 CORE1_WIN6_MMAP
0x3ff0_20b8 CORE0_WIN7_MMAP 0x3ff0_21b8 CORE1_WIN7_MMAP

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0x3ff0_2200 CORE2_WIN0_BASE 0x3ff0_2300 CORE3_WIN0_BASE
0x3ff0_2208 CORE2_WIN1_BASE 0x3ff0_2308 CORE3_WIN1_BASE
0x3ff0_2210 CORE2_WIN2_BASE 0x3ff0_2310 CORE3_WIN2_BASE
0x3ff0_2218 CORE2_WIN3_BASE 0x3ff0_2318 CORE3_WIN3_BASE
0x3ff0_2220 CORE2_WIN4_BASE 0x3ff0_2320 CORE3_WIN4_BASE
0x3ff0_2228 CORE2_WIN5_BASE 0x3ff0_2328 CORE3_WIN5_BASE
0x3ff0_2230 CORE2_WIN6_BASE 0x3ff0_2330 CORE3_WIN6_BASE
0x3ff0_2238 CORE2_WIN7_BASE 0x3ff0_2338 CORE3_WIN7_BASE
0x3ff0_2240 CORE2_WIN0_MASK 0x3ff0_2340 CORE3_WIN0_MASK
0x3ff0_2248 CORE2_WIN1_MASK 0x3ff0_2348 CORE3_WIN1_MASK
0x3ff0_2250 CORE2_WIN2_MASK 0x3ff0_2350 CORE3_WIN2_MASK
0x3ff0_2258 CORE2_WIN3_MASK 0x3ff0_2358 CORE3_WIN3_MASK
0x3ff0_2260 CORE2_WIN4_MASK 0x3ff0_2360 CORE3_WIN4_MASK
0x3ff0_2268 CORE2_WIN5_MASK 0x3ff0_2368 CORE3_WIN5_MASK
0x3ff0_2270 CORE2_WIN6_MASK 0x3ff0_2370 CORE3_WIN6_MASK
0x3ff0_2278 CORE2_WIN7_MASK 0x3ff0_2378 CORE3_WIN7_MASK
0x3ff0_2280 CORE2_WIN0_MMAP 0x3ff0_2380 CORE3_WIN0_MMAP
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0x3ff0_2288 CORE2_WIN1_MMAP 0x3ff0_2388 CORE3_WIN1_MMAP
0x3ff0_2290 CORE2_WIN2_MMAP 0x3ff0_2390 CORE3_WIN2_MMAP
0x3ff0_2298 CORE2_WIN3_MMAP 0x3ff0_2398 CORE3_WIN3_MMAP
0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff0_23a0 CORE3_WIN4_MMAP
0x3ff0_22a8 CORE2_WIN5_MMAP 0x3ff0_23a8 CORE3_WIN5_MMAP
0x3ff0_22b0 CORE2_WIN6_MMAP 0x3ff0_23b0 CORE3_WIN6_MMAP
0x3ff0_22b8 CORE2_WIN7_MMAP 0x3ff0_23b8 CORE3_WIN7_MMAP
0x3ff0_2600 HT0_WIN0_BASE 0x3ff0_2700 HT1_WIN0_BASE
0x3ff0_2608 HT0_WIN1_BASE 0x3ff0_2708 HT1_WIN1_BASE
0x3ff0_2610 HT0_WIN2_BASE 0x3ff0_2710 HT1_WIN2_BASE
0x3ff0_2618 HT0_WIN3_BASE 0x3ff0_2718 HT1_WIN3_BASE
0x3ff0_2620 HT0_WIN4_BASE 0x3ff0_2720 HT1_WIN4_BASE
0x3ff0_2628 HT0_WIN5_BASE 0x3ff0_2728 HT1_WIN5_BASE
0x3ff0_2630 HT0_WIN6_BASE 0x3ff0_2730 HT1_WIN6_BASE
0x3ff0_2638 HT0_WIN7_BASE 0x3ff0_2738 HT1_WIN7_BASE
0x3ff0_2640 HT0_WIN0_MASK 0x3ff0_2740 HT1_WIN0_MASK
0x3ff0_2648 HT0_WIN1_MASK 0x3ff0_2748 HT1_WIN1_MASK
0x3ff0_2650 HT0_WIN2_MASK 0x3ff0_2750 HT1_WIN2_MASK
0x3ff0_2658 HT0_WIN3_MASK 0x3ff0_2758 HT1_WIN3_MASK
0x3ff0_2660 HT0_WIN4_MASK 0x3ff0_2760 HT1_WIN4_MASK
0x3ff0_2668 HT0_WIN5_MASK 0x3ff0_2768 HT1_WIN5_MASK
0x3ff0_2670 HT0_WIN6_MASK 0x3ff0_2770 HT1_WIN6_MASK
0x3ff0_2678 HT0_WIN7_MASK 0x3ff0_2778 HT1_WIN7_MASK
0x3ff0_2680 HT0_WIN0_MMAP 0x3ff0_2780 HT1_WIN0_MMAP