Loongson 3A3000 User manual

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Loongson 3A3000 / 3B3000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.3
2017 Nian 4 Yue
Loongson Zhongke Technology Co., Ltd.
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Copyright Notice

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The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual
No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated
Legal responsibility.
Disclaimer
This document only provides periodic information, and the content can be updated at any time according to the actual situation of the product without notice. Ruin
The company does not assume any responsibility for direct or indirect losses caused by improper use of documents.
Loongson Zhongke Technology Co., Ltd.
Loongson Technology Corporation Limited
Address: Building 2, Longxin Industrial Park, Zhongguancun Environmental Protection Technology Demonstration Park, Haidian District, Beijing
Building No. 2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Telephone (Tel): 010-62546668
Fax: [phone]
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Reading guide
"Godson 3A3000 / 3B3000 Processor User Manual" is divided into the first and second volumes.
"Loongson 3A3000 / 3B3000 Processor User Manual" is divided into two parts, the first part introduces Loongson 3A3000 / 3B3000
Multi-core processor architecture and register descriptions, on-chip system architecture, main module functions and configuration, register list and
The domain is described in detail.
Volume 2 of the "Loongson 3A3000 / 3B3000 Processor User Manual" introduces Loongson in detail from the perspective of system software developers
3A3000 / 3B3000 uses the GS464e high-performance processor core.

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revise history
Document update record
Document name: Loongson 3A3000 / 3B3000 Processor User Manual
--volume One
version number V1.3
founder: Chip R & D Department
Creation Date: 2017-04-13
Update history
Serial numberUpdated version number update content
1 2016-06-14 V1.0 initial version
2 2016-09-14 V1.1 Updated some PLL configuration register descriptions, updated software and hardware changes descriptions
3 2016-11-25 V1.2 Add register description of BBGEN section
4 2017-04-13 V1.3 Add SPI address space description
Manual feedback: [email protected]
You can also submit chip production to our company through the problem feedback website http://bugs.loongnix.org/
Problems in the use of products, and obtain technical support.

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table of Contents
1 Overview................................................ .................................................. ........................ 11
1.1 Introduction to Loongson series processors ............................................ ....................................... 11
1.2 Introduction to Godson 3A3000 / 3B3000 ....................................................... ................................. 12
2 System Configuration and Control ....................................... .................................................. ....... 15
2.1 Chip working mode ................................................ .................................................. .15
2.2 Description of control pins ....................................... .................................................. ..15
2.3 Cache consistency ................................................. .................................................. ..17
2.4 Physical address space distribution at the node level of the system ............................................ ........................ 17
2.5 Address Routing Distribution and Configuration ............................................ ....................................... 19
2.6 Chip Configuration and Sampling Register .................................................. ............................... 25
3 GS464e processor core ................................................ .................................................. ... 30
4 Shared Cache (SCache) ................................................. ................................................... 32
5 Matrix processing accelerator ................................................. .................................................. ... 34
6 Interruption and communication between processor cores .................................... .......................................... 37
7 I / O interrupt ................................................ .................................................. .................... 40
8 Temperature sensor ................................................ .................................................. ............. 43
8.1 Real-time temperature sampling ............................................. .................................................. .43
8.2 High and low temperature interrupt trigger ................................................ ................................................ 43
8.3 High temperature automatic frequency reduction setting ............................................ ....................................... 44
9 DDR2 / 3 SDRAM controller configuration .......................................... ..................................... 46
9.1 DDR2 / 3 SDRAM Controller Function Overview .................................................. ..................... 46
9.2 DDR2 / 3 SDRAM read operation protocol .......................................... ................................. 46
9.3 DDR2 / 3 SDRAM write operation protocol .......................................... ................................. 47
9.4 DDR2 / 3 SDRAM parameter configuration format .......................................... ........................ 47
9.5 Software Programming Guide ................................................. .................................................. .51
9.5.1 Initialization ............................................. ................................................... 51
9.5.2 Control of reset pin .......................................... .................................... 51
9.5.3 Leveling ................................................. .................................................. 53

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9.5.3.1 Write Leveling ................................................ ........................... 53
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9.5.3.2 Gate Leveling ............................................. ................................... 54
9.5.4 Initiate MRS commands separately ........................................... ............................... 55
9.5.5 Arbitrary operation control bus .......................................... ............................... 56
9.5.6 Self-loop test mode control .......................................... ................................. 56
9.5.7 ECC function usage control .......................................... ................................ 57
10 HyperTransport Controller ............................................. ....................................... 58
10.1 HyperTransport hardware setup and initialization .................................................. .............. 58
10.2 HyperTransport protocol support ................................................. ........................... 61
10.3 HyperTransport interrupt support ................................................. ...................... 62
10.4 HyperTransport Address Window ................................................... ...................... 62
10.4.1 HyperTransport Space ............................................. ........................... 62
10.4.2 Internal window configuration of HyperTransport controller .................................................. .... 63
10.5 Configuration Register ................................................. .................................................. ..64
10.5.1 Bridge Control ............................................. ............................... 66
10.5.2 Capability Registers ................................................ ................... 66
10.5.3 User-defined register ................................................ .................................... 69
10.5.4 Receive diagnostic register .................................................. ................................ 71
10.5.5 Interrupt routing mode selection register .......................................... .................. 71
10.5.6 Receive buffer initial register .......................................... ............................ 71
10.5.7 Receive Address Window Configuration Register .......................................... .................. 72
10.5.8 Interrupt Vector Register ............................................ ................................ 75
10.5.9 Interrupt Enable Register ........................................... ................................. 78
10.5.10 Interrupt Discovery & Configuration ...................................... 81
10.5.11 POST address window configuration register .......................................... ..................... 82
10.5.12 Prefetchable address window configuration register ........................................... .................... 83
10.5.13 UNCACHE Address Window Configuration Register .......................................... ............... 84
10.5.14 P2P Address Window Configuration Register .......................................... ....................... 87
10.5.15 Command send buffer size register .......................................... ...................... 89
10.5.16 Data transmission buffer size register .......................................... ...................... 89
10.5.17 Send buffer debug register ........................................... ....................... 89
10.5.18 PHY impedance matching control register .......................................... ....................... 90
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10.5.19 Revision ID Register ................................................. ............................ 91
10.5.20 Error Retry Control Register ........................................... ..................... 91
10.5.21 Retry Count Register ................................................. ...................... 92
10.5.22 Link Train Register .................................................. ........................ 92
10.5.23 Training 0 Timeout Short Timer Register ................................................. ............. 93
10.5.24 Training 0 Time-out timer register .................................................. ............. 94
10.5.25 Training 1 Count Register ................................................. ....................... 94
10.5.26 Training 2 Count Register ........................................... ....................... 94
10.5.27 Training 3 Count Register ........................................... ....................... 94
10.5.28 Software Frequency Configuration Register ........................................... ............................. 95
10.5.29 PHY Configuration Register ................................................. .............................. 96
10.5.30 Link initialization debug register .......................................... .......................... 97
10.5.31 LDT debug register .................................................. ............................... 97
10.6 Access method of HyperTransport bus configuration space .......................................... .... 98
10.7 HyperTransport multiprocessor support .................................................. ...................... 98
11 Low speed IO controller configuration ............................................ .......................................... 101
11.1 PCI Controller ................................................. .................................................. ..101
11.2 LPC Controller ................................................. .................................................. ..106
11.3 UART Controller .............................................. .................................................. 107
11.3.1 Data Register (DAT) ................................................ ........................... 108
11.3.2 Interrupt Enable Register (IER) ................................................. ........................... 108
11.3.3 Interrupt Identification Register (IIR) .................................................. ........................... 108
11.3.4 FIFO Control Register (FCR) .................................................. ................... 109
11.3.5 Line Control Register (LCR) .................................................. .................... 109
11.3.6 MODEM Control Register (MCR) .................................................. .................. 111
11.3.7 Line Status Register (LSR) .................................................. .................... 111
11.3.8 MODEM Status Register (MSR) ...................................................... ................ 113
11.3.9 Frequency Division Latch .......................................... ........................................... 113
11.4 SPI Controller .............................................. .................................................. ..114
11.4.1 Control Register (SPCR) ................................................ ......................... 114
11.4.2 Status Register (SPSR) .......................................... ......................... 115
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11.4.3 Data Register (TxFIFO) ................................................ ............................ 115
11.4.4 External Register (SPER) ................................................ ......................... 115
11.4.5 Parameter control register (SFC_PARAM) ................................................. ........... 116
11.4.6 Chip Select Control Register (SFC_SOFTCS) ................................................. ........... 116
11.4.7 Timing control register (SFC_TIMING) .................................................. .......... 117
11.5 IO Controller Configuration ....................................... ................................................... 118
12 Chip Configuration Register List .......................................... ................................. 122
13 Software and Hardware Design Guidelines ................................................ .................................................. ... 162
13.1 Hardware modification guide ................................................. ............................................. 162

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13.2 Description of Frequency Setting ............................................. ............................................. 163
13.3 PMON Change Guide ................................................ ....................................... 163
13.4 Guidelines for kernel changes ............................................. ............................................. 164
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Loongson 3A3000 / 3B3000 processor user manual picture directory
Figure catalog
Figure 1-1 Loongson No. 3 system structure ............................................ ................................................. 11
Figure 1-2 Loongson No. 3 node structure ............................................ ........................................... 12
Figure 1-3 Godson 3A3000 / 3B3000 chip structure ........................................... ............................. 13
Figure 3-1 GS464e structure diagram .......................................... .................................................. ... 31
Figure 7-1 Loongson 3A3000 / 3B3000 processor interrupt routing diagram ..................................... ........ 40
Figure 9-1 DDR2 SDRAM read operation protocol .................................................. ................................. 47
Figure 9-2 DDR2 SDRAM write operation protocol .................................................. ................................. 47
Figure 10-1 HT protocol configuration access in Loongson 3A3000 / 3B3000 .................................... ....... 98
Figure 10-2 Four-piece Loongson No. 3 interconnection structure .......................................... ....................................... 99
Figure 10-3 Two-chip Loongson No. 3 8-bit interconnection structure ..................................... ........................... 100
Figure 10-4 Two-chip Loongson No. 3 16-bit interconnection structure ........................................... ............................... 100
Figure 11-1 Configure the read and write bus address generation ........................................... ............................... 105

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Table directory
Table 2-1 Control pin description .................................... .................................................. ..... 15
Table 2-2 Node-level system global address distribution .......................................... ................................. 17
Table 2-3 Address distribution in nodes ............................................ .......................................... 18
Table 2-4 Address distribution in nodes ............................................ .......................................... 18
Table 2-5 The space access attributes corresponding to the MMAP field ...................................... ....................... 19
Table 2-6 Primary Crossbar Address Window Register Table .......................................... ..................... 19
Table 2-7 Correspondence between the slave device number and the module at the secondary XBAR ..................................... .....twenty two
Table 2-8 The space access attributes corresponding to the MMAP field ............................................ .......................twenty two
Table 2-9 Secondary XBAR address window conversion register table ............................................ .......................twenty two
Table 2-10 Secondary XBAR default address configuration .......................................... .............................. 25
Table 2-11 Chip Configuration Register (Physical Address 0x1fe00180) ........................................... ......... 25
Table 2-12 Chip sampling register (physical address 0x1fe00190) ........................................... ......... 25
Table 2-13 Chip node and processor core software frequency multiplication setting register (physical address 0x1fe001b0) ... 27
Table 2-14 Chip memory and HT clock software frequency multiplier setting register (physical address 0x1fe001c0) ... 28
Table 2-15 Chip processor core software frequency division setting register (physical address 0x1fe001d0) ... 28
Table 4-1 Shared Cache Lock Window Register Configuration ........................................... ............................. 33
Table 5-1 Matrix processing programming interface description ............................................ ................................. 34
Table 5-2 Matrix processing register address description ............................................ .............................. 35
Table 5-3 Trans_ctrl register description ................................................ ..................................... 35
Table 5-4 Trans_status register description ................................................. ................................. 36
Table 6-1 Inter-processor interrupt related registers and their function descriptions ................................. ............ 37
Table 6-2 Interrupt and communication register list of processor core 0 ..................................... ................. 37
Table 6-3 List of Internuclear Interrupts and Communication Registers of No. 1 Processor Core ................................. .............. 38
Table 6-4 List of Internuclear Interrupts and Communication Registers of No. 2 Processor Core ....................................... .............. 38
Table 6-5 List of Internuclear Interrupts and Communication Registers of Processor Core 3 ................................. .............. 38
Table 7-1 Interrupt Control Register ........................................... .................................................. .41
Table 7-2 IO Control Register Address .................................... ................................................... 41

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Table 7-3 Description of Interrupt Routing Register ............................................ ....................................... 42
Table 7-4 Interrupt Routing Register Address .................................... ........................................... 42
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Table 8-1 Temperature sampling register description .................................... ........................................... 43
Table 8-2 High and low temperature interrupt register description ............................................ ....................................... 44
Table 8-3 Description of high-temperature down-frequency control register ........................................... ................................ 45
Table 10-1 HyperTransport bus related pin signals ................................................. ............... 58
Table 10-2 Commands that the HyperTransport receiver can receive .......................................... .................. 61
Table 10-3 Commands to be sent out in two modes .................................... ......................... 61
Table 10-4 Default Address Window Distribution of the Four HyperTransport Interfaces ................................. 62
Table 10-5 Address window distribution inside HyperTransport interface of Loongson No. 3 processor ................... 63
Table 10-6 Address window provided in HyperTransport interface of Loongson 3A3000 / 3B3000 processor ... 63
Table 10-7 Software visible register list .......................................... ....................................... 64
Table 10-8 Bus Reset Control Register Definition ............................................ ...................... 66
Table 10-9 Definition of Command, Capabilities Pointer, Capability ID registers ..................... 66
Table 10-10 Link Config, Link Control register definition .......................................... ............. 67
Table 10-11 Definition of Revision ID, Link Freq, Link Error, Link Freq Cap Registers ............ 68
Table 10-12 Definition of Feature Capability Register .................................... ................... 69
Table 10-13 MISC register definition ........................................... ........................................... 69
Table 10-14 Receive Diagnostic Register ........................................... ............................................. 71
Table 10-15 Interrupt Routing Selection Register ............................................ ........................... 71
Table 10-16 Receive buffer initial register ............................................ ............................... 71
Table 10-17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ....................... 72
Table 10-18 HT Bus Receive Address Window 0 Base Address (External Access) Register Definition ....................... 72
Table 10-19 HT Bus Receive Address Window 1 Enable (External Access) Register Definition .......................... 73
Table 10-20 HT Bus Receive Address Window 1 Base Address (External Access) Register Definition .......................... 73
Table 10-21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition .......................... 73
Table 10-22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition .......................... 74
Table 10-23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition .......................... 74
Table 10-24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ....................... 74
Table 10-25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ....................... 75
Table 10-26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition .......................... 75
Table 10-27 HT Bus Interrupt Vector Register Definition (1) ........................................... .................... 76
Table 10-28 Definition of HT Bus Interrupt Vector Register (2) ........................................... .................... 76
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Table 10-29 HT Bus Interrupt Vector Register Definition (3) ........................................... .................... 77
Table 10-30 HT Bus Interrupt Vector Register Definition (4) ........................................... .................... 77
Table 10-31 HT Bus Interrupt Vector Register Definition (6) ........................................... .................... 77
Table 10-32 HT Bus Interrupt Vector Register Definition (7) ........................................... .................... 77
Table 10-33 Definition of HT Bus Interrupt Vector Register (8) ........................................... .............. 78
Table 10-34 HT Bus Interrupt Enable Register Definition (1) .................................... ............... 79
Table 10-35 HT Bus Interrupt Enable Register Definition (2) .......................................... ............... 79
Table 10-36 HT Bus Interrupt Enable Register Definition (3) .......................................... ............... 79
Table 10-37 HT Bus Interrupt Enable Register Definition (4) .......................................... ............... 79
Table 10-38 HT Bus Interrupt Enable Register Definition (5) .......................................... ............... 80
Table 10-39 HT Bus Interrupt Enable Register Definition (6) .......................................... ............... 80
Table 10-40 HT Bus Interrupt Enable Register Definition (7) .......................................... ............... 80
Table 10-41 HT Bus Interrupt Enable Register Definition (8) .......................................... ............... 80
Table 10-42 Interrupt Capability Register Definition .......................................... ....................... 81
Table 10-43 Dataport register definition ........................................... ....................................... 81
Table 10-44 IntrInfo register definition (1) ........................................... ................................. 81
Table 10-45 IntrInfo register definition (2) ................................................. ................................. 81
Table 10-46 HT Bus POST Address Window 0 Enable (Internal Access) ........................................... ... 82
Table 10-47 HT Bus POST Address Window 0 Base Address (Internal Access) ....................................... ... 82
Table 10-48 HT Bus POST Address Window 1 Enable (Internal Access) ........................................... ... 83
Table 10-49 HT Bus POST Address Window 1 Base Address (Internal Access) ........................................... ... 83
Table 10-50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ..................................... ....... 83
Table 10-51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ................................ ....... 84
Table 10-52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ...................................... ....... 84
Table 10-53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ...................................... ....... 84
Table 10-54 HT Bus Uncache Address Window 0 Enable (Internal Access) ........................................... . 85
Table 10-55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........................................... . 85
Table 10-56 HT Bus Uncache Address Window 1 Enable (Internal Access) ........................................... . 85
Table 10-57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........................................... . 86
Table 10-58 HT Bus Uncache Address Window 2 Enable (Internal Access) ........................................... . 86
Table 10-59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........................................ . 86
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Table 10-60 HT Bus Uncache Address Window 3 Enable (Internal Access) ........................................... . 87
Table 10-61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........................................... . 87
Table 10-62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ....................... 87
Table 10-63 HT Bus P2P Address Window 0 Base Address (External Access) Register Definition .......................... 88
Table 10-64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition .......................... 88
Table 10-65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition .......................... 88
Table 10-66 Command Send Buffer Size Register ................................................. .......................... 89
Table 10-67 Data transmission buffer size register .................................................. .......................... 89