Aim ACE1553-3U-4 User manual

Hardware
Manual
V01.10 Rev. A
January 2016
ACE1553-3U-4
Quad Stream
MIL-STD-1553
PXI-Express / cPCI-Express
(3U) Modules

ACE1553-3U-4 Hardware Manual
i
ACE1553-3U-4
Quad Stream
MIL-STD-1553
PXI-Express / cPCI-Express
(3U) Modules
V01.10 Rev. A
January 2016
AIM No.
60-117E0-16-0110-A
Hardware
Manual

ACE1553-3U-4 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
Sasbacher Str. 2
D-79111 Freiburg / Germany
Phone [phone]
Fax [phone]
[e-mail]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
Fax [phone]
[e-mail]
AIM GmbH –Munich Sales Office
Terofalstr. 23a
D-80689 München / Germany
Phone [phone]
Fax [phone]
[e-mail]
AIM USA LLC
Seven Neshaminy Interplex
Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[e-mail]
© AIM GmbH 2015
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by
implication in connection therewith. Specifications are subject to change without notice.

ACE1553-3U-4 Hardware Manual
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DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 Rev. A
10.06.2015
E. Carraro
First Released Version
V01.10 Rev. A
19.01.2016
E. Carraro
New layout, corrections on the discrete
section (CDR5898)

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ACE1553-3U-4 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1INTRODUCTION .....................................................................................................1
General ...............................................................................................................11.1 How This Manual is Organized............................................................................21.2
Applicable Documents.........................................................................................21.3
1.3.1 Industry Documents ........................................................................................2
1.3.2 Product Specific AIM Documents....................................................................2
2INSTALLATION.......................................................................................................3
Preparation and Precaution for Installation..........................................................3
2.1
Installation Instructions........................................................................................32.2 Connecting to other Devices................................................................................42.3
2.3.1 MIL-STD-1553-A/B Dual Channel Interface Connector ...................................5
2.3.2 General Purpose I/O Connections...................................................................5
Front Panel LEDs................................................................................................62.4
3STRUCTURE OF THE ACE1553-3U-4....................................................................7
PCI-Express Interface and BIU-I/O FPGA ...........................................................83.1
3.1.1 Global RAM Interface and Arbitration..............................................................8
3.1.2 Boot Function..................................................................................................8
3.1.3 Controller for SPI-Flash update programming .................................................8
3.1.4 MIL-STD-1553 Encoder ..................................................................................8
3.1.5 MIL-STD-1553 Decoder ..................................................................................8
3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP)..............................9
3.1.7 System & Maintenance Controller / RS232 Maintenance Interface..................9
3.1.8 External Trigger Inputs and Outputs................................................................9
3.1.9 User programmable Discrete I/O (GPIO).......................................................10
Global RAM.......................................................................................................113.2
BIU Section .......................................................................................................113.3 Physical Bus Interface with four Dual Redundant MIL-STD-1553B Channels....123.4 IRIG- and Time Code Section............................................................................143.5
3.5.1 Time Code Encoder/Decoder........................................................................14
3.5.2 Time Tag Methods ........................................................................................14
General Purpose Discrete Inputs/Outputs (GPIO) .............................................153.6 PXIe / cPCIe - Connector Pin Assignment.........................................................153.7
4PXI-EXPRESS INSTRUMENTATION BUS ...........................................................17
About the PXIe Standard...................................................................................17
4.1
4.1.1 Backplane Trigger Lines................................................................................18
4.1.2 System Reference Clock (10MHz) ................................................................20
4.1.3 Star Trigger...................................................................................................21
5TECHNICAL DATA ...............................................................................................23
6NOTES ..................................................................................................................27
Acronyms ..........................................................................................................276.1

ACE1553-3U-4 Hardware Manual
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LIST OF TABLES
Table Title Page
Table 2.1: Pin Description of the two HD-DSUB15 front-panel connectors.............................5
Table 2.2: Front Panel LED description..................................................................................6
Table 3.1: Different Coupling for MILbus channels...............................................................12
Table 3.2: IRIG-B: Binary Coded Time Tag..........................................................................14
Table 3.3 PXIe XJ4 connector's pin-out................................................................................15
Table 3.4: PXIe XJ3 connector's pin-out...............................................................................15
LIST OF FIGURES
Figure Title Page
Figure 2.1: Front Panel View..................................................................................................4
Figure 2.2: Pinout of the 15 Pin HD-DSUB connector.............................................................5
Figure 2.3: Status LED view...................................................................................................6
Figure 3.1: Block Diagram of ACE1553-3U-4.........................................................................7
Figure 3.2: GPI/O ACE-1553-3U-x circuitry..........................................................................10
Figure 3.3: GPIO Protection with external resistor................................................................11
Figure 3.4: MILbus Amplitude vs. Vcontrol ...............................................................................13
Figure 4.1: PXI architecture..................................................................................................17
Figure 4.2: PXI/Front Panel-PBI Trigger Routing capabilities................................................19

ACE1553-3U-4 Hardware Manual
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1 INTRODUCTION
General1.1
This document comprises the Hardware User’s Manual for the ACE1553-3U-4 PXIe-Module.
The document covers the hardware installation, the board connections the technical data and a
general description of the hardware architecture. For programming information please refer to
the documents listed in the “Applicable Documents” section.
The ACE1553 modules are members of AIM's new family of advanced PXI-Express cards
compliant to PCI Express V1.1 communication standard. The PCI-Express Interface is 1-lane
wide and works with 2.5 Gbit/s in transmit and receive direction.
The ACE1553 modules are used to simulate, monitor and inject protocol errors of MIL-STD-
1553A/B based databus systems. The ACE1553-3U-4 offers an interface for up to four dual-
redundant MIL-STD-1553 bus channels. Furthermore the interface implements trigger IN/OUT
functions for Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM), as well as 2
user programmable Discrete I/O signals.
Additionally, a free-wheeling IRIG-B time code generator allows the user to synchronize to
either the onboard generated time code or the time code of an external board with a resolution
of 1us.
Transformer-, Direct-, Network Emulation- and Isolated Coupling- Modes are available at the
external interface connector. A standard breakout cable (2.0 m) is available for the ACE1553
card from HD-DSUB15 connector to four (two, if ACE1553-3U-1 module) PL-75 Twinax
Connectors.
The hardware architecture provides enough resources (i.e. processing capability and memory)
to guarantee, that all specified interface functions are available concurrently and to full
performance specifications.
A powerful PCI-Express Controller and Memory Arbiter are implemented in a Field
Programmable Gate Array (FPGA). This FPGA supports both, the interface to the application
and driver software tasks running on the host computer and assists the communication for data
transfer.
This feature expands the capability of the ACE1553 module to that of a high level instrument.
To fulfil the real-time requirements of a typical avionic type databus system, a high performance
32bit RISC processor (BIP) is implemented for each Bus Interface Unit (BIU) / each MIL-STD-
1553A/B stream.
A free-wheeling IRIG-B Time code Encoder/Decoder is implemented on the ACE1553 to satisfy
the requirements of “multi-channel time tag synchronization” on the system level. The IRIG-B
compatible amplitude modulated sinewave output allows the synchronization of any external
module implementing IRIG-B time stamping.
The module can be installed in standard cPCIe (3U) peripheral/hybrid slots and PXIe
peripheral/hybrid slots. If installed in a PXIe slot, 8 PXI Trigger I/O and a PXI System Reference
Clock (10MHz) based time tag mode are supported.

ACE1553-3U-4 Hardware Manual
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How This Manual is Organized1.2
Section 1 - INTRODUCTION - contains an overview of this manual.
Section 2 - INSTALLATION - describes the steps required to install the ACE1553 device,
and connect the device to other external interfaces including the MIL-STD-1553
Bus, IRIG-B, and triggers.
Section 3 - STRUCTURE OF THE ACE1553-3U-4 - describes the physical hardware
interfaces on the ACE1553 using a block diagram and a description of each main
component
Section 4 - TECHNICAL DATA - describes the technical specification of the ACE1553.
Applicable Documents1.3
The following documents shall be considered to be a part of this document to the extent that
they are referenced herein. In the event of conflict between the documents referenced and the
contents of this document, the contents of this document shall have precedence.
1.3.1 Industry Documents
[1] PXI Express Hardware Specification –Rev. 1.0 –Aug. 22, 2005
[2] PXI Hardware Specification –Rev. 2.2 –September 22, 2004
[3] MIL-STD-1553B, Department of Defence Interface Standard for Digital Time
Division Command/Response Multiplex Data Bus, Notice 1-4, January 1996
1.3.2 Product Specific AIM Documents
[4] AIM - Reference Manual ACE1553 Application Interface Library Detailed description of
the programming interface.

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2 INSTALLATION
Preparation and Precaution for Installation2.1
The ACE1553 features full PCIe Plug and Play capability; therefore, there are no jumpers or
switches on the board that require modification by the user in order to interface to the PCIe bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap available,
then touch a metal plate on your system to ground yourself and discharge any static electricity
during the installation work.
Installation Instructions
2.2
The following instructions describe how to install the ACE1553 module in your system. Please
follow the instructions carefully, to avoid any damage on the device.
To Install the ACE1553
1. Shutdown your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing modules with
power applied may result in damage to module devices).
3. Find a free peripheral/hybrid expansion slot in your system.
4. Remove the slot bracket from the slot you have chosen and put it aside.
5. Make sure the injector/ejector handle is in its downward position.
6. Align the ACE1553 with the card guides on the top and bottom of the
peripheral/hybrid expansion slot. Do not raise the injector/ejector handle as you
insert.
7. Hold the handle as you slowly slide the module into the chassis until the handle
catches on the injector/ejector rail.
8. Raise the injector/ejector handle until the module firmly seats into the backplane
receptacle connectors. The front panel of the ACE1553 should be even with the
front of the chassis.
9. Secure the card to the PXIe/cPCIe chassis tightening the two bracket-retaining
screws on the top and bottom of the front panel
10. Connect the system to the power source. Turn on the power of your system.

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Connecting to other Devices2.3
The external interface of the ACE1553 consists of up to 4 dual redundant channels compliant
with MIL-STD-1553A/B, Trigger In/Out signals for Bus Monitor, Bus Controller and Remote
Terminals, as well as the IRIG IN/OUT interface for multi-channel time tag synchronization.
Figure 2.1: Front Panel View
The ACE1553-3U-4 interface comprises two female DSUB15 connectors, which providing the
MILbus signals, the Trigger IN/OUT, the GPIOs and the IRIG IN/OUT signals.

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2.3.1 MIL-STD-1553-A/B Dual Channel Interface Connector
On the ACE1553-3U-4 card all MILbus signals are provided on two female HD-DSUB15
connectors at the front panel.
Figure 2.2: Pinout of the 15 Pin HD-DSUB connector
The pin assignment of the MILbus connectors is shown in the table here below:
DUSB-15 Connector (Ch1+2)
DUSB-15 Connector (Ch3+4)
Pin
Signal Description
Pin
Signal Description
1
MILBus Channel 1 A (true)
1
MILBus Channel 3 A (true)
2
MILBus# Channel 1 A (compl)
2
MILBus# Channel 3 A (compl)
3
IRIG-OUT
3
DISCRETE GPIO (1)
4
MILBus Channel 1 B (true)
4
MILBus Channel 3 B (true)
5
MILBus# Channel 1 B (compl)
5
MILBus# Channel 3 B (compl)
6
IRIG-IN
6
DISCRETE GPIO (2)
7
Trigger CH1 IN
7
Trigger CH3 IN
8
Trigger CH1 OUT
8
Trigger CH3 OUT
9
Trigger CH2 IN
9
Trigger CH4 IN
10
Trigger CH2 OUT
Trigger CH4 OUT
11
MILBus Channel 2 A (true)
MILBus Channel 4 A (true)
12
MILBus# Channel 2 A (compl)
MILBus# Channel 4 A (compl)
13
GND
GND
14
MILBus Channel 2 B (true)
MILBus Channel 4 B (true)
15
MILBus# Channel 2 B (compl)
MILBus# Channel 4 B (compl)
Table 2.1: Pin Description of the two HD-DSUB15 front-panel connectors
2.3.2 General Purpose I/O Connections
Two General Purpose I/O's (GPIO1 –GPIO2) are provided on the DUSB-15 Connector (Ch3+4)
with Avionic Level inputs and outputs.
The GPIO’s can be used as simple discrete inputs or outputs, for example to generate strobes
(i.e. to another AIM board) or to sample a digital input signal generated by an external system
(or AIM board).
Optional a Breakout cable can be ordered with four two-meter stub cables terminated with
trumpeter PL-75 plugs for the MILbus and with a stub cable which provides the IRIG-Signal, the
Trigger-Lines and the GPIO-Signals

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Front Panel LEDs2.4
Two sub miniature LEDs for each channel, located at the front panel, indicate the module
status. The LEDs are located in two quadruple LED-Arrays on the physical interface
daughterboard.
Figure 2.3: Status LED view
LED Name
Colour
Description
FAIL (CH1)
Red
LED illuminates if an Error during the MILbus Channel1 self-test
occurs.
BUSY (CH1)
Green
LED illuminates permanently if the MILbus channel 1 is connected.
LED flashes if any MILbus Activity is detected by the
Encoder/Decoder of the MILbus channel 1.
FAIL (CH2)
Red
LED illuminates if an Error during the MILbus Channel2 self-test
occurs.
BUSY (CH2)
Green
LED illuminates permanently if the MILbus channel 2 is connected.
LED flashes if any MILbus Activity is detected by the
Encoder/Decoder of the MILbus channel 2.
FAIL (CH3)
Red
LED illuminates if an Error during the MILbus Channel3 self-test
occurs.
BUSY (CH3)
Green
LED illuminates permanently if the MILbus channel 3 is connected.
LED flashes if any MILbus Activity is detected by the
Encoder/Decoder of the MILbus channel 3.
FAIL (CH4)
Red
LED illuminates if an Error during the MILbus Channel4 self-test
occurs.
BUSY (CH4)
Green
LED illuminates permanently if the MILbus channel 4 is connected.
LED flashes if any MILbus Activity is detected by the
Encoder/Decoder of the MILbus channel 4.
PCI Activity
Blue
LED flashes if there is local (on board PCIe/PCI bus) activity
Table 2.2: Front Panel LED description

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3 STRUCTURE OF THE ACE1553-3U-4
The structure of the ACE1553-3U-4 is shown in Figure 3.1. The ACE1553-3U-4 comprises the
following main sections:
PCI-Express bus and BIU-IO FPGA
Global RAM
BIU Processor Section
Physical I/O Interface with up to four Dual redundant MIL-STD-1553B Channels
IRIG- Time Code Proc. with free-wheeling function and Sine Wave Output
Boot-Up Flash
PXI Instrumentation Bus
Figure 3.1: Block Diagram of ACE1553-3U-4

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PCI-Express Interface and BIU-I/O FPGA3.1
The new common FPGA architecture of AIM’s PCI-Express family includes both the complete
PCI-Express bus logic and the BIU processor logic. This programmable device implements the
following features:
PCI Express 1.1 compliant bus interface
Global RAM interface and arbitration
Boot function
SPI controller for update programming
MIL-STD-1553 Encoder
MIL-STD-1553 Decoder
IRIG Encoder and decoder support
System & Maintenance Controller / RS232 Maintenance Interface
External Trigger Inputs and Outputs
User programmable GPI/Os
PXI Instrumentation Bus Capabilities
3.1.1 Global RAM Interface and Arbitration
The Global RAM Arbiter and the Global RAM interface port are implemented in the FPGA. The
Arbiter controls Global RAM access between the participants (BIU Processors, PCIe, and the
Timecode Processor) in a fair arbitration scheme
3.1.2 Boot Function
To provide maximum flexibility and upgradeability, the FPGA device and the processor are
booted automatically after power up.
3.1.3 Controller for SPI-Flash update programming
IP-Core SPI-Controller to program the on board SPI-Flash memory.
3.1.4 MIL-STD-1553 Encoder
The MIL-STD-1553 encoder comprises a Manchester Encoder with full error injection capability.
The encoder is used to generate faulty (or fault free) command and data words on the bus. This
encoder allows the user to insert protocol errors as required by the 'Remote Terminal
Production Test Plan'.
3.1.5 MIL-STD-1553 Decoder
The MIL-STD-1553 decoder comprises a Manchester Bi-phase decoding unit which samples
the incoming serial data stream. The decoder detects the synchronization pattern
(Command/Status and Data Sync.), converts 16 bit Manchester encoded serial data to parallel

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and receives the parity bit. The decoder indicates the sync. pattern and error information (parity
error, Manchester error, framing error) via dedicated bits in a readable error register.
3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP)
The IRIG-B time code will be received and decoded from the TCP. The decoded millisecond
time code received from TCP is expanded by a self-generated microsecond value and
organized to a 46Bit time tag value.
The IRIG-B time encoder generates the transmitted timecode sinusoidal signal. The IRIG start-
time can be set via software.
3.1.7 System & Maintenance Controller / RS232 Maintenance Interface
The System and Maintenance Controller is used for on board debugging and board
maintenance purposes in the factory.
3.1.8 External Trigger Inputs and Outputs
For Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM) triggering, separate
trigger input and trigger output are provided for each MILbus channel at the Front I/O connector.
The minimum trigger pulse length must be greater than 75 nanoseconds to be detected. The
trigger inputs are high active and their voltage level is of type TTL and is +5.0V tolerant.

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3.1.9 User programmable Discrete I/O (GPIO)
The ACE1553-3U-4 module provides 2 user programmable discrete I/O signals. Discrete input
signals are always active whereas the discrete output signals are per default inactive. An open
collector circuitry is used for the discrete output with approximately 4V provided by default. An
external voltage from 0 to 35V can be supplied externally for switching higher voltages.
Please Note:
The discrete outputs don’t provide a series resistor for over current protection. In case a discrete
input is used, make sure that the output-mode for that discrete is disabled, before connecting an
external voltage, otherwise a high short circuit current to GND can damage the output transistor.
Figure 3.2: GPI/O ACE-1553-3U-x circuitry
Be aware that a series resistor must be provided when a user voltage is used (Figure 3.3). This
serial resistor must limit the current through the open collector transistor to max. current (see
technical data chapter for details). Otherwise the open collector transistor can be damaged.
EMC aspects are covered by filter circuitry.
GND
Discrete IO-Pin Front Connector
ACE1553-3U-x Board
Pulldown
Resistor
Current
limiting
Resistor
(1 KΩ)
+5V
Current
limiting
Resistor
(10 KΩ)
Discrete output circuitry
Discrete input circuitry
GND
FPGA
Output
Pin
FPGA
Input
Pin

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Figure 3.3: GPIO Protection with external resistor
Global RAM3.2
The Global RAM is shared between both BIU processors (BIP) and the Host PCIe-Bus. The
arbitration is handled by the common FPGA. It has access to the common Global RAM via a 32
bit wide data port.
BIU Section3.3
Up to two Bus Interface Units (BIUs) are implemented on the ACE1553-3U module. Both BIUs
implement exactly the same functionality. Each BIU handle up to two MIL-STD-1553B channels
and provide the trigger signals for BC, RT and BM applications. The control logic is
implemented in the common FPGA device.
Discrete IO-Pin
Front Connector
Off-Board User Voltage
Customized
Discrete Output
Rserial
ACE1553-3U-x Board
GND
FPGA
Output
Pin

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Physical Bus Interface with four Dual Redundant MIL-STD-1553B Channels3.4
The Physical Bus Interface (PBI) is implemented as a daughter-board and is mounted on the
ACE1553 main board. The Physical Bus Interface (PBI) contains four dual redundant MIL-STD-
1553 channels, each channel comprises a dual-redundant transceiver, transmitter amplitude
control circuitry, a dual bus coupling transformer and the coupling relays with the MILbus
network emulation circuitry.
The MIL-STD-1553 dual trapezoidal transceivers allow for output amplitude control on primary
and secondary channel.
The MILbus coupling network of the PBI consists of sophisticated relay circuitry which offers
various coupling capabilities.
The following coupling modes (shown in Table 3.1) can be programmed via software:
Transformer coupled
Direct coupled
Transformer coupled with resistive network emulation
Isolated (Internal termination)
MILbus Coupling
Representation
MIL-BUS Isolated (Default)
No connection to the MILbus
MIL-BUS Transformer Coupled
SH
LG
/LG
/SH
IN
/IN
MIL-BUS Direct Coupled
SH
LG
/LG
/SH
IN
/IN
55R
55R
MIL-BUS Transformer Coupled with
Network Emulation
IN
/IN
SH
LG
/LG
/SH
93R
93R
92,8R 92,8R
Rin=Rout
=69,62R
Table 3.1: Different Coupling for MILbus channels