Aim ACE1553-3U-4 User manual

Hardware
Manual
V01.10 Rev. A
January 2016
ACE1553-3U-4
Quad Stream
MIL-STD-1553
PXI-Express / cPCI-Express
(3U) Modules

ACE1553-3U-4 Hardware Manual
i
ACE1553-3U-4
Quad Stream
MIL-STD-1553
PXI-Express / cPCI-Express
(3U) Modules
V01.10 Rev. A
January 2016
AIM No.
60-117E0-16-0110-A
Hardware
Manual

ACE1553-3U-4 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
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Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
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[e-mail]
AIM GmbH –Munich Sales Office
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AIM USA LLC
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[e-mail]
© AIM GmbH 2015
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by
implication in connection therewith. Specifications are subject to change without notice.

ACE1553-3U-4 Hardware Manual
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DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 Rev. A
10.06.2015
E. Carraro
First Released Version
V01.10 Rev. A
19.01.2016
E. Carraro
New layout, corrections on the discrete
section (CDR5898)

ACE1553-3U-4 Hardware Manual
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ACE1553-3U-4 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1INTRODUCTION .....................................................................................................1
General ...............................................................................................................11.1 How This Manual is Organized............................................................................21.2
Applicable Documents.........................................................................................21.3
1.3.1 Industry Documents ........................................................................................2
1.3.2 Product Specific AIM Documents....................................................................2
2INSTALLATION.......................................................................................................3
Preparation and Precaution for Installation..........................................................3
2.1
Installation Instructions........................................................................................32.2 Connecting to other Devices................................................................................42.3
2.3.1 MIL-STD-1553-A/B Dual Channel Interface Connector ...................................5
2.3.2 General Purpose I/O Connections...................................................................5
Front Panel LEDs................................................................................................62.4
3STRUCTURE OF THE ACE1553-3U-4....................................................................7
PCI-Express Interface and BIU-I/O FPGA ...........................................................83.1
3.1.1 Global RAM Interface and Arbitration..............................................................8
3.1.2 Boot Function..................................................................................................8
3.1.3 Controller for SPI-Flash update programming .................................................8
3.1.4 MIL-STD-1553 Encoder ..................................................................................8
3.1.5 MIL-STD-1553 Decoder ..................................................................................8
3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP)..............................9
3.1.7 System & Maintenance Controller / RS232 Maintenance Interface..................9
3.1.8 External Trigger Inputs and Outputs................................................................9
3.1.9 User programmable Discrete I/O (GPIO).......................................................10
Global RAM.......................................................................................................113.2
BIU Section .......................................................................................................113.3 Physical Bus Interface with four Dual Redundant MIL-STD-1553B Channels....123.4 IRIG- and Time Code Section............................................................................143.5
3.5.1 Time Code Encoder/Decoder........................................................................14
3.5.2 Time Tag Methods ........................................................................................14
General Purpose Discrete Inputs/Outputs (GPIO) .............................................153.6 PXIe / cPCIe - Connector Pin Assignment.........................................................153.7
4PXI-EXPRESS INSTRUMENTATION BUS ...........................................................17
About the PXIe Standard...................................................................................17
4.1
4.1.1 Backplane Trigger Lines................................................................................18
4.1.2 System Reference Clock (10MHz) ................................................................20
4.1.3 Star Trigger...................................................................................................21
5TECHNICAL DATA ...............................................................................................23
6NOTES ..................................................................................................................27
Acronyms ..........................................................................................................276.1

ACE1553-3U-4 Hardware Manual
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LIST OF TABLES
Table Title Page
Table 2.1: Pin Description of the two HD-DSUB15 front-panel connectors.............................5
Table 2.2: Front Panel LED description..................................................................................6
Table 3.1: Different Coupling for MILbus channels...............................................................12
Table 3.2: IRIG-B: Binary Coded Time Tag..........................................................................14
Table 3.3 PXIe XJ4 connector's pin-out................................................................................15
Table 3.4: PXIe XJ3 connector's pin-out...............................................................................15
LIST OF FIGURES
Figure Title Page
Figure 2.1: Front Panel View..................................................................................................4
Figure 2.2: Pinout of the 15 Pin HD-DSUB connector.............................................................5
Figure 2.3: Status LED view...................................................................................................6
Figure 3.1: Block Diagram of ACE1553-3U-4.........................................................................7
Figure 3.2: GPI/O ACE-1553-3U-x circuitry..........................................................................10
Figure 3.3: GPIO Protection with external resistor................................................................11
Figure 3.4: MILbus Amplitude vs. Vcontrol ...............................................................................13
Figure 4.1: PXI architecture..................................................................................................17
Figure 4.2: PXI/Front Panel-PBI Trigger Routing capabilities................................................19

ACE1553-3U-4 Hardware Manual
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1 INTRODUCTION
General1.1
This document comprises the Hardware User’s Manual for the ACE1553-3U-4 PXIe-Module.
The document covers the hardware installation, the board connections the technical data and a
general description of the hardware architecture. For programming information please refer to
the documents listed in the “Applicable Documents” section.
The ACE1553 modules are members of AIM's new family of advanced PXI-Express cards
compliant to PCI Express V1.1 communication standard. The PCI-Express Interface is 1-lane
wide and works with 2.5 Gbit/s in transmit and receive direction.
The ACE1553 modules are used to simulate, monitor and inject protocol errors of MIL-STD-
1553A/B based databus systems. The ACE1553-3U-4 offers an interface for up to four dual-
redundant MIL-STD-1553 bus channels. Furthermore the interface implements trigger IN/OUT
functions for Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM), as well as 2
user programmable Discrete I/O signals.
Additionally, a free-wheeling IRIG-B time code generator allows the user to synchronize to
either the onboard generated time code or the time code of an external board with a resolution
of 1us.
Transformer-, Direct-, Network Emulation- and Isolated Coupling- Modes are available at the
external interface connector. A standard breakout cable (2.0 m) is available for the ACE1553
card from HD-DSUB15 connector to four (two, if ACE1553-3U-1 module) PL-75 Twinax
Connectors.
The hardware architecture provides enough resources (i.e. processing capability and memory)
to guarantee, that all specified interface functions are available concurrently and to full
performance specifications.
A powerful PCI-Express Controller and Memory Arbiter are implemented in a Field
Programmable Gate Array (FPGA). This FPGA supports both, the interface to the application
and driver software tasks running on the host computer and assists the communication for data
transfer.
This feature expands the capability of the ACE1553 module to that of a high level instrument.
To fulfil the real-time requirements of a typical avionic type databus system, a high performance
32bit RISC processor (BIP) is implemented for each Bus Interface Unit (BIU) / each MIL-STD-
1553A/B stream.
A free-wheeling IRIG-B Time code Encoder/Decoder is implemented on the ACE1553 to satisfy
the requirements of “multi-channel time tag synchronization” on the system level. The IRIG-B
compatible amplitude modulated sinewave output allows the synchronization of any external
module implementing IRIG-B time stamping.
The module can be installed in standard cPCIe (3U) peripheral/hybrid slots and PXIe
peripheral/hybrid slots. If installed in a PXIe slot, 8 PXI Trigger I/O and a PXI System Reference
Clock (10MHz) based time tag mode are supported.

ACE1553-3U-4 Hardware Manual
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How This Manual is Organized1.2
Section 1 - INTRODUCTION - contains an overview of this manual.
Section 2 - INSTALLATION - describes the steps required to install the ACE1553 device,
and connect the device to other external interfaces including the MIL-STD-1553
Bus, IRIG-B, and triggers.
Section 3 - STRUCTURE OF THE ACE1553-3U-4 - describes the physical hardware
interfaces on the ACE1553 using a block diagram and a description of each main
component
Section 4 - TECHNICAL DATA - describes the technical specification of the ACE1553.
Applicable Documents1.3
The following documents shall be considered to be a part of this document to the extent that
they are referenced herein. In the event of conflict between the documents referenced and the
contents of this document, the contents of this document shall have precedence.
1.3.1 Industry Documents
[1] PXI Express Hardware Specification –Rev. 1.0 –Aug. 22, 2005
[2] PXI Hardware Specification –Rev. 2.2 –September 22, 2004
[3] MIL-STD-1553B, Department of Defence Interface Standard for Digital Time
Division Command/Response Multiplex Data Bus, Notice 1-4, January 1996
1.3.2 Product Specific AIM Documents
[4] AIM - Reference Manual ACE1553 Application Interface Library Detailed description of
the programming interface.