Maxim Integrated Teridian 78M6618 Instruction Manual

78M6618
Hardware Design Guidelines
APPLICATION NOTE
AN_6618_027 October 2010
Rev. 1.2 © 2010 Teridian Semiconductor Corporation 1
A Maxim Integrated Products Brand
1 Introduction
This application note provides hardware and system design guidelines for those incorporating the
78M6618 System on Chip in their products. These guidelines will help hardware engineers to reduce
design cycle times.
The following topics are discussed:
•Non-isolated Configuration
oSafety Precautions
o3.3 VDC Supply (V3P3) and System Connection
oLine Voltage Resistor Divider Selection
oShunt Selection and Connections
•Isolated Configuration
oCurrent Transformers
oOther Connections
oVoltage Transformers
•Calibration Considerations
•Basic Configuration
oReset Circuitry
oV2P5 Voltage Reference Pin
oV1 Pin
oIn Circuit Emulator (ICE) Pins
oConnecting 5 V Devices
oDriving External Loads
oConnecting I2C EEPROMs
oConnecting 3-Wire EEPROMs
oUART0 (TX/RX)
oUART1 Interface
oPower Supply Topologies
•Timing Reference
oOscillator Connections and Components Selection
oPCB Layout Recommendations
oOther Considerations

78M6618 Hardware Design Guidelines AN_6618_027
2 Rev 1.2
2 Non-isolated Configuration
When using a resistive shunt current sensor, the measurement IC and its power domain are not isolated
from the AC mains. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6618 must be directly
connected to AC-Neutral for precision energy measurement. Isolation components, if required, are added
in between the measurement IC and the rest of the system.
The V3P3 connection to AC-Neutral can be eliminated when using current transformers (CT) as the
current sensing elements. Refer to the section on Isolated Connections for designing with CTs.
2.1 Safety Precautions
With V3P3 directly connected to NEUTRAL, the 78M6618’s Ground signal is -3.3 V below earth ground.
Therefore, any external test equipment attached to the 78M6618 will be subject to this -3.3 V ground
reference disparity.
External test equipment must
be floated from earth ground to avoid equipment damage due to
this ground reference disparity.
An additional safety issue may arise due to mis-wiring of the AC outlets. If the LINE and NEUTRAL wire
connections at the AC plug are reversed between the 78M6618 and the external test equipment, the
78M6618 and external test equipment will see a 120/240 VAC voltage difference rather than -3.3 V. This
scenario can occur when the 78M6618 and external test equipment are powered from different wall
outlets or power strips, one of which is mis-wired. With proper earth grounding, the external equipment is
always referenced to earth ground via their enclosures.
Any systems communication interface (UART, SPI, I2C) between the 78M6618 and external
circuitry must be isolated to accommodate the -3.3 V disparity in their GND pins (or in the event
of a LINE reversal).
Refer to the 78M6618 Safety Precautions document.

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 3
2.2 3.3 VDC Supply (V3P3) and System Connection
The 78M6618 requires a single 3.3 VDC supply. The 3.3 VDC (V3P3) also represents the reference
potential for the 78M6618. The basic connections for a shunt-based system are represented in Figure 1.
Shunt x8
NEUTRAL
LINE
VA
VB
750
1M
1M
1000pF
IA-IH
1000pF
x8
Unused
Inputs LOAD
x8
750 x8
78M6618
1M 1M
EARTH
V3P3
750 1000pF
0.1uF
0.1uF
x8
0.1uF
Figure 1: Basic Connection Diagram on Shunt-Based Systems
The analog inputs to the 78M6618 are used as follows:
•The VA input is used to measure the line voltage.
•The IA-IH inputs are used to measure the load currents. Terminate unused current inputs to V3P3.
•The VB input is used to flag a Line/Neutral polarity reversal. If this feature is not desired, the VB input
can be tied directly to the VA input or directly to V3P3.
Notes:
•The values used for the anti-aliasing filters are 750 Ω and 0.1 µF. The filters have in this case a cutoff
frequency of about 2.1 KHz. Since the sample rate of the ADC converter may vary depending on the
different firmware configurations, a different value may be required. To tune the filter, it is
recommended to keep the 750 Ω resistor unchanged and modify the value of the capacitor.
Do not tie the ground of the 78M6618 directly to earth ground. See the Safety Precautions
section.

78M6618 Hardware Design Guidelines AN_6618_027
4 Rev 1.2
Effective 3.3 VDC bypassing incorporates the combination of three different capacitor values. A 1000 pF
in parallel with a 0.1 µF ceramic capacitor must be placed as close as possible to the 78M6618 V3P3A
pin. Place the 1000 pF capacitor closest to the V3P3A pin of the 78M6618. An additional 22 µF bulk
capacitor is placed in the vicinity of the V3P3SYS pin to provide decoupling for the external DIO circuitry.
Connect the VBAT pin to the V3P3SYS pin, directly to V3P3. These three capacitor values provide
decoupling over a wide frequency spectrum. Do not connect V3P3D to V3P3. V3P3D only requires a
0.1 µF capacitor to ground.
GNDA
V3P3SYS
VBAT
V3P3A
GNDD
1000pF 0.1μF 22μF
V3P3
Place Capacitors
Close to V3P3A
V3P3D 0.1μF
Figure 2: Power Supply Decoupling

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 5
2.3 Line Voltage Resistor Divider Selection
The input line voltage must be scaled to match the 78M6618’s ADC input signal range of 176.78 mVrms.
In the example of Figure 3, the line voltage is scaled as follows:
The use of two 1 MΩ resistors instead of a single 2 MΩ resistor is required to meet the maximum voltage
rating of the resistor package and to provided adequate breakdown and arcing clearance. 1206 series
surface mount resistors are recommended.
An important aspect to consider is the accuracy of the resistors in the voltage ladder. Another
consideration that can affect the overall measurement accuracy is the resistor temperature coefficient
(TCR in Ωppm/°C).
VA
VB
1M
1M
750
LINE
V3P3 1000pF
0.1μF
Figure 3: Input Voltage Divider and Filtering
Initial component tolerance can easily be compensated for during calibration. Depending on the system
accuracy requirements, the incremental cost of a higher precision resistor (i. e. 0.1% versus 5%) may
result in a lower production line calibration cost (shorter calibration time). If 0.1% tolerance resistors are
used, a calibration would only need to be done on one system and then the voltage calibration coefficient
obtained can be used for all others in production thus saving time through the production line. The
variation from board to board would be within the tolerance of the resistors used in the divider.
Additionally, the higher precision resistor will have a smaller temperature coefficient. This eliminates the
source of error that can arise from changes in resistance from self heating as the line voltage changes.
TCR of 50 ppm/°C or lower (preferably 25 ppm/°C) is recommended.

78M6618 Hardware Design Guidelines AN_6618_027
6 Rev 1.2
2.4 Shunt Selection and Connections
The 78M6618 sensor input range is 12.5 μV (8.84 μVrms) to +250 mV (176.78 mVrms). The value of the
shunt to be used is usually a tradeoff between a higher shunt value to utilize the full analog sensor input
range of the IC and the power loss in the shunt.
Use the maximum rated load power when calculating the value of the shunt resistor for best utilization of
the ADC’s input range (+/-250 mVpp). Also, use the lowest operating LINE voltage (for example 90 VAC
for 120 VAC rated systems) for this calculation. The maximum input current is then:
For example, if the maximum input power is 1.0 KW, the maximum input current is 11.12 A rms.
The resultant peak-to-peak current is calculated to be:
In the example above, the peak to peak value is 31.4 A.
A 15 mΩshunt value fully utilizes the ADC input range. This shunt value produces a dissipated power of
1.85 W at maximum load current. In order to ensure more ADC signal margin due to transients and to
lower the power dissipation in the shunt resistor, a lower value shunt of 8 mΩis recommended. In this
case, the shunt’s power dissipation reduces to 0.99 W at the maximum load current.
The next steps involved in the shunt resistor selection include considerations for power dissipation, initial
tolerance and the device’s temperature coefficient. In the case selected above, the power dissipated in
the shunt at maximum load current is 0.99 W. A 2 W rated device package is recommended for good
long-term reliability. The initial tolerance can be compensated during calibration. However, the
temperature coefficient plays a role in the overall accuracy and cannot be easily compensated. For
example, a temperature coefficient of 100 ppm/°C causes a resistance variation of 1% over the 100 °C
operating temperature environment.
IA-IH
V3P3
SHUNT
750
0.1μF1000pF
Figure 4: Shunt Connections and Filtering

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 7
2.4.1 Single-ended Shunt Connections
Multi-shunt measurement systems typically require use of differential input circuits. These differential
input circuits add cost due to added components. The 78M6618 Evaluation Board presents a lower cost
multi-shunt measurement system alternative. Additionally, the proposed circuit design results in a very
compact printed board layout for a high accuracy energy measurement system.
The key for single ended measurements is a noise free reference point. Attaching multiple shunts to a
common reference point presents mechanical challenges due to physical size and placement. The linear
spacing required (side by side placement) for multiple shunts compromises the “noise free” reference
point. The resistance along a linear surface from one shunt to another is not insignificant relative to the
low ohms value of the current sensing shunt.
Measurement errors occur in adjacent shunts as the collective currents produce voltages in the
interconnecting “reference point” structure. The small resistance present in the interconnecting structure
between adjacent shunts creates this voltage offset when high load currents are present. The voltage
offset results in a measurement error for each shunt. Reducing the resistance of the interconnecting
structure is critical to achieving high accuracy in a single ended multi-shunt measurement system.
The 78M6618 Evaluation Board minimizes the interconnecting structure’s resistance and minimizes
adjacent shunt influences (error voltage due to load current) by employing a radial disk topology. The
78M6618 reference point utilizes a copper disk. The copper disk provides a much lower resistance
structure compared to 1 oz. copper plating. The thickness of the copper disk is equal to the printed circuit
board thickness for ease of manufacture. Uniform distance to the reference “center” point is achieved by
placing the shunts radially around the copper disk. Placing the shunts on both sides of the board
minimizes the diameter of the copper disk reducing the overall reference point resistance.
Figure 5: 78M6618 Evaluation Board Copper Disk with Radial Shunt Placement
The 78M6618 Evaluation Board is designed for a typical 15A household service. Ideally, a large current
load at one outlet should not affect the remaining outlets. Due to the finite resistance of the copper disk,
a measurement error is unavoidable. The copper disk’s resistance is calculated as follows:
Copper resistivity at 25C = 1.7 x 10-6 ohm-cm
Resistance = Resistivity*Length/Area*(1 + (Temp_Co*(Temp - 25))
Assuming a straight conduction path from the shunt to the copper disk center point:
Thickness = 62 mils, same as printed circuit board thickness
Width = 200 mils, width of shunt pad
Length = 100 mils, distance of shunt to center point
The linear resistance from the shunt to the copper disk center point = 5 µohm
Copper
Disk

78M6618 Hardware Design Guidelines AN_6618_027
8 Rev 1.2
This represents a 0.1% error when using a 6 mohm shunt.
Current does not flow in a single straight line between two points in a conductor. Due to internal
resistance in the conductor, the current spreads out through the medium. Figure 6 shows how current
from one outlet produces a distributive voltage across the copper disk.
Figure 6: Single Load Voltage Distribution in a Disk
Observe how the presence of a current at one location (assume position 0 degrees), creates a small
voltage at positions 45, 90, 135, 180, 225, 270 and 315 degrees (the other shunt locations).The shunts
most affected by a single large load (at position 0 degs) are the two adjacent shunts on the opposite side
of the board (at positions 45 and 315 degs). The above voltage distribution assumes no current flow in
the other seven outlets.
When current flows in two or more outlets, the current distribution through the copper disk depends on the
difference between the adjacent currents. A small outlet current flowing next to a large outlet current will
endure a non-linear measurement error due to the larger load’s current distribution implied in Figure 6.
The smaller current’s path to the center point is no longer a straight line but a longer curved path. The
longer curved path effectively reflects itself as additional resistance in the path from the shunt to the
center point.
The above condition exhibits itself when the relative current magnitudes approach 100:1. For example, a
10 A load at one outlet affects the accuracy of an adjacent 100 ma load. The 100 ma load will be
measured as 105 ma. Similarly, a 1 A small load with a 10 A large load will be measured as 1.002 ma.
2.4.2 Differential Shunt Connections
Alternatively, the system designer can preserve the use of differential measurements on the 78M6618 by
using a differential op-amp between the current sense input of the 78M6618 and the shunt resistor.
Contact Teridian support engineers for more information on using op-amps for differential input
measurement of shunts.
Outlet Current
Exit Point
Edge of Disk
Source Current
Inlet Point
Disk Center Point

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 9
3 Isolated Configuration
Alternatively, the 78M6618 can sense the load current using a current transformer (CT) for an isolated
configuration. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6618 is not directly tied to
AC mains. The analog inputs to the 78M6618 are used as follows:
•The VA and VB inputs are used to measure the line voltage differentially
•The IA-IH inputs are used to measure the load currents.
•Terminate unused current inputs to V3P3 as shown in Figure 4.
3.1 Current Transformers
The selection of a current transformer with respect for the desired measurement accuracy includes
factors such as line frequency, measured current range and the CT’s turns ratio. Also, subjecting a
current transformer to load currents above the manufacturer’s rated current specification may saturate the
CT and cause winding failures due to excessive temperature rise. On the other hand, a current
transformer that is rated much higher than the target load current might be restrictively too large and
expensive for its purpose.
Figure 7: Current Transformer (CT) Basic Connections
Usually, current transformers have turns ratios ranging from 10:1 to 2500:1. The higher the turns ratio
(TurnRatio = Nsecondary/Nprimary), the higher the resolution of the current measurement. A too high
turns ratio increases distributed capacitance and leakage inductance. These characteristics may
decrease the CT’s accuracy and capability to operate at higher frequencies. However, if the number of
turns is too low, the output signal may distort or “droop” (for positively sloped unipolar input signals).
Such distortion may cause measurement inaccuracies.We recommend a minimum turns ratio of 1000:1.
The next step towards selecting a current transformer is the calculation of the burden resistor’s value
(RBurden). The 78M6618 signal input range is 176.78 mVrms (250 mVpk).Therefore, the CT’s
secondary output voltage (Vout) must operate within this range. Assuming the maximum load current is
20 Arms (28.284A pk), a 1000:1 ratio current transformer will produce a secondary current of 20 mA rms
(28.284 mA pk). Per Figure 7, the burden resistor’s value is calculated as follows:
Using the values in the above example, the value of the burden resistor is:
A standard value 8.2 Ωresistor is recommended.

78M6618 Hardware Design Guidelines AN_6618_027
10 Rev 1.2
Figure 8 shows a basic connection diagram of a CT-based system.
Figure 8: Basic Connection Diagram of a CT-Based System
The use of a CT allows for the 78M6618’s V3P3 to be isolated from the plant NEUTRAL wiring. This
topology eliminates the safety issues stated earlier regarding shunt-based current sensing. Figure
shows a 2 MΩ isolation from the LINE voltage via the voltage divider network. In this topology, the line
voltage is a pseudo-differential measurement of VB-VA.
The V3P3 reference point critical to multi-shunt measurement performance is not an issue with CTs. The
output currents generated by the CT’s secondary winding is small enough that the sheet resistance of the
1 oz. copper plating does not present measurement errors from adjacent CTs. Shield the CTs secondary
pins, burden resistor and filter components with top and bottom printed circuit board layer V3P3 plane
surfaces. Insert multiple V3P3 vias to interconnect the top and bottom V3P3 structures for a low
impedance shield. Refer to the 78M6618 Printed Circuit Board Layout Guidelines application note for
additional layout design recommendations.
See Using Current Transformers with the 78M661x for additional information.
3.2 Other Connections
The same power supply decoupling circuit from Section 2.2 can be used for an isolated configuration.
The 78M6618 supply and ground connections, however, can be shared with other (isolated) components
in the system when V3P3 is not tied to AC Neutral.
Line voltage sensor recommendations for a non-isolated sensor configuration (resistor divider) can also
be used in an isolated configuration due to the high impedance connections between high voltage AC and
the 78M6618. Alternatively, a voltage transformer (VT) can be used for fully isolated voltage sensing.
NEUTRAL
LINE
VA
VB
750
1M
1M
IA-IH
Unused
Current
Inputs
LOAD
x8
750
78M6618
1M
1M
V3P3
1000pF
Rburden
x8 750 x8
1000pF
x8
0.1μF
x8
0.1μF
1000pF

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 11
3.3 Voltage Transformers
The pseudo-differential voltage measurement circuit of VB-VA shown in Figure 6 can be replaced with a
voltage transformer (VT). The VT replaces the two 2 MΩresistor divider networks and requires use of
only V. Use of a CT with a VT provides complete galvanic isolation from the plant wiring. A good quality
VT provides accurate linear measurements from 100VAC to 240VAC.
The basic connection of a VT to the 78M6612 is similar to Figure 5. The VT’s secondary output voltage
range in conjunction with the manufacturer’s recommended burden resistor value must meet the
78M6612’s signal input range of ±176.78 mVrms (±250 mVpk). Higher output VT secondary voltages can
be accommodated using a resistor divider between the VT the 78M6612.
Use only good quality VTs which introduce minimal phase shift between the primary to secondary
winding. The CT phase calibration routine can be used to compensate for any VT phase delay.
Figure 7 shows a basic connection diagram of a CT and VT based system.
NEUTRAL
LINE
VA
VB
IA
IB
LOAD
750
78M6612
V3P3
0.1µF
RBurden
750
V3P3A
750
0.1µF
0.1µF
1000pF
1000pF
RBurden
750
0.1µF 1000pF
CT
VT
Figure 7: Basic Connection Diagram of a CT and VT Based System

78M6618 Hardware Design Guidelines AN_6618_027
12 Rev 1.2
4 Calibration Considerations
All power measurement ICs must employ in-system calibration to achieve higher accuracy. In-system
calibration compensates for the PCB trace lengths, LINE input voltage divider resistor network, current
sensor tolerances and 78M6618 IC tolerances. Using tighter tolerance components can help reduce or
even eliminate in-system calibration depending on the required measurement accuracy.
As an example, the following table shows different levels of accuracies that can be achieved with different
levels of calibration. The Current Only Calibration compensates for only the current sensing resistor
tolerance and utilizes 0.1% tolerance resistors for the voltage sensor. The Full Calibration compensates
for both the voltage divider plus the current sensor tolerances.
If the system does not require a high level of accuracy relative to the initial tolerance of the voltage divider
and current sensor components, predetermined coefficients can also be hard coded into the firmware to
eliminate production line calibration and maximize cost savings.
Calibration Type Time Accuracy
Full Calibration per outlet < 15s < 0.5%
Current Only Calibration per outlet
1
< 7.5s < 1%
No Calibration (fixed coeff.)
1 2
0 < 2.5
Notes:
1. Use 0.1% tolerance resistors voltage divider.
2. Use 1% tolerance shunt resistor or burden resistor when using a current transformer.
Refer to the 78M661x Calibration Procedure for additional information.

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 13
5 Basic Configuration
The section describes the remaining hardware interfaces found on the 78M6618.
5.1 Reset Circuitry
The 78M6618 employs an active high Reset input pin. Figure shows the external circuit configuration
using a pushbutton switch to generate the reset signal. If an external reset is not required, connect the
Reset pin to GND (GNDD). An external reset is recommended only during the development phase of a
project. It is recommended that the RESET pin be grounded for the production version of the PCB.
GNDD
V3P3D
RESET
1nF
10KΩ
1KΩ
Figure 10: Reset Circuitry
GNDD
RESET
Figure 11: Connection for Unused Reset Pin
5.2 V2P5 Voltage Reference Pin
The V2P5 pin is connected to an internal 2.5 VDC reference voltage. Do not attach external circuitry to
this pin. This pin must be left unconnected.

78M6618 Hardware Design Guidelines AN_6618_027
14 Rev 1.2
V3P3
V3P3 -
400mV
V3P3 - 10mV
VBIAS
0V
Battery or
reset
mode
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
5.3 V1 Pin
The V1 pin is connected to an internal power-fail comparator. The V1 input voltage is compared to an
internal reference voltage of 1.6 V (VBIAS). If the V1 voltage is above VBIAS, the comparator output is
high (1) signaling normal operation. If the V1 voltage is below VBIAS, the comparator output is low (0)
signaling battery mode operation (via an external battery attached to the VBAT pin). Connect the voltage
divider shown in Figure 6 to the V1 pin to enable normal (WDT enabled) 78M6618 operation. The
watchdog may be disabled for debugging by raising the V1 pin above 2.9 V.
R3 is used to provide hysteresis to the comparator.
The input pin V1 sinks 1 µA when V1< VBIAS and 0 µA when V1 ≥ VBIAS.
Therefore the thresholds are:
(High to Low transition, VBIAS = 1.6 VDC)
(Low to High transition, VBIAS = 1.6 VDC)
C1 provides additional filtering to the V1 input to prevent spurious commutations of the V1 comparator.
Figure 6: Voltage Divider

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 15
5.4 In Circuit Emulator (ICE) Pins
The 78M6618 evaluation boards employ a reduced component ICE interface. This circuit design is
sufficient when short ICE cables (less than 12 inches) are used or large RF fields are not present. If
either case is not true, the following recommendations are to be utilized.
If the ICE pins are used to drive LCD segments, attach 22 pF capacitors from the ICE signals to GND for
EMI protection.If the trace length of the ICE signals exceeds 2 inches, add 22 pF capacitors across the
ICE signals to GND for EMI protection. If the external ICE cables exceed 12 inches, insert the series
resistors to control signal reflections.
Connect the ICE_EN pin to GND on production boards using pre-programmed 78M6618 devices.
Otherwise, provide a strong pull-down resistor (recommend 330 Ωvalue) along with a filter capacitor of
1000 pF on ICE_EN to allow in-circuit programming.
Figure 7: ICE Pin Used to Drive LCD Segments
5.5 Connecting 5 V Devices
All digital input pins (DIO pins) of the 78M6618 are 5 V compatible allowing connection to external 5 V
devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected
to external 5 V devices.
E_RST
E_RXTX
E_TCLK
62
Ω
62
Ω
62
Ω
22pF
22pF
22pF
LCD Segments
(optional)
ICE_E
E_RST
78M6618
E_RXTX
E_TCLK
62
Ω
62
Ω
62
Ω
22pF
22pF
22pF
LCD Segments
(optional)
ICE_E
V3P3

78M6618 Hardware Design Guidelines AN_6618_027
16 Rev 1.2
5.6 Driving External Loads
Connect external loads to the digital outputs (DIO pins) as shown in Figure 8.
V3P3
DGND
V3P3
DGND
NOT RECOMMENDED RECOMMENDED
Figure 8: Connecting an External Load to a Digital Output
5.7 Connecting I2C EEPROMs
Connect I2C EEPROMs or other I2C compatible devices to DIO pins DIO4 and DIO5 as shown in
Figure 15. Add pull-up resistors of roughly 10 kΩto V3P3 for both the SCL and SDA signals. The I/O
RAM register DIO_EEX must be set to 01 to convert the DIO pins DIO4 and DIO5 to SCL and SDA I2C
operational mode.
.
Figure 9: I2C EEPROM Connection
DIO4
DIO5
78M6618
EEPROM
SCL
SDA
V3P3
10 kΩ
10 kΩ
DIO4
DIO5
EEPROM
SCL
SDA

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 17
5.8 Connecting 3-Wire EEPROMs
Connect µWire EEPROMs and other compatible devices to DIO pins DIO4 and DIO5 as shown in Figure
10. Connect DIO5 to both the DI and DO pins of the three-wire device. Connect the CS pin to a vacant
78M6618 DIO pin. Add a pull-up resistor of roughly 10 kΩto V3P3 to the DI/DO signals. Add a pull-down
resistor to the CS pin to prevent that the 3-wire device from being enabled on power-up before the
78M6618 can establish a stable signal for CS. The I/O RAM register DIO_EEX must be set to 10 in order
to convert the DIO pins DIO4 and DIO5 to µWire operational mode pins.
Figure 10: 3-Wire EEPROM Connection
5.9 UART0 (TX/RX)
Attach a 10 kΩpull-down resistor to the RX input pin. Additionally, include a 100 pF ceramic capacitor for
EMI protection as shown in Figure 11.
Figure 11: Connections for the RX Pin
5.10 UART1 Interface
The TX1 and RX1 (UART1) pins can be used as a regular serial UART interface, e.g. by connecting a
RS-232 transceiver.
Alternatively, they can directly interface to optical components, e.g. an infrared diode and phototransistor
implementing a FLAG interface. Contact Teridian applications support for more information.
DIO4
DIO5
EEPROM
SCLK
DI
10k
Ω
CS
DIOn
DO
10k
Ω
DIO4
DIO5
78M6618
EEPROM
SCLK
DI
V3P3
10k
Ω
CS
DIOn
DO
10k
Ω
TX
RX
10k
Ω
100pF
RX
TX
TX
RX
78M6618
10k
Ω
100pF
RX
TX

78M6618 Hardware Design Guidelines AN_6618_027
18 Rev 1.2
5.11 Power Supply Topologies
Several power supply topologies are presented for consideration as a dedicated source of V3P3 power in
non-isolated configurations.
5.11.1 Capacitive
Figure 12: Connections for the RX Pin
5.11.2 Transformer
Figure 13: No High-Voltage Components for Higher-Power Applications
5.11.3 Half-Wave Rectification with Switch-Mode Power Supply or Regulator
Figure 14: High Efficiency for Higher-Power Applications
NEUTRAL
LIVE
V3P3
GND
78M6618
VREG

AN_6618_027 78M6618 Hardware Design Guidelines
Rev. 1.2 19
6 Timing Reference
This section is both a design and troubleshooting guide for using the low-power crystal oscillator interface
on the 78M6618.
The 78M6618 typically uses a crystal oscillator as the clock source. Another option is to use an external
canned oscillator. The main advantages of a crystal oscillator are frequency accuracy, stability, low cost,
high reliability, and low power consumption.
To avoid common problems with crystal oscillators and to achieve high reliability, it is important to pay
attention to the components and their values, and the layout. This section shows how these elements
affect such factors as stability, temperature variation, start-up time, and noise immunity. It also contains
suggestions for solving problems in these areas.
6.1 Oscillator Connections and Components Selection
Figure 15 shows the recommended connection of the crystal oscillator.
XIN
XOUT
C1
C2
32.768 kHz
Y1
Figure 15: 78M6618 Crystal Oscillator Connection
Typical values for C1 and C2 are 33 pF and 9 pF respectively for a crystal load capacitance value of
12.5 pF.
The crystal output (XOUT) driver strength is internally limited to reduce the power dissipation.

78M6618 Hardware Design Guidelines AN_6618_027
20 Rev 1.2
6.2 PCB Layout Recommendations
6.2.1 Power Supply Noise and Electromagnetic Noise
Supply noise and electromagnetic noise are common causes of crystal oscillator failures. The oscillator
gain, and the slow rise and fall times (the signal is near sinusoidal), are typical characteristics of a
low-power and low-frequency oscillator. Because of these characteristics, the 32-kHz oscillator is
sensitive to power supply noise and to electromagnetic coupling.
Do not locate power magnetic components near the crystal oscillator components. Select a PCB layout
topology that places the crystal components on the opposite PCB side from the power magnetic
components and resulting magnetic fields.
6.2.2 Component Placement
To minimize noise sensitivity to spurious coupling or parasitic antenna phenomena on the PCB, the
connections of the crystal to oscillator input and output and to other components must be as
short as possible. The best practice is to place the crystal and phasing capacitors as close as possible to
the 78M6618. This helps to minimize the length of the connections.
The currents flowing through the two load capacitors (C1 and C2) are in opposition. The best practice is
to connect the two capacitors before connecting to the ground reference. At that time, the current back to
the ground is significantly reduced. The connections must be as short as possible and of identical
lengths. Avoid long connections from these capacitors that make a large loop on the PCB, which
behaves like an antenna and can collect surrounding high-frequency radiation.
6.2.3 Layout
The reference ground of the oscillator must be as quiet as possible; otherwise, high-frequency noise is
transmitted directly to the oscillator input and output, resulting in degradation of the oscillator
performance.
To prevent cross-coupling to fast signals with high-level harmonic content, do not route signal traces
through the crystal area. Both oscillator pin connections are critical.
Vias in the oscillator circuit should only be used for connections to the ground plane. Do not share
ground connections; instead, make a separate connection to ground for each component that requires
grounding. If possible, place multiple vias in parallel for each connection to the ground plane.
The use of high-quality components in the oscillator circuit is equally important to achieve correct and
reliable operation. Capacitors should be high-quality capacitors with very low ESR, designed for use in
high-frequency applications (i.e., NP0 and COG).
Figure 16, Figure 17, and Figure 18 show layout examples for the crystal oscillator.Figure 16 and Figure
17 show the placement and layout of the crystal oscillator components on the opposite side of the PCB
from the 78M6618. The 32.768 kHz crystal and its two 27 pF capacitors are placed on the GND layer.
This allows the crystal and the two capacitors to be surrounded with a ground shield. Place the XIN and
XOUT vias as close as possible to the 78M6618 pins. Shield the XIN and XOUT signal vias with a
Ground plane flood sectioned out of the V3P3 layer.