Microchip Technology dsPIC33F Family User manual

© 2006 Microchip Technology Inc. DS70183A-page 16-1
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Section 16. Analog-to-Digital Converter (ADC)
HIGHLIGHTS
This section of the manual contains the following major topics:
16.1 Introduction..................................................................................................................16-2
16.2 Control Registers.........................................................................................................16-4
16.3 A/D Terminology and Conversion Sequence.............................................................16-14
16.4 ADC Module Configuration........................................................................................16-16
16.5 Selecting the Voltage Reference Source...................................................................16-16
16.6 Selecting the A/D Conversion Clock..........................................................................16-17
16.7 Selecting Analog Inputs for Sampling........................................................................16-18
16.8 Enabling the Module..................................................................................................16-20
16.9 Specifying Sample/Conversion Control .....................................................................16-20
16.10 How to Start Sampling ...............................................................................................16-21
16.11 How to Stop Sampling and Start Conversions...........................................................16-22
16.12 Controlling Sample/Conversion Operation.................................................................16-32
16.13 Specifying Conversion Results Buffering...................................................................16-33
16.14 Conversion Sequence Examples...............................................................................16-37
16.15 A/D Sampling Requirements......................................................................................16-49
16.16 Reading the ADC Result Buffer .................................................................................16-50
16.17 Transfer Function (10-bit Mode).................................................................................16-52
16.18 Transfer Function (12-bit Mode).................................................................................16-53
16.19 ADC Accuracy/Error...................................................................................................16-54
16.20 Connection Considerations........................................................................................16-54
16.21 Code Examples..........................................................................................................16-54
16.22 Operation During Sleep and Idle Modes....................................................................16-61
16.23 Effects of a Reset.......................................................................................................16-62
16.24 Special Function Registers Associated with the ADC................................................16-62
16.25 Design Tips................................................................................................................16-64
16.26 Related Application Notes..........................................................................................16-65
16.27 Revision History.........................................................................................................16-66

dsPIC33F Family Reference Manual
DS70183A-page 16-2 © 2006 Microchip Technology Inc.
16.1 INTRODUCTION
The dsPIC33F family devices have up to 32 A/D input channels. These devices also have up to
two ADC modules (ADCx, where x = 1 or 2), each with its own set of Special Function Registers
(SFRs).
The 10-bit or 12-bit Operation Mode (AD12B) bit in the ADCx Control 1(ADxCON1) register
allows each of the ADC modules to be configured by the user application as either a 10-bit, 4
Sample/Hold (S/H) ADC (default configuration) or a 12-bit, 1 Sample/Hold ADC.
The 10-bit ADC configuration (AD12B = 0) has the following key features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
• External voltage reference input pins
• Simultaneous sampling of up to four analog input pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• DMA support, including Peripheral Indirect Addressing
• Four result alignment options (signed/unsigned, fractional/integer)
• Operation during CPU Sleep and Idle modes
Depending on the particular device pinout, the ADC can have up to 32 analog input pins, desig-
nated AN0 through AN31. In addition, there are two analog input pins for external voltage refer-
ence connections. These voltage reference inputs can be shared with other analog input pins.
The actual number of analog input pins and external voltage reference input configuration will
depend on the specific device. Refer to the device data sheet for further details.
The analog inputs are multiplexed to four Sample/Hold amplifiers, designated CH0-CH3. One,
two, or four of the Sample/Hold amplifiers can be enabled for acquiring input data. The analog
input multiplexers can be switched between two sets of analog inputs during conversions. Uni-
polar differential conversions are possible on all channels using certain input pins (see
Figure 16-1).
An Analog Input Scan mode can be enabled for the CH0 Sample/Hold Amplifier. A Control
register specifies which analog input channels are included in the scanning sequence.
The ADC is connected to a single-word result buffer. However, multiple conversion results can
be stored in a DMA RAM buffer with no CPU overhead. Each conversion result is converted to
one of four 16-bit output formats when it is read from the buffer.
The 12-bit ADC configuration (AD12B = 1) supports all the above features, except:
• In the 12-bit configuration, conversion speeds of up to 500 ksps are supported
• There is only one Sample/Hold amplifier in the 12-bit configuration, so simultaneous
sampling of multiple channels is not supported.
Note: The ADC module needs to be disabled before the AD12B bit is modified.

© 2006 Microchip Technology Inc. DS70183A-page 16-3
Section 16. Analog-to-Digital Converter (ADC)
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Figure 16-1: ADC Block Diagram
S/H
+
-
Conversion Conversion Logic
VREF+(1)
AVSS
AVDD
ADC
Data Format
16-bit
ADC Result
Bus Interface
00000
00101
00111
01001
11110
11111
00001
00010
00011
00100
00110
01000
01010
01011
AN30
AN31
AN8
AN9
AN10
AN11
AN2
AN4
AN7
AN0
AN3
AN1
AN5
CH1(2)
CH2(2)
CH3(2)
CH0
AN5
AN2
AN11
AN8
VREF-
AN4
AN1
AN10
AN7
VREF-
AN3
AN0
AN9
AN6
VREF-
AN1
VREF-
VREF-(1)
Sample/Sequence
Control
Sample
CH0,CH1,
CH2,CH3
Input MUX
Control
Input
Switches
S/H
+
-
S/H
+
-
S/H
+
-
AN6
Buffer
Result
Note1: VREF+, VREF- inputs can be multiplexed with other analog inputs. See device data sheet for details.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: The ADC1 module can use all 32 analog input pins (AN0-AN31), whereas ADC2 can use only 16
analog input pins (AN0-AN15).
Analog Input Pins(3)

dsPIC33F Family Reference Manual
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16.2 CONTROL REGISTERS
The ADC module has ten Control and Status registers. These registers are:
• ADxCON1: ADCx Control Register 1(1)
• ADxCON2: ADCx Control Register 2(1)
• ADxCON3: ADCx Control Register 3(1)
• ADxCON4: ADCx Control Register 4(1)
• ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register(1)
• ADxCHS0: ADCx Input Channel 0 Select Register
• AD1CSSH: ADC1 Input Scan Select Register High
• ADxCSSL: ADCx Input Scan Select Register Low
• AD1PCFGH: ADC1 Port Configuration Register High
• ADxPCFGL: ADCx Port Configuration Register Low
The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.
The ADxCON4 register sets up the number of conversion results storedin a DMA buffer for each
analog input in the Scatter/Gather mode. The ADxCHS123 and ADxCHS0 registers select the
input pins to be connected to the Sample/Hold amplifiers. The ADxPCFGH/L registers configure
the analog input pins as analog inputs or as digital I/O. The ADCSSH/L registers select inputs to
be sequentially scanned.

© 2006 Microchip Technology Inc. DS70183A-page 16-5
Section 16. Analog-to-Digital Converter (ADC)
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Register 16-1: ADxCON1: ADCx Control Register 1(1)
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
ADON — ADSIDL ADDMABM —AD12B FORM<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
HC,HS R/C-0 HC, HS
SSRC<2:0> — SIMSAM ASAM SAMP DONE
bit 7 bit 0
Legend: HC = Cleared by hardware HS = Set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1= ADC module is operating
0=ADCisoff
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12 ADDMABM: DMA Buffer Build Mode bit
1= DMA buffers are written in the order of conversion. The module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer.
0= DMA buffers are written in Scatter/Gather mode. The module provides a Scatter/Gather address
to the DMA channel, based on the index of the analog input and the size of the DMA buffer.
bit 11 Unimplemented: Read as ‘0’
bit 10 AD12B: 10-bit or 12-bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8 FORM<1:0>: Data Output Format bits
For 10-bit operation:
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s= .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s= .NOT.d<11>)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00 = Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = MPWM interval ends sampling and starts conversion
010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion
001 = Active transition on INTx pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
bit 4 Unimplemented: Read as ‘0’
Note 1: The ‘x’ in ADxCON1 and ADCx refers to ADC 1 or ADC 2.

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bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set.
0= Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1= ADC Sample/Hold amplifiers are sampling
0= ADC Sample/Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed.
0= ADC conversion not started or in progress
Automatically set by hardware when A/D conversion iscomplete. Softwarecan write‘0’ to clear DONE
status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
Register 16-1: ADxCON1: ADCx Control Register 1(1) (Continued)
Note 1: The ‘x’ in ADxCON1 and ADCx refers to ADC 1 or ADC 2.

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Register 16-2: ADxCON2: ADCx Control Register 2(1)
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG<2:0> —— CSCNA CHPS<1:0>
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0> BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1= Scan inputs for CH0+ during Sample A bit
0= Do not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1= ADC is currently filling the second half of the buffer. The user application should access data in
the first half of the buffer
0= ADC is currently filling the first half of the buffer. The user application should access data in the
second half of the buffer.
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Increment Rate for DMA Addresses bits
1111 = Increments the DMA address or generates interrupt after completion of every 16th
sample/conversion operation
1110 = Increments the DMA address or generates interrupt after completion of every 15th
sample/conversion operation
• • •
0001 = Increments the DMA address or generates interrupt after completion of every 2nd
sample/conversion operation
0000 = Increments the DMA address or generates interrupt after completion of every
sample/conversion operation
bit 1 BUFM: Buffer Fill Mode Select bit
1= Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer
on next interrupt
0= Always starts filling the buffer from the start address.
bit 0 ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
Note 1: The ‘x’ in ADxCON2 and ADCx refers to ADC 1 or ADC 2.
VREFH VREFL
000 AVDD Avss
001 External VREF+Avss
010 AVDD External VREF-
011 External VREF+ External VREF-
1xx AVDD Avss

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Register 16-3: ADxCON3: ADCx Control Register 3(1)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC —— SAMC<4:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1= ADC Internal RC Clock
0= Clock Derived From System Clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto Sample Time bits
11111 = 31 TAD
• • •
00001 = 1 TAD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = TCY ·(ADCS<7:0> + 1) = 256 ·TCY = TAD
• • •
00000010 = TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001 = TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000 = TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
Note 1: The ‘x’ in ADxCON3 and ADCx refers to ADC 1 or ADC 2.

© 2006 Microchip Technology Inc. DS70183A-page 16-9
Section 16. Analog-to-Digital Converter (ADC)
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Register 16-4: ADxCON4: ADCx Control Register 4(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DMABL<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111 =Allocates 128 words of buffer to each analog input
110 =Allocates 64 words of buffer to each analog input
101 =Allocates 32 words of buffer to each analog input
100 =Allocates 16 words of buffer to each analog input
011 =Allocates 8 words of buffer to each analog input
010 =Allocates 4 words of buffer to each analog input
001 =Allocates 2 words of buffer to each analog input
000 =Allocates 1 word of buffer to each analog input
Note 1: The ‘x’ in ADxCON4 and ADCx refers to ADC 1 or ADC 2.

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Register 16-5: ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register(1)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NB<1:0> CH123SB
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NA<1:0> CH123SA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is VREFL
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3 Unimplemented: Read as ‘0’
bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is VREFL
bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
Note 1: The ‘x’ in ADxCHS123 and ADCx refers to ADC 1 or ADC 2.