Microchip Technology Microsemi UG0936 User manual

UG0936
User Guide
RT PolarFire FPGA Transceiver

50200936. 1.0 2/21
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Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 iii
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Enhanced Receiver Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Transceiver PCS Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 8b10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.2 64b66b/64b67b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.3 PIPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.4 PIPE Interface Compliance Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.5 PMA Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 PCS/FPGA Fabric Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.1 Non-Deterministic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.2 Deterministic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4.3 Transceiver Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.4 Transceiver Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.5 Transceiver Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5.1 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.2 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.5.3 Transmit Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.4 Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6 PMA and PCS Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7 PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1 Libero Configurators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1.1 Transceiver Reference Clock Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.2 Transmit PLL Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.1.3 Transceiver Interface Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.2 Transceiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.2.1 Full-Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2.2 Half-Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3 Libero Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4 Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4.1 Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4.2 Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.5 Adding Physical Constraints Using Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.5.1 Invoking the Pin Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.6 Transceiver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.1 Transceiver Initialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 Signal Integrity Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 iv
5.1.1 Transmit Emphasis and DC Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.1.2 Impedance (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.1.3 Tx Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.1.4 Transmit Common Mode Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.1 Rx Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.2 Rx CTLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.3 Rx Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.4 AC/DC Coupled Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.5 Loss-of-Signal Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.2.6 Polarity Invert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3 IO Editor for Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.1 IO Editor—Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.2 PDC Constraint File Commands for XCVR Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4 SmartDebug Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.4.1 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.4.2 SmartBERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.4.3 Eye Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1 RTL Simulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7 Debug and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.1 PRBS Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.2 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.2.1 EQ Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.2.2 EQ Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.2.3 CDR Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.3 Dynamic Reconfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8 Board Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.1 Transceiver Top-Level Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.2 Design for Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2.1 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2.2 JESD204B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.3 10G Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.3.1 Unused Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.4 Transceivers Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 v
Figures
Figure 1 Transceiver Lane Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2 Transceiver Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3 Receiver Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 Input Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 CDR Lock Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6 Transceiver Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7 Transmit Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8 Enhanced Receiver Management in XCVR Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 Calibration Options for Enhanced Receiver Management Operations . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10 Exposing RX_READY_CDR and RX_VAL_CDR Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11 DFE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 First Lock Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13 Disruption of Serial Rx Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14 Restart after Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15 On-Demand Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16 8b10b Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17 64b6xb Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18 64b66b Receive Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19 64b66b Receive Sequence For 64-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20 64b66b Transmit Sequence For 64-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21 64b66b Transmit Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22 64b67b Transmit Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23 64b67b Receive Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24 Initial Receiver Detection Response For Receiver-Not-Present . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25 Initial Receiver Detection For Receiver-Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26 Subsequent Receiver Detection Where Prior Status Was Receiver-Not-Present . . . . . . . . . . . . . 41
Figure 27 PMA-Bus Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 28 PMA Only Data Path – 80-bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29 PMA Only Data Path – Less Than or Equal to 40-bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 30 Global-shared Clocking Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 31 Non-Deterministic Interface With FWF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 32 Non-Deterministic Interface Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 33 Non-Deterministic Transceiver Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 34 Deterministic Timing Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 35 Deterministic Transceiver Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 36 Deterministic Transceiver Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 37 Transceiver Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 38 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 39 Spread Spectrum Clocking Modulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 40 Using TXPLL_SSC For Upto Four Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 41 Using TXPLLs For Upto Four Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 42 FPGA Logic For TX Alignment (5 to 8 Lanes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 43 Reference Clock (REFCLK) Interface to Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 44 Typical Jitter Attenuator Application Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 45 Jitter Attenuation TXPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 46 JAPLL Custom Protocol Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 47 Reference Clock Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 48 Rx JA Clock Frequency (XCVR Configurator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 49 Dedicated Transceiver Reference Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 50 REFCLK Input Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 51 RTPF500T Transceiver and Transmit PLL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 52 PCS Rate Switch between 8b10b and 64b66b Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 53 Transceiver Reference Clock Selection from Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 54 Transceiver Reference Clock Configurator GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 vi
Figure 55 Transceiver Reference Clock Mode Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 56 PF_XCVR_REF_CLK With One Single-Ended Input and Single Output Clock . . . . . . . . . . . . . . . 78
Figure 57 PF_XCVR_REF_CLK With Two Single-Ended Input and Two Output Clock . . . . . . . . . . . . . . . . . 78
Figure 58 PF_XCVR_REF_CLK With Differential Input and Single Output Clock . . . . . . . . . . . . . . . . . . . . . 79
Figure 59 PF_XCVR_REF_CLK With Fabric Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 60 Transceiver Transmit PLL Selection from Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 61 Transmit PLL Configurator GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 62 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 63 Fabric Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 64 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 65 Spread Spectrum Clock Generation Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 66 Spread Spectrum Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 67 Enable Dynamic reconfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 68 CLK_125 GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 69 Transceiver Interface Selection From Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 70 Transceiver Interface Configuration GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 71 PMA Mode—Enable CDR Bit-Slip Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 72 XCVR Component With CDR Bit-Slip Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 73 XCVR Component With BMR Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 74 XCVR Component With DRI Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 75 Transceiver with ERM Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 76 PMA Only PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 77 8b10b PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 78 64b66b PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 79 Soft PIPE PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 80 Completed Transceiver Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 81 Completed Transceiver Subsystem with ERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 82 Transceiver Modes shown in Transceiver GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 83 Derive Constraints using Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 84 IO Editor GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 85 XCVR Placement Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 86 XCVR Signal Integrity Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 87 Signal Integrity Conditioning Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 88 IO Editor—XCVR View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 89 IO Editor—Signal Integrity View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 90 SmartDebug Signal Integrity GUI Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 91 Loopback Modes—Far-end Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 92 PRBS Self Test Near-End Loopback Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 93 Test Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 94 Eye Monitor Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 95 Example of Optimize DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 96 RTL Simulation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 97 Transceiver Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 98 PF_DRI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 99 Connectivity Between XCVR Interface and PCIe Edge Connector . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 100 Connectivity Between RT PolarFire Device and JESD204B Interface . . . . . . . . . . . . . . . . . . . . . 122
Figure 101 Connectivity Between RT PolarFire Device to SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 vii
Tables
Table 1 Supported Serial Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2 CDR Lock Mode Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3 Mode of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4 ERM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5 DFE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6 System Registers Affecting 8b10b Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7 8b10b Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8 64b6xb Transmit Data Path Blocks, Fabric to PMA Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9 64b6xb Receive Data Path Blocks, PMA to Fabric Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10 System Registers Affecting 64b6xb Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11 64b66b/64b67b Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12 PIPE Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13 PMA Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 14 Clock Region Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15 Transceiver Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 16 Transceiver Interface Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 17 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 18 Transmit PLL Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 19 Jitter Attenuation PLL Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 20 XCVR REFCLK Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 21 Reference clock input buffer Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 22 RT PolarFire Transceiver Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 23 Port Crossover between the 8b10b and 64b66b Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24 System Registers Affecting 8B10B and 64B6xB Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 25 Transceiver Configurator Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 26 Transceiver Reference Clock Configurator GUI Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 27 Transmit PLL Configurator GUI Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 28 Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 29 Transceiver Interface General Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 30 Transceiver Interface PMA Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 31 Transceiver Interface PCS Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 32 Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 33 PCS Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 34 Physical Constraint Instances For XCVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 35 Amplitude and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 36 LOS Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 37 TX Attributes and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 38 RX Attributes and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 39 Transceiver Device Level Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 40 Transceivers Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Revision History
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the current publication.
1.1 Revision 1.0
The first publication of this document.

Overview
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 2
2 Overview
The RT PolarFire® FPGA family includes multiple embedded low-power, performance-optimized
transceivers. Each transceiver has both the physical medium attachment (PMA), protocol physical
coding sub-layer (PCS) logic, and interfaces to the FPGA fabric. The transceiver has a multi-lane
architecture with each lane natively supporting serial data transmission rates from 250 Mbps to
10.3125 Gbps.
The transceiver includes all required analog functions for high-speed data transmission between devices
over printed circuit boards (PCB) and high-quality cables. The transceiver is suitable for a variety of
device-to-device communication protocols, as shown in the following table.
Table 1 • Supported Serial Protocols
Protocol Standard/Version Protocol Standard/Version
PCIe Gen1 CPRI1
1. Common Public Radio Interface (CPRI) Specification V7.0 (2015-10-09).
CPRI-1, 2, 3, 4, 5, 6, 7, 7A, 8, 9
PCIe Gen2 SATA2
2. SATA is supported using PMA only mode.
1.0a
XAUI IEEE 802.3 SATA22.0
Interlaken3
3. Interlaken Protocol Specification, v1.2.
10.3125 SATA23.0
Interlaken36.375 SDI-SD SMPTE 259M
10GBASE-R IEEE 802.3 SDI-HD SMPTE 292M
10GBASE-KR4
4. PMA supports 10GBASE-KR operation.
IEEE 802.3 SDI-3G SMPTE 424M
Fibre Channel 1GFC SGMII
Fibre Channel 2GFC 1000BASE-X IEEE 802.3
Fibre Channel 4GFC LiteFast Proprietary Lightweight Serial
Protocol Interface (up to
10.3125 Gbps, 8b10b mode
only.)
Fibre Channel 8GFC RXAUI N/A
JESD204B LV-OIF-SxI5 QSGMII
JESD204B LV-OIF-6G-SR SLVS-EC
JESD204B LV-OIF-11G-SR DisplayPort
USXGMII CoaXPress

Overview
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 3
Figure 1 • Transceiver Lane Overview
Note: Transmit/receive fabric interfaces are specified in the associated PCS pin lists, that is, 8b10b, 64b6xb,
PIPE, and PMA Only.
Note: For more information on PCIe Sub-system, see UG0685: PolarFire FPGA PCI Express User Guide.
Transmit
PCS/
Fabric
Interface
Transmit PMA
PCIe Sub-System (PCIESS)
Transmit PCS
Receive
PMA
Transmit PLL
Reference
Clock
Network
Receive
PCS
Polarity Receive
PCS/
Fabric
Interface
PCIe Sub-System (PCIESS)
8b10b
Encoder
64b/6xb
Encoder
PCIe/PIPE
Pre-/Post-
Emphasis
Serializer
PCS
Divider
Out of Band
Electrical
Idle
PMA Only
CTLE
Eye
Monitor
Jitter
Attenuation
or Spread
Spectrum
Frac-N
PLL
8b10b
Decoder
64b/6xb
Decoder
PCIe/PIPE
PMA Only
PCS
Divider
÷ 1, 2, 4, 8, 11
CDR w/DFE
Deserializer
Loopback
FIFO
XCVR_TXP
XCVR_TXN
XCVR_RXP
XCVR_RXN
CTLE: Continuous Time Linear Equalization
DFE: Decision-feedback Equalizer
Optional path used
with Jitter
Attenuation
EQ Far_end Loopback or
Near-End Loopback
CDR Far-End
Loopback
PCIe
Rx
Det
LOS
Det

Overview
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 4
2.1 Features
The RT PolarFire transceiver enables users to quickly build high-speed links that support many standard
protocols with the features listed:
• Supports data rates from 250 Mbps up to 10.3125Gbps.
• Serialization/deserialization width at FPGA fabric interface—8, 10, 16, 20, 32, 40, 64, and 80 bits.
• Differential output termination from 85 , 100 , and 150 
• Low-power modes.
• Receivers are compatible with CML and LVDS I/O Standards.
• Transmitters are compatible with CML, LVDS, and LVPECL I/O Standards.
• Configurable transmit pre- and post-tap de-emphasis controls.
• Configurable amplitude control from 250 mV to 1 V differential.
• Receivers detect circuitry for use with PCIe.
• Out-of-band (OOB), electrical idle signaling capability for
• Serial-attached SCSI: small computer system interface (SAS).
• Serial advanced technology attachment (SATA).
• Peripheral component interconnect express (PCIe).
• Spread-spectrum generation built into the transmit phase-locked loop (PLL).
• 1 Gb and 10 Gb SyncE compatible Jitter attenuation available in the transmit PLL for loop timing
applications.
• Continuous time linear equalizer (CTLE) with optional auto-calibration to improve received signal
integrity.
• 5-tap decision feedback equalizer (DFE) with auto-calibration to compensate for high-frequency
losses.
• Receive data eye monitor for link analysis.
• Configurable peak detector/signal detect.
• Polarity inversion (receiver).
• Diagnostic loopback modes.
• Embedded pseudo-random binary sequence (PRBS) test pattern generators/checkers—available
PRBS polynomials (2n), where n = 7, 9, 15, 23, and 31.
• AC JTAG (IEEE 1149.6) and DC JTAG (IEEE 1149.1) transmitter and receiver.
• IBIS-AMI support of transceiver inputs and outputs
• Supports AC and DC coupling modes with configurable transmit common-mode voltage.
• Embedded PCS:
• 8b10b—encoding/decoding is provided.
• 64b6xb—64b/66b or 64/67b encoding/decoding with gearbox logic is provided.
• PIPE—PHY interface for the PCI Express Rev 3.0 supporting PCIe Gen1/2.
• PMA only—direct access to the PMA without any encoding.
• PCIe—fully embedded PCIe Gen1/Gen2 root-port or endpoint subsystem (PCIESS) with AXI4
user interface with built-in DMA. The embedded PCIe controller subsystem is available only
within Quad0. See UG0685: PolarFire FPGA PCI Express User Guide for more information on
the embedded PCIE capabilities and its usage.
The Microsemi Libero® SoC software supports configuration for the various modes of transceiver
operations. Table 1, page 2 shows which of these configurations support industry-standard protocols and
user-defined custom protocols. The Libero SoC software design tools allow designers to set the
configuration needed for a specific operational mode for each transceiver lane. The software correctly
provisions and generates all the required programming and configuration data used to initialize and bring
the transceiver into operation. The transceiver configuration registers are set automatically by the Libero
SoC transceiver configurator. These registers must be left at their default values set by the configurator,
except for use cases that explicitly request different values.

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 5
3 Functional Description
The RT PolarFire transceiver (Figure 1, page 3) is divided into four distinct transmit (Tx) and receive (Rx)
blocks:
• PMA
• PCS interface block, including a dedicated PCIe PCS
• Transmit PLL (Tx PLL)
• Reference clock inputs
The high-speed PMA blocks connect to the FPGA fabric through the PCS block. The PMA generates the
required clocks and converts the transmit data from parallel to serial, and receive data from serial to
parallel. Each PMA block includes a connection to a PCS block and associated interface to the FPGA
fabric making up a transceiver lane. The PCS interface block provides several industry-standard
interfaces for use in protocol-specific designs.
A group of four transceiver lanes is called a quad. Each quad has a local transmit PLL used exclusively
within the four transceiver lanes. Additional transmit PLLs are shared between quads.
In addition to the 8b10b, 64b6xb, PIPE, and PMA only blocks, two PCIe PCS logic blocks are included in
each RT PolarFire device. These blocks include hard embedded logic that provides full-featured PCIe
endpoint/root port sub-system. These PCIe subsystems (PCIESS) have hard connections to multiple
transceiver lanes, providing flexibility for ×1, ×2, and ×4 width links. See UG0685: PolarFire FPGA PCI
Express User Guide for additional information pertaining to PCIe.
3.1 PMA
The transceiver lanes include PMA receiver and transmitter sub-modules. These PMA sub-modules
include the input and output buffers, signal conditioning circuits, CDRs, and transceiver. The PMA
architecture allows the receive and transmit portions of each lane to operate independently. The PMA
features are initialized at power-up and can also be altered during device operation using an APB
dynamic reconfiguration interface (DRI).
The SmartDebug tool set provides access to dynamic changes of PMA features, including transmit and
receive tuning, and receive eye monitoring capabilities.
3.1.1 Receiver
The receiver deserializes high-speed serial data received through the input buffer by creating a parallel
data stream for the FPGA fabric and recovering the clock information from the received data. The
receiver portion of the PMA includes the receiver buffer, the clock and data recovery (CDR) unit, and the
deserializer. The deserializer within the receive PMA passes deserialized data to the PCS block across a
data bus up to 40-bits wide of the PMA-PCS interface, which provides the data path to the gearing logic
before the data is passed to the FPGA fabric.

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 6
Figure 2 • Transceiver Receiver
3.1.1.1 Receive Input Buffer
The receiver provides an external input interface through differential pins, XCVR_RXP/N, as shown in
the following figure. The receiver includes a current mode logic (CML) input buffer with programmable
DC restoration that is used in either AC- or DC-coupled applications.
The receive buffer provides an on-die differential termination scheme which can be programmed to 85 ,
100 , or 150 . The receiver buffer also includes a high-impedance (high-Z) mode for hot-swap
capability when the device is powered off. Additionally, the receiver input supports logical swapping of the
polarity of the P and N pins for added flexibility.
Figure 3 • Receiver Input Buffer
Note: VICM is connected to VDDA when AC-coupled link is configured. DC-coupled configurations effectively
disconnects VICM source. See AC/DC Coupled Connection, page 104.
Each receiver lane includes optional signal threshold detection circuitry that users can select according
to protocol or application requirements. This feature identifies whether the signal level present at the
receiver input buffer is above the signal detect threshold voltage needed to trip or activate the receiver
input, which prevents false activity on the receiver path. The signal detection has both a high and low
signal detector. The Libero SoC software configurator provides the correct setting based on protocol or
customization.
Note: The user can also use a JTAG-based interface from SmartDebug to experiment with receiver settings.
Receive PMA Receive PCS
Polarity Receive
PCS/
Fabric
Interface
PCIe Sub-System (PCIESS)
CTLE
Eye
Monitor
8b10b
Decoder
64b/6xb
Decoder
PCIe/PIPE
PMA Only
PCS
Divider
CDR w/DFE
Deserializer
Reference
Clock
Network
XCVR_RXP
XCVR_RXN
Signal
Detect
CTLE
VICM
Input Common-Mode
Voltage
XCVR_RXP
XCVR_RXN
On-Die Termination
LOS Detect

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 7
3.1.1.2 Continuous-Time Linear Equalizers (CTLE)
The CTLEs equalize a lane’s low-pass response to compensate for high-frequency losses in that lane,
thereby improving the quality of the received signal. This circuit can be adjusted to compensate for any
physical lane mismatches.
There are two transparent stages of CTLE and a separate pair of stages for the decision feedback
equalizer (DFE)/eye monitor receive path. The input signal path (Figure 4, page 7) is conditioned by
tuning the incoming signal allowing the user to observe the effects of the tuning. The DC gain and peak
bandwidth of each stage is selected with Libero; CTLE settings can be selected based on DC gain,
peaking frequency, and AC gain or with an auto adaptive setting through the Libero transceiver interface
configurator. The automatic or adaptive mode uses internally generated settings to the physical channels
for lane optimization.
Figure 4 • Input Signal Path
3.1.1.3 Decision Feedback Equalizer
In the receiver front end, an optionally enabled 5-tap decision feedback equalizer (DFE) is available to
equalize the lane response in conjunction with the CTLE. The DFE allows better compensation of
transmission channel losses than a linear equalizer of CTLE, by providing a closer adjustment of filter
parameters. The tap values of the DFE are the coefficients of this filter that are set by the adaptive
algorithm.
The DFE mitigates lane noise or inter-symbol interference (ISI) caused by reflections or cross-talk
without amplifying the high-frequency noise within the data. The DFE-based operation uses current bit
information to cancel ISI for the following bit through a feedback mechanism, allowing the following bits to
be correctly sampled. Using taps to delay and multiply the symbols, the DFE effectively cancels out
interference on the analog signal. Similar to the CTLE operation, the DFE has an automatic mode. When
the DFE is used in automatic mode, the CTLE can be in automatic mode as-well.
The operation is nonlinear, allowing it to overcome the notch response that the CTLE cannot perform.
The DFE also includes an automatic calibration that finds the best possible tuning to match the
transceiver lane to the system channel.
Receiver Input CTLE DFE + CDR
Eye
Monitor
Deserializer
Adaptive Tuning
SmartDebug
Via JTAG

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 8
3.1.1.4 Eye Monitor
The eye monitor is on-device circuitry to visualize the post-equalization signal quality in the receive path
while the data path is still active in the system. The non-destructive eye monitor runs a separate sampler
in parallel with the CDR and DFE data sampler. This permits the system to remain operational while the
eye monitor is functioning.
The eye monitor systematically adjusts the offsets across the complete eye, calculates the bit-error rate
(BER) for each offset setting, then correlates the BER and offset to statistically rebuild the eye diagram.
Eye diagram statistics can be read and reconstructed using the Libero SmartDebug tools, which permits
access through a JTAG interface for transceiver debugging and test access.
Swing and de-emphasis can be configured in hundreds of combinations. It is, however, very
cumbersome for the user to tune these when optimizing the transceiver input. The eye monitor feature
eases the need to go through the manual steps to find the adjustments. It is used as part of the
CTLE/DFE auto-calibration. The eye monitor feedback mechanism optimizes the correct DFE settings by
using a duplicate DFE circuit to monitor and adjust the incoming data stream.
3.1.1.5 Receive Clock and Data Recovery
The receive CDR circuit follows the CTLE and works in tandem with the DFE. The receive CDR PLL can
lock onto the input reference clock or the incoming data stream to be able to re-time the incoming data.
The deserializer is closely coupled with the CDR, and translates the data from a serial to a parallel
stream.
3.1.1.5.1 CDR Options
The PMA of each lane includes a PLL used for the receiver CDR. The CDR PLL supports
lock-to-reference and lock-to-data modes, which allows customization of the CDR options best suited for
the application. It also includes a Burst-mode receiver option, which can switch between both options
that are selectable through the Libero transceiver configurator.
Lock-to-Reference: The phase frequency detector (PFD) in the CDR tracks the receiver input reference
clock. The PFD controls the charge pump that tunes the VCO in the CDR. The LOCK status signal is
asserted high to indicate that the CDR has locked to the phase and frequency of the receiver input
reference clock regardless of the data phase detector (PD). Lock-to-reference is used to lock the
transceiver CDR to the reference clock rather than the incoming data when the receiver is used as a
simple over-sampler, or when the CDR must be locked to a local oscillator.
Lock-to-Data: The CDR must use the lock-to-data mode to recover the clock and data from the incoming
serial data. In this mode, the data phase detector of the CDR tracks the incoming serial data at the
receiver input. Depending on the phase difference between the incoming data and the CDR output clock,
the PD controls the CDR charge pump that adjusts the VCO. The LOCK status signal is asserted when
the CDR finds valid data. The actual lock time depends on the incoming data stream's transition density.
Burst Mode Receiver: The transceiver CDR circuit has enhanced capabilities to support burst mode
receivers (BMR). BMR is used in NGPON2 and 10GEPON passive optical network applications for fast
and bounded lock times. The BMR option is used to implement the fast clock-data recovery when the
conventional bang-bang phase detector PLLs cannot meet the stringent lock times required by the
passive optical network (PON) applications.
Note: DFE auto-calibration is not available when the transceiver is configured for burst mode (BMR).

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 9
When BMR mode is selected, LANE_X_CDR_LOCKMODE[1:0] are exposed for CDR mode control. The
following table lists the value and the description of the CDR lock mode control bits.
For detailed CDR specifications, see DS0141: PolarFire FPGA Datasheet. For application example and
implementation details, see DG0841: PolarFire Burst Mode Receiver Demo Guide.
Lock to Data with 2X Gain: This transceiver option is used to implement the fast clock-data recovery
when incoming data streams such as stressful SDI patterns require high gain to quickly phase lock to the
incoming pattern. This mode produces faster lock times than that of normal lock-to-data mode.
The following figure shows the CDR lock mode options.
Figure 5 • CDR Lock Mode Options
3.1.1.6 Bit Slip
The deserializer has a bit-slip feature for word alignment. In this mode, the CDR slips to the next bit from
the deserializer. This feature helps with building word-alignment logic in the fabric. It is not used with the
built-in 8b10b PCS core but is available for PMA only applications using fabric-based alignment. This
feature adjusts the alignment of the deserialized word by 1-bit in either direction when the bit-slip feature
is active, reducing the uncertainty by ensuring deterministic latency. This feature is supported by the
transceiver configurator. The configurator enables this RX_SLIP input port. This port requests the
transceiver CDR lane slip the parallel boundary by 1-bit.
In PMA mode applications, the RX_BIT_SLIP port is exposed on the block for the fabric to access. The
RX_BIT_SLIP rising edge requests Rx data path slip relative to the RX_CLK by 1-bit (UI) using
handshaking between RX_BIT_SLIP and RX_VAL. The handshake works as follows:
• Fabric must wait for RX_VAL = 1. Then RX_BIT_SLIP may be asserted to initiate slip.
• XCVR responds by lowering RX_VAL to 0.
• Fabric then lowers RX_BIT_SLIP.
• XCVR completes the slip and the RX_VAL is assigned to 1 synchronously with respect to RX_CLK
rising edge.
3.1.1.7 Receive PCS Divider
The PCS divider divides the bit-rate clock from the CDR PLL to a lower rate for use in the receive PCS.
The PMA sends parallel data from the de-serializer up to 40-bits wide. This divider also sets the width of
the parallel data provided to the PCS to 8, 10, 16, 20, 32, 40, 64, or 80 bits. The Libero transceiver
configurator sets the divider based on the data rate and ultimate fabric interface width.
Table 2 • CDR Lock Mode Values
LANE_X_CDR_LOCKMODE[1:0]
Values Mode
2’b00 Not used
2’b01 High gain1
1. High Gain mode is used during Preamble/delimiter detection
phase to fast phase lock to the incoming RX data. This mode may
generate additional clock jitter on the recovered clock. Once the
preamble/de-limiter is detected, it is recommended to switch to
normal CDR mode to minimize jitter.
2’b10 Lock to reference
2’b11 Normal Mode2
2. This is used when payload is received form burst mode receiver.

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 10
3.1.1.8 Receiver Calibration
The RT PolarFire XCVR receivers include both analog and digital blocks that require calibration to
compensate for process, voltage, and temperature (PVT) variations in conjunction with signal integrity.
The embedded calibration block of RT PolarFire transceiver performs calibration operations that optimize
the performance of the transceiver interconnection. It includes an adaptive deserializer calibration
algorithm to correct for lossy channels.
Libero selects CTLE only and CTLE/DFE modes based on the system data rate and channel loss needs.
The pre-determined settings provide the starting point for the design. These settings are configured to
the appropriate calibration requirements based on the targeted requirements. Three types of calibrations
are carried out within the Rx:
• CTLE DC-offset
• CTLE Frequency Response
• DFE
3.1.1.8.1 CTLE DC-offset Calibration
Process, voltage, and temperature (PVT) variations result in a DC-offset of the receiver front-end
amplifiers, that is, the output is different from zero when the input is zero. This limits the sensitivity of the
receiver and therefore the signal-to-noise (SNR). It also limits the performance of the other calibration
mechanisms.
The CTLE DC-offset calibration circuitry calibrates the DC-offset by zeroing the input and adding an
offset. This offset is dynamically determined by a binary search in response to the logic output of the
amplifier.
3.1.1.8.2 CTLE Frequency Response Calibration
The CTLE frequency response can be set to a few discrete values, therefore calibration depends on
searching for the settings that result in the largest eye area.
CTLE DC_offset and CTLE Frequency Response calibration together make up the CTLE solution. For
the most lossy and disruptive channels, many or all CTLE settings combinations can result in a zero eye-
opening area. In these scenarios, DFE can sometimes allow for a non-zero area, which would otherwise
be impossible with CTLE alone.
3.1.1.8.3 DFE Calibration
DFE calibration is carried out by an embedded sequence function, which is optimized to avoid local
minima, achieve predictable results, allow for low area, and operate at high clock speeds. It adjusts the
feedback coefficients in response to the eye-area. The sequence of the function is used to determine the
width, height, and center of the eye opening. DFE Calibration is carried out by a algorithm that adjusts
the feedback coefficients (from H1 to H5) by trial-and-error in response to the eye-area of the
eye_monitor. The algorithm operates on one dimension (a single coefficient) at a time. It takes a step of
size 1 in the positive direction and then the negative direction that is H1+1 and H1-1. If the area improves
on either step, it continues to take another step in the same direction. If both directions yield a lower area,
it continues to the next coefficient with the same step size. After failing to improve the area on all
coefficients, it increases the step size and continue. If the area is improved, the step size immediately
reduces to 1. See the AC468: PolarFire FPGA Transceiver Decision Feedback Equalization Application
Note for more information.
Dependent on the specific design targets chosen through Libero, the design can be configured in one of
two modes that require calibration of the receiver.
In CTLE only mode, CTLE solution is executed to optimize gain/frequency settings using CTLE
Frequency Response and DC Offset calibration.
In CTLE/DFE mode, CTLE calibration is first run to optimize gain/frequency settings using CTLE
Frequency Response and DC Offset calibration. DFE calibration is then run for centering and
coefficients.
DFE is optionally programmed to be used in several operations. Full DFE calibration autonomously
calibrates to the best found DFE coefficients for optimized data eye centering. These are controlled by
Libero specified options.

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 11
DFE can also be set in static mode where the user can specify the exact DFE coefficients required by the
design. DFE Coefficients are set through PDC commands (see DFE Coefficients, page 97) can be used
from the register rather than from calibration. This mode does not expose the CALIB_REQ pin or any of
the pins to trigger auto-calibration or incremental calibration.
Incremental DFE is another option of calibration to incrementally improve the performance of the DFE
path. A specific PF_XCVR_ERM core is generated by Libero which, exposes the required pins to trigger
the incremental calibration.
Two algorithms are available for re-calibration.
• Data Eye clock centering Re-calibration
• DFE Coefficient Re-calibration.
Both algorithms do eye-centering, however, they are independent operations. Full calibration and Static
calibration are mutually exclusive and Incremental calibration of any of the two algorithms can only be
applied after at least one ‘Full calibration’.
Users can enable one or both choices in PF_XCVR_ERM configurator depending on the mode of
operation and the receiver calibration options selected.
The calibration blocks are used at power-up calibration and user demanded recalibration. These are
Libero configured. The following table lists the summary of mode of operations.
Examples of the specific types of calibration are:
ON_DEMAND
The receiver does not calibrate automatically. The user must initiate an on-demand calibration using
either the wires on the XCVR interface or over the DRI. If the specific design performs dynamic
reconfiguration using DRI, then the user routine must perform a recalibration each time the XCVR locks
to a new data rate and/or data pattern.
In CDR modes where data rate ≤ 10312.5 Mbps, the device performs DC offset calibration of the CDR
and the CTLE calibration when the user toggles the CALIB_REQ port. When calibration is completed, the
best DC offset and RX CTLE settings are applied to the receiver.
In DFE modes where data rate > 10312.5 Mbps, the device performs the same optimization as in CDR
mode with the addition on performing full DFE calibration of the DFE coefficients. When calibration is
completed the best DC offset, RX CTLE, and DFE coefficient settings are applied to the receiver.
To successfully complete the RX (CTLE) calibration process, the reference clocks must be stable and
free running at device power-up and valid data must be present at the transceiver Rx input buffers. The
data should be approximately the actual data that is received but does not need to be any particular data
pattern. However, for DFE, calibration can be dependent on the data pattern used at DFE calibration. For
Table 3 • Mode of Operations
CDR Mode
(Data Rate ≤ 10312.5 Mbps) Incrementally Re-calibrate Data Eye
Incrementally Re-calibrate DFE
Coefficients
None_CDR Not supported Not supported
On Demand Supported Not supported
On Demand and First Lock Supported Not supported
None_DFE Not supported Not supported
DFE Mode
(Data Rate > 10312.5 Mbps) Incrementally Re-calibrate Data Eye
Incrementally Re-calibrate DFE
Coefficients
None_CDR Not supported Not supported
On Demand Supported Supported
On Demand and First Lock Supported Supported
None_DFE Not supported Not supported

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 12
example, JESD204B startups with a continuous K28.5 stream, then later shifts to actual 8b10b data. This
is a change in data pattern and may impact calibrated DFE coefficients.
The RT PolarFire transceiver component is generated by the Libero software to include enhanced
receiver management logic to control the proper calibration of the receiver, see Enhanced Receiver
Management, page 14. The ERM manages calibration providing the user design a streamlined
procedure to initiate and monitor calibration from the fabric interface. These calibration modes have
higher power than using the NONE selection as the EYE MONITOR circuitry is active during these
modes.
ON_DEMAND_AND_FIRST_LOCK
It is same as On_Demand with the addition of auto calibration. Auto calibration occurs automatically the
first time the CDR locks to data. The user can also on-demand initiate a calibration event using wires on
the XCVR interface or over the DRI.
3.1.2 Transmitter
The transmitter takes parallel data from the FPGA fabric through the PCS-fabric interface block and
gearing logic. The data passes through the PMA-PCS interface to the serializer to create a high-speed
serial data stream using the serial clock provided from the transmit PLL. The transmitter portion of the
PMA includes the transmitter serializer and the transmitter buffer as shown in the following figure.
Figure 6 • Transceiver Transmitter
3.1.2.1 Serializer
The serializer provides the link between the high-speed interface and the transmit PCS by performing a
parallel-to-serial conversion. Each lane has up to 40-bit data bus to the transmit PCS block and a
separate post-divider for a divide by 1, 2, 4, 8, or 11. The post dividers are provided to divide the high-
speed clock from the TxPLL to exactly what the serializer requires for the data rate. This allows sharing
of a high-speed TxPLL by adjusting the local data rate within the transceiver lane. The glitch-free post-
divider also allows for dynamic switching between dividers and data rates using the APB DRI.
3.1.2.2 Transmit PCS Divider
The PCS divider divides the bit-rate clock from the transmit PLL to a lower rate TX_CLK clock for use in
the fabric. The PMA receives parallel data in the serializer up to 40-bits wide. This divider also sets the
width of the parallel data received from the PCS to 8, 10, 16, 20, 32, 40, 64, and 80 bits. The specific ratio
is a function of the parallel-to-serial or serial-to-parallel conversion in the PMA.
Transmit
PCS/
Fabric
Interface
Transmit PMA
PCIe Sub-System (PCIESS)
Transmit PCS
Transmit PLL
8b10b
Encoder
64b/6xb
Encoder
PCIe/PIPE
Pre-/Post-
Emphasis
Serializer
PCS
Divider
Out of Band
Electrical
Idle
PMA Only
÷ 1, 2, 4, 8, 11
XCVR_TXP
XCVR_TXN
PCIe
Rx
Detect

Functional Description
Microsemi Proprietary and Confidential UG0936 User Guide Revision 1.0 13
3.1.2.3 Transmit Output Buffer
The following figure shows the transmit output buffer of the transceiver lane, which connects to the PCB
via the XCVR_TXP/N output pins. The low-power H-bridge differential output buffer includes a
configurable driver for amplitude on the 100  differential load up to a maximum swing of 1 V peak to
peak. In addition, selectable levels of transmit common-mode voltage (Tx VCM) are available besides
the swing amplitude control for the output driver segments to control the amount of emphasis. The
transmit output buffer settings are accessible in real-time for adjustment through the JTAG interface
using SmartDebug. It includes a receiver detection to recognize the presence of a physical link. The
output buffer also has electrical idle capabilities used to orderly quiet the link transmitters.
Figure 7 • Transmit Output Driver
Transmit common-mode voltage levels for the drivers are selected by the user during the configuration of
the PMA when using the transceiver configurator in the Libero software. Reducing the transmit output
amplitude lowers the overall transceiver power consumption.
Note: The user can also use a JTAG-based interface from SmartDebug to experiment with transmit settings.
Pre-Cursor
H-Bridge
VDDA
XCVR_TXP
XCVR_TXN
TXCM
Output
Common
Mode
Main Cursor
Post Cursor
Pre-Driver
Pre-Driver
Pre-Driver
PCIe Receiver Detection
Electrical Idle