Microchip Technology Microsemi UG0677 User manual

UG0677
User Guide
PolarFire FPGA Transceiver

50200677. 9.0 5/21
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Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 iii
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.6 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.7 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.8 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.9 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Enhanced Receiver Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Transceiver PCS Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 8b10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2 64b66b/64b67b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.3 PIPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.4 PIPE Interface Compliance Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.5 PMA Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 PCS/FPGA Fabric Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4.1 Non-Deterministic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.2 Deterministic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.3 Transceiver Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.4 Transceiver Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4.5 Transceiver Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.5 Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.1 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.2 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5.3 Transmit Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5.4 Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.6 PMA and PCS Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.7 PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1 Libero Configurators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1.1 Transceiver Reference Clock Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1.2 Transmit PLL Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.1.3 Transceiver Interface Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2 Transceiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.1 Full-Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.2 Half-Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.3 Libero Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4 Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 iv
4.4.1 Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4.2 Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.5 Adding Physical Constraints Using Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.5.1 Invoking the Pin Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.6 Transceiver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.6.1 Transceiver Initialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5 Signal Integrity Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.1 Transmit Emphasis and DC Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.2 Impedance (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.3 Tx Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.4 Transmit Common Mode Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.1 Rx Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.2 Rx CTLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.3 Rx Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.4 AC/DC Coupled Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.5 Loss-of-Signal Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.2.6 Polarity Invert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3 IO Editor for Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3.1 IO Editor—Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.2 PDC Constraint File Commands for XCVR Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4 SmartDebug Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4.1 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.4.2 SmartBERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.4.3 Eye Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 RTL Simulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7 Debug and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.1 PRBS Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.2 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.2.1 EQ Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.2.2 EQ Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.2.3 CDR Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.3 Dynamic Reconfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8 Board Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.1 Transceiver Top-Level Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2 Design for Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2.1 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2.2 JESD204B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.3 10G Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.3.1 Unused Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.4 Transceivers Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 v
Figures
Figure 1 Transceiver Lane Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2 Transceiver Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 Receiver Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 Input Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5 CDR Lock Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6 Transceiver Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 Transmit Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 Enhanced Receiver Management in XCVR Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9 Calibration Options for Enhanced Receiver Management Operations . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10 Exposing RX_READY_CDR and RX_VAL_CDR Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11 DFE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12 First Lock Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13 Disruption of Serial Rx Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14 Restart after Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15 On-Demand Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16 8b10b Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17 64b6xb Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18 64b66b Receive Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19 64b66b Receive Sequence For 64-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20 64b66b Transmit Sequence For 64-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21 64b66b Transmit Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22 64b67b Transmit Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23 64b67b Receive Sequence For 32-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24 Initial Receiver Detection Response For Receiver-Not-Present . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 25 Initial Receiver Detection For Receiver-Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26 Subsequent Receiver Detection Where Prior Status Was Receiver-Not-Present . . . . . . . . . . . . . 44
Figure 27 PMA-Bus Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 28 PMA Only Data Path – 80-bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 29 PMA Only Data Path – Less Than or Equal to 40-bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 30 Global-shared Clocking Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 31 Non-Deterministic Interface With FWF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 32 Non-Deterministic Interface Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 33 Non-Deterministic Transceiver Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 34 Deterministic Timing Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 35 Deterministic Transceiver Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 36 Deterministic Transceiver Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 37 Transceiver Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 38 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 39 Spread Spectrum Clocking Modulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 40 Using TXPLL_SSC For Upto Four Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 41 Using TXPLLs For Upto Four Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 42 FPGA Logic For TX Alignment (5 to 8 Lanes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 43 Reference Clock (REFCLK) Interface to Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 44 Typical Jitter Attenuator Application Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 45 Jitter Attenuation TXPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 46 JAPLL Custom Protocol Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 47 Reference Clock Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 48 Rx JA Clock Frequency (XCVR Configurator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 49 Dedicated Transceiver Reference Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 50 REFCLK Input Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 51 MPF100 Transceiver and Transmit PLL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 52 MPF200 and MPF300 Transceiver and Transmit PLL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 53 MPF500 Transceiver and Transmit PLL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 54 PMA_ARST_N Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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Figure 55 PCS Rate Switch between 8b10b and 64b66b Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 56 Transceiver Reference Clock Selection from Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 57 Transceiver Reference Clock Configurator GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 58 Transceiver Reference Clock Mode Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 59 PF_XCVR_REF_CLK With One Single-Ended Input and Single Output Clock . . . . . . . . . . . . . . . 84
Figure 60 PF_XCVR_REF_CLK With Two Single-Ended Input and Two Output Clock . . . . . . . . . . . . . . . . . 84
Figure 61 PF_XCVR_REF_CLK With Differential Input and Single Output Clock . . . . . . . . . . . . . . . . . . . . . 85
Figure 62 PF_XCVR_REF_CLK With Fabric Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 63 Transceiver Transmit PLL Selection from Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 64 Transmit PLL Configurator GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 65 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 66 Fabric Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 67 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 68 Spread Spectrum Clock Generation Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 69 Spread Spectrum Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 70 Enable Dynamic reconfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 71 CLK_125 GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 72 Transceiver Interface Selection From Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 73 Transceiver Interface Configuration GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 74 PMA Mode—Enable CDR Bit-Slip Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 75 XCVR Component With CDR Bit-Slip Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 76 XCVR Component With BMR Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 77 XCVR Component With DRI Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 78 Transceiver with ERM Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 79 PMA Only PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 80 8b10b PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 81 64b66b PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 82 Soft PIPE PCS Example SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 83 Completed Transceiver Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 84 Completed Transceiver Subsystem with ERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 85 Transceiver Modes shown in Transceiver GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 86 Derive Constraints using Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 87 IO Editor GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 88 XCVR Placement Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 89 XCVR Signal Integrity Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 90 Signal Integrity Conditioning Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 91 IO Editor—XCVR View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 92 IO Editor—Signal Integrity View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 93 SmartDebug Signal Integrity GUI Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 94 Loopback Modes—Far-end Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 95 PRBS Self Test Near-End Loopback Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 96 Test Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 97 Eye Monitor Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 98 Example of Optimize DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 99 RTL Simulation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 100 Transceiver Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 101 PF_DRI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 102 Connectivity Between XCVR Interface and PCIe Edge Connector . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 103 Connectivity Between PolarFire Device and JESD204B Interface . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 104 Connectivity Between PolarFire Device to SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 vii
Tables
Table 1 Supported Serial Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2 CDR Lock Mode Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3 Mode of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4 ERM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5 DFE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6 System Registers Affecting 8b10b Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7 8b10b Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8 64b6xb Transmit Data Path Blocks, Fabric to PMA Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9 64b6xb Receive Data Path Blocks, PMA to Fabric Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10 System Registers Affecting 64b6xb Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11 64b66b/64b67b Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12 PIPE Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13 PMA Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14 Clock Region Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15 Transceiver Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16 Transceiver Interface Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18 Transmit PLL Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19 Jitter Attenuation PLL Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 20 XCVR REFCLK Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21 Reference clock input buffer Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 22 PolarFire Transceiver Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 23 Port Crossover between the 8b10b and 64b66b Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 24 System Registers Affecting 8B10B and 64B6xB Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 25 Transceiver Configurator Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 26 Transceiver Reference Clock Configurator GUI Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 27 Transmit PLL Configurator GUI Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 28 Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 29 Transceiver Interface General Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 30 Transceiver Interface PMA Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 31 Transceiver Interface PCS Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 32 Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 33 PCS Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 34 Physical Constraint Instances For XCVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 35 Amplitude and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 36 LOS Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 37 TX Attributes and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 38 RX Attributes and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 39 Transceiver Device Level Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 40 Transceivers Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Revision History
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the current publication.
1.1 Revision 9.0
The following is a summary of the changes in this revision.
• Information about incremental DFE calibration was added. See DFE Calibration, page 12.
• Information about Enhanced Receiver Management, page 16 was updated.
• Information about Transceiver Reference Clock Interface, page 61 was updated.
• Information about spread spectrum was updated. See Table 28, page 90.
• Information about PIPE Port List, page 39 and PMA Port List, page 46 was updated.
• Information about Loss of Signal Detect (LOS), page 9 was added.
• Information about PMA and PCS Resets, page 73 was updated.
• Information about Transceiver Reference Clock Configurator, page 82 was updated.
• Information about Dynamic Reconfiguration Interface, page 124 was updated.
• Information about Jitter Attenuator, page 63 was updated.
• Information about Transceiver Initialization, page 107 was updated.
• Information about Libero Generated Files, page 101 was updated.
1.2 Revision 8.0
The following is a summary of the changes in this revision.
• Information about 8b10b Data Path Interface, page 24, 8b10b Bit and Octet Sequencing, page 25,
and 8b10b System Registers, page 26 was added.
• Information about 64b6xb Data Path Interface, page 30, 64b6xb System Registers, page 32,
64b66b Receiver, page 33, 64b66b Transmit, page 34, 64b67b Transmit, page 35, and 64b67b
Receive, page 35 was added.
• Information about None_DFE (Static DFE) was updated. See Enhanced Receiver Management,
page 16.
• Information about LANE#_CLK_REF port name was added. See Table 7, page 27, Table 11,
page 36, Table 12, page 39, and Table 13, page 46.
• Information about Table 21, page 68 was updated.
• Information about DFE Coefficients, page 104 was added.
• Information about AC/DC Coupled Connection, page 110 was updated.
• Information about Table 39, page 125 was updated.
• Information about Design for Protocols, page 127 and Unused Transceiver Pins, page 129 was
updated.
• Information about Half-Duplex Mode, page 100 was updated.
• Information about Receive Input Buffer, page 8 was updated.
1.3 Revision 7.0
The following is a summary of the changes in this revision.
• Information about physical constraint instances was updated. See Table 34, page 103.
• Information about TX and RX interface clock was updated. See Table 16, page 54.
• Information about Enhanced Receiver Management, page 16 was updated.
1.4 Revision 6.0
The following is a summary of the changes in this revision.
• Information about capability to support switching between two TXPLLs or two CDR REFCLKs via the
DRI interface was added. See Transceiver Interface Configurator, page 91.
• Information about LiteFast was updated. See Table 1, page 4.
• Information about PCS/FPGA Fabric Interface, page 48 was added.

Revision History
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 2
• Information about new latency was updated. See Table 15, page 53.
• Information about Transceiver Data Path Latency, page 53 was added.
• Information about footnote was updated. See Table 21, page 68.
• Information about PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI, page 75 was
added.
• Information about MPF500 Transceiver and Transmit PLL Layout was updated. See Figure 53,
page 72.
• Information about JA PLL settings for each preset was added. See Jitter Attenuator, page 63.
• Information about Transceiver Modes, page 99 was added.
• Information about PMA and PCS Resets, page 73 was updated.
• Information about Custom Protocol Settings, page 65 was added.
• Information about Table 7, page 27, Table 11, page 36, Table 12, page 39, and Table 13, page 46
was updated.
1.5 Revision 5.0
The following is a summary of the changes in this revision.
• Information about SATA sub-mode was removed from PIPE, page 38.
• Information about RX_IDLE was updated. See Table 7, page 27, Table 11, page 36, and Table 13,
page 46.
• Information about LANE#_TX_WCLK input pin was added. See PCS/FPGA Fabric Interface,
page 48.
• Information about Transceiver Clock Regions, page 52 was added.
• Information about Reference Clock Disruptions, page 69 was added.
• Information about Jitter Attenuator, page 63 was added.
• Information about REFCLK input pins were updated. See Reference Clock Input Pins, page 68.
• Information about PMA and PCS Resets, page 73 was added.
• Information about the interface clocks for the Transceiver PLL was updated. See Table 32, page 94.
• Information about Enhanced Receiver Management, page 16 was added.
• Information about PIPE Interface Compliance Exceptions, page 43 was added.
1.6 Revision 4.0
The following is a summary of the changes in this revision.
• Updated the document for Libero® SoC PolarFire v2.3 release.
• Added information about burst mode receiver, see CDR Options, page 10.
• Added information about the alignment of transmit lanes, see Transmit Lane Alignment, page 58.
• Added information about Tx loss insertion, see Tx Insertion Loss, page 109.
• Added a footnote under Table 34, page 103 that describes how to disable the ODT value for the
differential REFCLK.
• Added a footnote under Table 32, page 94 that describes the minimum pulse width for the PMA
reset signal.
1.7 Revision 3.0
The following is a summary of the changes in this revision.
• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, page 23,
64b66b/64b67b, page 30, and PMA Only, page 44.
• Information about signal integrity was added. See Signal Integrity Conditioning, page 108.
• Information about Bit-slip was updated. See Bit Slip, page 11. 8b10b does not support bit slip
mechanism.
1.8 Revision 2.0
The following is a summary of the changes in this revision.
• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, page 23,
64b66b/64b67b, page 30, and PMA Only, page 44.

Revision History
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 3
• Information about Word Alignment was added as sub-section to 8b10b, page 23. See Word
Alignment (Byte Boundary or Comma Detect), page 24.
• Updated Figure 52, page 71 and Figure 53, page 72.
• Information about LANE#_RX_VAL port name description was updated. See Table 4, page 16,
Table 7, page 27, and Table 11, page 36.
1.9 Revision 1.0
The first publication of this document.