Microsemi SmartFusion2 MSS User manual

SmartFusion2 MSS
DDR Controller Configuration
Libero SoC v11.6 and later

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Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 MDDR Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 MDDR Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MSS DDR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Importing DDR Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Exporting DDR Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MSS DDR Configuration Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
A Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Introduction
The SmartFusion2 MSS has an embedded DDR controller. This DDR controller is intended to control an
off-chip DDR memory. The MDDR controller can be accessed from the MSS as well as from the FPGA
fabric. In addition, the DDR controller can also be bypassed, providing an additional interface to the
FPGA fabric (Soft Controller Mode (SMC)).
To fully configure the MSS DDR controller, you must:
1. Select the datapath using the MDDR Configurator.
2. Set the register values for the DDR controller registers.
3. Select the DDR memory clock frequencies and FPGA fabric to MDDR clock ratio (if needed)
using the MSS CCC Configurator.
4. Connect the controller’s APB configuration interface as defined by the Peripheral Initialization
solution. For the MDDR Initialization circuitry built by System Builder, refer to the "MSS DDR
Configuration Path" on page 13 and Figure 2-7.
You can also build your own initialization circuitry using standalone (not by System Builder)
Peripheral Initialization. Refer to the SmartFusion2 Standalone Peripheral Initialization User
Guide.

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1 – MDDR Configurator
The MDDR Configurator is used to configure the overall datapath and the external DDR Memory
Parameters for the MSS DDR controller.
The General tab sets your Memory and Fabric Interface settings (Figure 1-1).
Memory Settings
Enter the DDR Memory Settling Time. This is the time the DDR memory requires to initialize. The default
value is 200 us. Refer to your DDR Memory Data Sheet for the correct value to enter.
Use Memory Settings to configure your memory options in the MDDR.
•Memory Type - LPDDR, DDR2, or DDR3
•Data Width - 32-bit, 16-bit or 8-bit
•SECDED Enabled ECC - ON or OFF
•Arbitration Scheme - Type-0, Type -1, Type-2,Type-3
•Highest Priority ID - Valid values are from 0 through 15
•Address Width (bits) - Refer to your DDR Memory Data Sheet for the number of row, bank, and
column address bits for the LPDDR/DDR2/DDR3 memory you use. select the pull-down menu to
choose the correct value for rows/banks/columns as per the data sheet of the LPDDR/DDR2/
DDR3 memory.
Note: The number in the pull-down list refers to the number of Address bits, not the absolute number of
rows/banks/columns. For example, if your DDR memory has 4 banks, select 2 (22=4) for banks. If
your DDR memory has 8 banks, select 3 (23=8) for banks.
Figure 1-1 • MDDR Configurator Overview

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Fabric Interface Settings
By default, the hard Cortex-M3 processor is set up to access the DDR Controller. You can also allow a
fabric Master to access the DDR Controller by enabling the Fabric Interface Setting checkbox. In this
case, you can choose one of the following options:
•Use an AXI Interface - The fabric Master accesses the DDR Controller through a 64-bit AXI
interface.
•Use a Single AHBLite Interface - The fabric Master accesses the DDR Controller through a
single 32-bit AHB interface.
•Use two AHBLite Interfaces - Two fabric Masters access the DDR Controller using two 32-bit
AHB interfaces.
The configuration view (Figure 1-1) updates according to your Fabric Interface selection.
I/O Drive Strength (DDR2 and DDR3 only)
Select one of the following drive strengths for your DDR I/Os:
• Half Drive Strength
• Full Drive Strength
Libero SoC sets the DDR I/O Standard for your MDDR system based on your DDR Memory type and I/O
Drive Strength (as shown in Table 1-1).
IO Standard (LPDDR only)
Select one of the following options:
• LVCMOS18 (Lowest Power) for LVCMOS 1.8V IO standard. Used in typical LPDDR1
applications.
• LPDDRI Note: Before you choose this standard, make sure that your board supports this
standard. You must use this option when targeting the M2S-EVAL-KIT or the SF2-STARTER-KIT
boards. LPDDRI IO standards require that a IMP_CALIB resistor is installed on the board.
IO Calibration (LPDDR only)
Choose one of the following options when using LVCMOS18 IO standard:
•On
• Off (Typical)
Calibration ON and OFF optionally controls the use of an IO calibration block that calibrates the IO
drivers to an external resistor. When OFF, the device uses a preset IO driver adjustment.
When ON, this requires a 150-ohm IMP_CALIB resistor to be installed on the PCB.
This is used to calibrate the IO to the PCB characteristics. However, when set to ON, a resistor needs to
be installed or the memory controller will not initialize.
For more information, refer to AC393-SmartFusion2 and IGLOO2 Board Design Guidelines Application
Note and the SmartFusion2 SoC FPGA High Speed DDR Interfaces User Guide.
Table 1-1 • I/O Drive Strength and DDR Memory Type
DDR Memory Type Half Strength Drive Full Strength Drive
DDR3 SSTL15I SSTL15II
DDR2 SSTL18I SSTL18II
LPDDR LPDRI LPDRII

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2 – MDDR Controller Configuration
When you use the MSS DDR Controller to access an external DDR Memory, the DDR Controller must be
configured at runtime. This is done by writing configuration data to dedicated DDR controller
configuration registers. This configuration data is dependent on the characteristics of the external DDR
memory and your application. This section describes how to enter these configuration parameters in the
MSS DDR controller configurator and how the configuration data is managed as part of the overall
Peripheral Initialization solution.
MSS DDR Control Registers
The MSS DDR Controller has a set of registers that need to be configured at runtime. The configuration
values for these registers represent different parameters, such as DDR mode, PHY width, burst mode,
and ECC. For complete details about the DDR controller configuration registers, refer to the
SmartFusion2 SoC FPGA High Speed DDR Interfaces User's Guide.
MDDR Registers Configuration
Use the Memory Initialization (Figure 2-1, Figure 2-2, and Figure 2-3) and Memory Timing (Figure 2-4)
tabs to enter parameters that correspond to your DDR Memory and application. Values you enter in
these tabs are automatically translated to the appropriate register values. When you click a specific
parameter, its corresponding register is described in the Register Description pane (lower portion in
Figure 1-1 on page 4).
Memory Initialization
The Memory Initialization tab allows you to configure the ways you want your LPDDR/DDR2/DDR3
memories initialized. The menu and options available in the Memory Initialization tab vary with the type of
DDR memory (LPDDR/DDR2/DDR3) you use.
Refer to your DDR Memory Data Sheet when you configure the options.
When you change or enter a value, the Register Description pane gives you the register name and
register value that is updated. Invalid values are flagged as warnings.
Figure 2-1, Figure 2-2, and Figure 2-3 show the Initialization tab for LPDDR, DDR2 and DDR3,
respectively.

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•Timing Mode - Select 1T or 2T Timing mode. In 1T (the default mode), the DDR controller can
issue a new command on every clock cycle. In 2T timing mode, the DDR controller holds the
address and command bus valid for two clock cycles. This reduces the efficiency of the bus to
one command per two clocks, but it doubles the amount of setup and hold time.
•Partial-Array Self Refresh (LPDDR only). This feature is for power saving for the LPDDR.
Select one of the following for the controller to refresh the amount of memory during a self
refresh:
– Full array: Banks 0, 1,2, and 3
– Half array: Banks 0 and 1
– Quarter array: Bank 0
– One-eighth array: Bank 0 with row address MSB=0
– One-sixteenth array: Bank 0 with row address MSB and MSB-1 both equal to 0.
For all other options, refer to your DDR Memory Data Sheet when you configure the options.
Figure 2-1 • MDDR Configuration—Memory Initialization Parameters (LPDDR)

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Figure 2-2 • MDDR Configuration—Memory Initialization Parameters (DDR2)

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Memory Timing
This tab allows you to configure the Memory Timing parameters. Refer to the Data Sheet of your LPDDR/
DDR2/DDR3 memory when configuring the Memory Timing parameters.
When you change or enter a value, the Register Description pane gives you the register name and
register value that is updated. Invalid values are flagged as warnings.
Figure 2-3 • MDDR Configuration—Memory Initialization Paramet ers (DDR3)

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Importing DDR Configuration Files
In addition to entering DDR Memory parameters using the Memory Initialization and Timing tabs, you can
import DDR register values from a file. To do so, click the Import Configuration button and navigate to
the text file containing DDR register names and values. Figure 2-5 shows the import configuration
syntax.
Figure 2-4 • MDDR Configuration Memory Timing Tab
Figure 2-5 • DDR Register Configuration File Syntax