MicroSys miriac MPX-LS1046A User manual

miriac MPX-LS1046A
User Manual (HW Revision 5)
V 5.0

Table of Contents
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© MicroSys Electronics GmbH 2017-2023
Table of Contents
1General Notes..............................................3
1.1 Warranty........................................................3
1.2 Links..............................................................3
1.3 Liability..........................................................3
1.4 Offer to Provide Source Code of Certain
Software........................................................4
1.5 Symbols, Conventions and Abbreviations.....5
1.5.1 Symbols ........................................................5
1.5.2 Conventions ..................................................5
1.6 Safety and Handling Precautions..................6
2Short Description........................................7
3System Description.....................................8
3.1 Block Diagram...............................................8
3.2 System Components.....................................8
3.3 Power Consumption......................................9
3.4 Cooling........................................................10
3.5 Ordering Information ...................................10
4Technical Description...............................11
4.1 Pinouts........................................................11
4.1.1 Module Connector –Bottom Pins [ST1]......12
4.1.2 Module Connector –Top Pins [ST1] ...........18
4.1.3 Programming Connector [ST2]....................23
4.2 Reset Structure ...........................................24
4.3 Power Structure...........................................26
4.4 Clock Structure............................................28
4.5 Boot Sources...............................................29
4.6 LEDs ...........................................................30
4.7 RTC (Real-Time Clock)...............................31
4.8 Temperature sensor....................................32
4.9 Power-up/down behaviour...........................33
4.10 GPIO Expander (2 GByte NAND version
only) ............................................................33
4.11 Interface Description ...................................35
4.11.1 GPIOs .........................................................35
4.11.2 JTAG/COP ..................................................36
4.11.3 I2C...............................................................37
4.11.4 QSPI............................................................39
4.11.5 SPI...............................................................40
4.11.6 NAND ..........................................................41
4.11.7 USB.............................................................42
4.11.8 UART...........................................................45
4.11.9 eSDHC ........................................................47
4.11.10 SerDes.........................................................52
4.11.11 RGMII..........................................................54
4.11.12 10G Mode....................................................58
5Mechanical Description.............................59
5.1 Edge Finger.................................................59
5.2 Board Outline...............................................62
5.3 Height..........................................................63
5.4 Thickness ....................................................63
5.5 Top Side Component Layout.......................64
5.6 Bottom Side Component Layout..................65
6Software .....................................................66
6.1 U-Boot .........................................................66
6.2 Operating System........................................66
7Safety Requirements And Protective
Regulations................................................67
7.1 EMC ............................................................67
7.2 ESD.............................................................67
7.3 Reliability.....................................................67
7.4 Climatic conditions.......................................68
7.5 RoHS...........................................................68
8General notes.............................................69
9Appendix....................................................70
9.1 Acronyms.....................................................70
9.2 Table of Figures...........................................71
9.3 Table of Tables............................................72
10 4.1History...................................................74

General Notes 1
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© MicroSys Electronics GmbH 2017-2023
1 General Notes
Copyright © MicroSys Electronics GmbH 2017-2023
All rights reserved. All rights in any information which appears in this document
belong to MicroSys Electronics GmbH or our licensors. You may copy the
information in this manual for your personal, non-commercial use.
Copyrighted products are not explicitly indicated in this manual. The absence of the
copyright (©) and trademark (TM or ®) symbols does not imply that a product is not
protected. Additionally, registered patents and trademarks are similarly not
expressly indicated in this manual.
1.1 Warranty
To the extent permissible by applicable law all information in this document is
provided without warranty of any kind, whether expressed or implied, including but
not limited to any implied warranty of satisfactory quality or fitness for a particular
purpose, or of non-infringement of any third party’s rights. We try to keep this
document accurate and up-to-date but we do not make any warranty or
representation about such matters. In particular we assume no liability or
responsibility for any errors or omissions in this document.
MicroSys Electronics GmbH neither gives any guarantee nor accepts any liability
whatsoever for consequential damages resulting from the use of this manual or its
associated product.
MicroSys Electronics GmbH further reserves the right to alter the layout and/or
design of the hardware without prior notification and accepts no liability for doing
so.
1.2 Links
We make no warranty about any other sites that are linked to or from this
document, whether we authorise such links or not.
1.3 Liability
To the extent permissible by applicable law, in no circumstance, including (but not
limited to) negligence, shall we be liable for your reliance on any information in this
document, nor shall we be liable for any direct, incidental, special, consequential,
indirect or punitive damages nor any loss of profit that result from the use of, or the
inability to use, this document or any material on any site linked to this document
even if we have been advised of the possibility of such damage. In no event shall
our liability to you for all damages, losses and causes of action whatsoever,
whether in contract, tort (including but not limited to negligence) or otherwise
exceed the amount, if any, paid by you to us for gaining access to this document.
MicroSys Electronics GmbH
Muehlweg 1
D-82054 Sauerlach
Germany
Phone: [phone]
Fax: [phone]

General Notes 1
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1.4 Offer to Provide Source Code of Certain
Software
This product contains copyrighted software that is licensed under the General
Public License (“GPL”) and under the Lesser General Public License Version
(“LGPL”). The GPL and LGPL licensed code in this product is distributed without
any warranty. Copies of these licenses are included in this product.
You may obtain the complete corresponding source code (as defined in the GPL)
for the GPL Software, and/or the complete corresponding source code of the LGPL
Software (with the complete machine-readable “work that uses the Library”) for a
period of three years after our last shipment of the product including the GPL
Software and/or LGPL Software, which will be no earlier than December 1, 2010,
for the cost of reproduction and shipment, which is dependent on the preferred
carrier and the location where you want to have it shipped to, by sending a request
to:
MicroSys Electronics GmbH
Muehlweg 1
D-82054 Sauerlach
Germany
In your request please provide the product name and version for which you wish to
obtain the corresponding source code and your contact details so that we can
coordinate the terms and cost of shipment with you.
The source code will be distributed WITHOUT ANY WARRANTY and licensed
under the same license as the corresponding binary/object code.
This offer is valid to anyone in receipt of this information.
MicroSys Electronics GmbH is eager to duly provide complete source code as
required under various Free Open Source Software licenses. If however you
encounter any problems in obtaining the full corresponding source code we would
be much obliged if you give us a notification to the email address
[email protected], stating the product and describing the problem (please do NOT
send large attachments such as source code archives etc to this email address)

General Notes 1
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1.5 Symbols, Conventions and Abbreviations
1.5.1 Symbols
Throughout this document, the following symbols will be used:
Information marked with this symbol MUST be obeyed to avoid the risk
of severe injury, health danger, or major destruction of the unit and its
environment
Information marked with this symbol MUST be obeyed to avoid the risk
of possible injury, permanent damage or malfunction of the unit.
Information marked with this symbol gives important hints upon details
of this manual, or in order to get the best use out of the product and its
features.
Table 1-1 Symbols
1.5.2 Conventions
Symbol
explanation
#
denotes a low active signal
←
denotes the signal flow in the shown direction
→
denotes the signal flow in the shown direction
↔
denotes the signal flow in both directions
→
denotes the signal flow in the shown direction with additional logic /
additional ICs in the signal path
I/O
denotes a bidirectional pin
Input
denotes an input pin
matched
denotes the according signal to be routed impedance controlled and
length matched
Output
denotes an output pin
Pin 1
refers to the numeric pin of a component package
Pin a1
refers to the array position of a pin within a component package
XXX-
denotes the negative signal of a differential pair
XXX+
denotes the positive signal of a differential pair
XXX
denotes an optional not mounted or fitted part
Table 1-2 Conventions

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1.6 Safety and Handling Precautions
DO NOT exceed the rated maximum values for the power
supply! This may result in severe permanent damage to
the unit, as well as possible serious injury.
ALWAYS keep the unit dry, clean and free of foreign
objects. Otherwise, irreparable damage may occur.
Parts of the unit may become hot during operation. Take
care not to touch any parts of the circuitry during
operation to avoid burns, and operate the unit in a well-
ventilated location. Provide an appropriate cooling
solution as required.
ALWAYS take care of ESD-safe handling!
Many pins on the module connector are directly
connected to the CPU or other ESD sensitive devices.
Make or break ANY connections ONLY while the unit is
switched OFF.
Otherwise, permanent damage to the unit may occur,
which is not covered by warranty.
There is no separate SHIELD connection.
The module’s mounting holes are not connected to GND
Take this into account when handling and mounting the
unit.
Table 1-3 Safety and Handling Precautions

Short Description 2
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2 Short Description
The miriac MPX-LS1046A is a member of the MPX module family based on NXP’s
QorIQ® Layerscape LS1046A Multicore Communications Processor.
MicroSys Electronics GmbH offers a Starterkit which provides the key features of
the module. The customer can:
■…evaluate the basic concept of the MPX2 standard
■…test the operation of the MPX-LS1046A module
■…evaluate the main interfaces of the LS1046A CPU
■…test the provided software
■…start developing

System Description 3
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3 System Description
3.1 Block Diagram
3.2 System Components
■QorIQ Layerscape processor LS1046A or LS1026A
■Microcontroller as monitoring and supervising unit with power management
and configuration tasks
■DDR4 SDRAM
■Clock Generators for CPU and interface clocks
■QSPI flash as boot or storage device
■NAND flash as storage device
■I²C EEPROM
■I²C temperature sensor
■I²C RTC
■Voltage regulators for onboard generated voltages
Figure 3-1 Block Diagram

System Description 3
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3.3 Power Consumption
The MPX-LS1046A can be supplied by a single input power rail ranging from 5V to
12V. The efficiency of the voltage regulators differs in that range. Thus for best
overall efficiency choose 5V input voltage if possible. The typical power
consumption values for the module are determined on a CRX05 carrierboard
running U-boot (idle) at room temperature (4 cores @ 1600MHz / 600MHz CCB
clock) with 2GByte of DDR4 memory + ECC (1600 MHz) and passive cooling:
■5V input: ~6,5 Watt
■12V input: ~7,2 Watt
The consumed power is distributed among the following components based on
estimated values:
■CPU: ~4-6 Watt
■DDR4 + ECC: ~1-1,5 Watt
■QSPI Flash: ~0,05 Watt
■NAND Flash: ~0,05 Watt
■Onboard clock generator: ~0,25 Watt
■Temperature Sensor, RTC, EEPROM: ~0,025 Watt
■Regulator efficiency: ~80-90%
The typical power consumption values for the module over junction temperature
are determined on a CRX05 carrier running Linux. Input voltage 12V with 4 times
RJ45 1G Ethernet connected as well as console over USB. The module is supplied
by 5V.
Linux Stress: stressapptest (https://github.com/stressapptest/stressapptest) (start
parameters: -W -s 60, all cores)
Linux Idle: command prompt
Tj[°C] from
internal probe
Power dissipation idle [W]
Power dissipation stress [W]
15
7,3
12,4
40
8,0
13,3
60
9,0
14,7
80
10,5
16,4
Table 3-1 Typical power consumption running module with Linux

System Description 3
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3.4 Cooling
In chapter 3.3 the power consumption of the MPX-LS1046A module was specified.
With this information a cooling method needs to be designed in coordination with
the final use case. If desired, MicroSys Electronics GmbH can support you with
your cooling concept. Please ask your sales representative or send an email
inquiry to [e-mail].
Commercial temperature grade (0/+70° C) variants:
Component
Temperature
(max.)
Description
CPU
105° C
Junction Temperature
DDR
85° C
Case Temperature
Core Regulator
150° C
Junction Temperature
Table 3-2 Commercial grade variants: maximum temperature
Industrial temperature grade (-40/+85° C) variants:
Component
Temperature
(max.)
Description
CPU
105° C
Junction Temperature
DDR
95° C
Case Temperature
Core Regulator
150° C
Junction Temperature
Table 3-3 Industrial grade variants: maximum temperature
3.5 Ordering Information
Ordering information can be found on the website
https://www.microsys.de/de/products/system-on-modules/arm-architecture/miriac-
mpx-ls1046a/
or contact your local sales representative.

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4 Technical Description
4.1 Pinouts
The following table gives an overview of the 314 pins of the module’s edge finger.
For a detailed connector description see chapter 5.1. The pins will be described in
chapter 4.11 and the following sections.
Hardware Revision 3 added four additional pins named “TK1”, “TK2”, “BK1” and
“BK2”.
In Hardware Revision 1 and 2 those pins were “KEY” pins which did not carry any
signals.
Please note that the pinout has not been shifted!
The signal direction is from the module’s view. For example JTDO (pin B104) is an
output from the module and an input to peripheral devices on the carrierboard.

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4.1.1 Module Connector –Bottom Pins [ST1]
The following pinout is specific for the MPX-LS1046A module and to large parts
common for most of the MPX modules.
Nevertheless, different modules do not claim to be pin compatible. Individual modules
may have deviating assignments for some functions, whereas power and ground are
always assigned to the same pins.
Pin
Signal
I/O
Group
Power Rail
B1
n.c.
O
Quicc Engine
3,3V Level
B2
GND
Power
Ground
B3
GPIO1_28
I/O
Quicc Engine
3,3V Level
B4
GPIO1_30
I/O
Quicc Engine
3,3V Level
B5
GPIO1_23
I/O
Quicc Engine
3,3V Level
B6
GPIO1_29
I/O
Quicc Engine
3,3V Level
B7
GPIO4_13
I/O
Quicc Engine
3,3V Level
B8
GND
Power
Ground
B9
GPIO1_24
I/O
Quicc Engine
3,3V Level
BK1
n.c.
BK2
10G-MODE#
I
Management
3,3V Level
B10
GPIO1_26
I/O
Quicc Engine
3,3V Level
B11
GPIO1_27
I/O
Quicc Engine
3,3V Level
B12
GPIO1_25
I/O
Quicc Engine
3,3V Level
B13
GPIO4_12
I/O
Quicc Engine
3,3V Level
B14
GND
Power
Ground
B15
n.c.
O
Quicc Engine
3,3V Level
B16
n.c.
O
Quicc Engine
3,3V Level
B17
GND
Power
Ground
B18
n.c.
O
Quicc Engine
3,3V Level
B19
n.c.
O
Quicc Engine
3,3V Level
B20
GND
Power
Ground
B21
n.c.
O
Quicc Engine
3,3V Level
B22
n.c.
O
Quicc Engine
3,3V Level
B23
GND
Power
Ground

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Pin
Signal
I/O
Group
Power Rail
B24
n.c.
I/O
TDM / DMA
3,3V Level
B25
n.c.
I/O
TDM / DMA
3,3V Level
B26
n.c.
I/O
TDM / DMA
3,3V Level
B27
n.c.
I/O
TDM / DMA
3,3V Level
B28
GND
Power
Ground
B29
n.c.
I/O
TDM / DMA
3,3V Level
B30
n.c.
I/O
TDM / DMA
3,3V Level
B31
GND
Power
Ground
B32
UART2-RXD
I
UART2
3,3V Level
B33
UART2-TXD
O
UART2
3,3V Level
B34
UART2-CTS#
I
UART2
3,3V Level
B35
UART2-RTS#
O
UART2
3,3V Level
B36
GND
Power
Ground
B37
UART1-RXD
I
UART
3,3V Level
B38
UART1-TXD
O
UART
3,3V Level
B39
UART1-CTS#
I
UART
3,3V Level
B40
UART1-RTS#
O
UART
3,3V Level
B41
GND
Power
Ground
B42
n.c.
O
IEEE1588
1,8V Level
B43
n.c.
I
IEEE1588
1,8V Level
B44
n.c.
O
IEEE1588
1,8V Level
B45
n.c.
O
IEEE1588
1,8V Level
B46
n.c.
I
IEEE1588
1,8V Level
B47
n.c.
I
IEEE1588
1,8V Level
B48
n.c.
O
IEEE1588
1,8V Level
B49
n.c.
O
IEEE1588
1,8V Level
B50
GND
Power
Ground
B51
n.c.
O
Display
3,3V Level
B52
n.c.
O
Display
3,3V Level
B53
n.c.
O
Display
3,3V Level
B54
n.c.
O
Display
3,3V Level

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Pin
Signal
I/O
Group
Power Rail
B55
GND
Power
Ground
B56
n.c.
O
Display
3,3V Level
B57
n.c.
O
Display
3,3V Level
B58
n.c.
O
Display
3,3V Level
B59
n.c.
O
Display
3,3V Level
B60
n.c.
O
Display
3,3V Level
B61
n.c.
O
Display
3,3V Level
B62
n.c.
O
Display
3,3V Level
B63
n.c.
O
Display
3,3V Level
B64
n.c.
O
Display
3,3V Level
B65
n.c.
O
Display
3,3V Level
B66
n.c.
O
Display
3,3V Level
B67
n.c.
O
Display
3,3V Level
B68
GND
Power
Ground
B69
SPI-CLK
O
SPI
3,3V Level
B70
SPI-CS0#
O
SPI
3,3V Level
B71
SPI-MOSI
O
SPI
3,3V Level
B72
SPI-MISO
I
SPI
3,3V Level
B73
GND
Power
Ground
B74
I2C2-SDA
I/O
I2C
3,3V Level
B75
I2C2-SCL
O
I2C
3,3V Level
B76
GND
Power
Ground
B77
I2C1-SDA
I/O
I2C
3,3V Level
B78
I2C1-SCL
O
I2C
3,3V Level
B79
GND
Power
Ground
B80
VBAT
Power
Power
3,0V
B81
VREF-SDC
Power
Power
Reference volt-
age for SD-Card
Interface
B82
GND
Power
Ground
B83
MDC2
O
EC
Management2
1,2V Level
B84
MDIO2
I/O
EC
Management2
1,2V Level
B85
GND
Power
Ground

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Pin
Signal
I/O
Group
Power Rail
B86
MDC1
O
EC
Management1
VREF-MII
B87
MDIO1
I/O
EC
Management1
VREF-MII
B88
GND
Power
Ground
B89
SDC-WP
O
SDHC
3,3V Level
B90
SDC-CD#
I
SDHC
3,3V Level
B91
SDC-D7 / SPI-CS3#
I/O
eMMC / SPI
eMMC: 1,8V
SPI: 3,3V
B92
SDC-D6 / SPI-CS2#
I/O
eMMC / SPI
eMMC: 1,8V
SPI: 3,3V
B93
SDC-D5 / SPI-CS1#
I/O
eMMC / SPI
eMMC: 1,8V
SPI: 3,3V
B94
SDC-D4
I/O
eMMC
1,8V Level
B95
SDC-D3
I/O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B96
SDC-D2
I/O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B97
SDC-D1
I/O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B98
SDC-D0
I/O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B99
SDC-CMD
I/O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B100
SDC-CLK
O
eMMC / SDHC
eMMC: 1,8V
SDC: 3,3V
B101
GND
Power
Ground
B102
JTMS
I
JTAG
1,8V Level
B103
JTDI
I
JTAG
1,8V Level
B104
JTDO
O
JTAG
1,8V Level
B105
JTCK
I
JTAG
1,8V Level
B106
COP-TRST#
O
JTAG / COP
1,8V Level
B107
GND
Power
B108
n.c.
I
COP
1,8V Level
B109
COP-CKSTPO#
O
COP
1,8V Level
B110
COP-PRST#
O
COP
1,8V Level
B111
MCU-HRST#
O
COP
1,8V Level
B112
GND
Power
Ground
B113
DBG-RXD
I
Debug
1,8V Level

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Pin
Signal
I/O
Group
Power Rail
B114
DBG-TXD
O
Debug
1,8V Level
B115
GND
Power
Ground
B116
GPIO1
I/O
GPIO
1,8V Level
B117
GPIO2
I/O
GPIO
1,8V Level
B118
WDOG-TRIG#
I/O
GPIO
1,8V Level
B119
GPIO4
I/O
GPIO
1,8V Level
B120
GPIO5
I/O
GPIO
1,8V Level
B121
GPIO6
I/O
GPIO
1,8V Level
B122
GPIO7
I/O
GPIO
1,8V Level
B123
GPIO8
I/O
GPIO
1,8V Level
B124
GND
Power
Ground
B125
USB2-ID
Analog
USB2.0
1,8V Level
B126
USB2-OC
I
USB2.0
3,3V Level
B127
USB2-EN
O
USB2.0
3,3V Level
B128
USB2-VBUS
I
USB2.0
5V sense
B129
GND
Power
Ground
B130
USB1-ID
Analog
USB2.0
1,8V Level
B131
USB1-OC
I
USB2.0
3,3V Level
B132
USB1-EN
O
USB2.0
3,3V Level
B133
USB1-VBUS
I
USB2.0
5V sense
B134
GND
Power
Ground
B135
USB3-ID
Analog
USB2.0
1,8V Level
B136
USB3-OC
I
USB2.0
3,3V Level
B137
USB3-EN
O
USB2.0
3,3V Level
B138
USB3-VBUS
I
USB2.0
5V sense
B139
GND
Power
Ground
B140
GND
Power
Ground
B141
GND
Power
Ground
B142
GND
Power
Ground
B143
GND
Power
Ground
B144
GND
Power
Ground

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Pin
Signal
I/O
Group
Power Rail
B145
GND
Power
Ground
B146
GND
Power
Ground
B147
GND
Power
Ground
B148
VCC
Power
5V (-5%) up to
12V (+5%)
B149
VCC
Power
5V (-5%) up to
12V (+5%)
B150
VCC
Power
5V (-5%) up to
12V (+5%)
B151
VCC
Power
5V (-5%) up to
12V (+5%)
B152
VCC
Power
5V (-5%) up to
12V (+5%)
B153
VCC
Power
5V (-5%) up to
12V (+5%)
B154
VCC
Power
5V (-5%) up to
12V (+5%)
B155
VCC
Power
5V (-5%) up to
12V (+5%)
B156
VCC
Power
5V (-5%) up to
12V (+5%)
Table 4-1 Module connector: Bottom pins

Technical Description 4
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© MicroSys Electronics GmbH 2017-2023
4.1.2 Module Connector –Top Pins [ST1]
The following pinout is specific for the MPX-LS1046A module and to large parts
common for most of the MPX modules.
Nevertheless, different modules do not claim to be pin compatible. Individual modules
may have deviating assignments for some functions, whereas power and ground are
always assigned to the same pins.
Pin
Signal
I/O
Group
Power Rail
T1
GND
Power
Ground
T2
RX7+
I
Serdes
T3
RX7-
I
Serdes
T4
GND
Power
Ground
T5
TX7+
O
Serdes
T6
TX7-
O
Serdes
T7
GND
Power
Ground
T8
RX6+
I
Serdes
T9
RX6-
I
Serdes
TK1
TBSCAN_EN#
I
JTAG
1,8V Level
TK2
VCC_FUSE
Power
1,8V
T10
GND
Power
Ground
T11
TX6+
O
Serdes
T12
TX6-
O
Serdes
T13
GND
Power
Ground
T14
RX5+
I
Serdes
T15
RX5-
I
Serdes
T16
GND
Power
Ground
T17
TX5+
O
Serdes
T18
TX5-
O
Serdes
T19
GND
Power
Ground
T20
RX4+
I
Serdes
T21
RX4-
I
Serdes
T22
GND
Power
Ground
T23
TX4+
O
Serdes
T24
TX4-
O
Serdes
T25
GND
Power
Ground
T26
RX3+
I
Serdes
T27
RX3-
I
Serdes

Technical Description 4
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© MicroSys Electronics GmbH 2017-2023
Pin
Signal
I/O
Group
Power Rail
T28
GND
Power
Ground
T29
TX3+
O
Serdes
T30
TX3-
O
Serdes
T31
GND
Power
Ground
T32
RX2+
I
Serdes
T33
RX2-
I
Serdes
T34
GND
Power
Ground
T35
TX2+
O
Serdes
T36
TX2-
O
Serdes
T37
GND
Power
Ground
T38
RX1+
I
Serdes
T39
RX1-
I
Serdes
T40
GND
Power
Ground
T41
TX1+
O
Serdes
T42
TX1-
O
Serdes
T43
GND
Power
Ground
T44
RX0+
I
Serdes
T45
RX0-
I
Serdes
T46
GND
Power
Ground
T47
TX0+
O
Serdes
T48
TX0-
O
Serdes
T49
GND
Power
Ground
T50
CLK1+
O
Serdes
T51
CLK1-
O
Serdes
T52
GND
Power
Ground
T53
n.c.
O
Serdes
T54
n.c.
O
Serdes
T55
GND
Power
Ground
T56
MII2-TXCTL
O
RGMII2
VREF-MII
T57
n.c.
I/O
-
VREF-MII
T58
GND
Power
Ground
T59
MII2-TXD0
O
RGMII2
VREF-MII
T60
MII2-TXD1
O
RGMII2
VREF-MII
T61
GND
Power
Ground
T62
MII2-TXD2
O
RGMII2
VREF-MII
T63
MII2-TXD3
O
RGMII2
VREF-MII

Technical Description 4
miriac MPX-LS1046A User Manual
V 5.0
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© MicroSys Electronics GmbH 2017-2023
Pin
Signal
I/O
Group
Power Rail
T64
GND
Power
Ground
T65
MII2-TCLK
O
RGMII2
VREF-MII
T66
MII2-RXCTL
I
RGMII2
VREF-MII
T67
GND
Power
Ground
T68
MII2-RXD0
I
RGMII2
VREF-MII
T69
MII2-RXD1
I
RGMII2
VREF-MII
T70
GND
Power
Ground
T71
MII2-RXD2
I
RGMII2
VREF-MII
T72
MII2-RXD3
I
RGMII2
VREF-MII
T73
GND
Power
Ground
T74
n.c.
I
-
VREF-MII
T75
MII2-RCLK
I
RGMII2
VREF-MII
T76
GND
Power
Ground
T77
MII2-CLK125M
I
RGMII2
VREF-MII
T78
n.c.
O/I
RGMII2
VREF-MII
T79
GND
Power
Ground
T80
VREF-MII
Power
Reference Volt-
age for MII-
Interface
T81
GND
Power
Ground
T82
n.c.
I
RGMII1
VREF-MII
T83
MII-CLK125M
I
RGMII1
VREF-MII
T84
GND
Power
Ground
T85
n.c
I
-
VREF-MII
T86
MII-RCLK
I
RGMII1
VREF-MII
T87
GND
Power
Ground
T88
MII-RXD0
I
RGMII1
VREF-MII
T89
MII-RXD1
I
RGMII1
VREF-MII
T90
GND
Power
Ground
T91
MII-RXD2
I
RGMII1
VREF-MII
T92
MII-RXD3
I
RGMII1
VREF-MII
T93
GND
Power
Ground
T94
MII-TCLK
O
RGMII1
VREF-MII
T95
MII-RXCTL
I
RGMII1
VREF-MII
T96
GND
Power
Ground
T97
MII-TXD0
O
RGMII1
VREF-MII
T98
MII-TXD1
O
RGMII1
VREF-MII
T99
GND
Power
Ground