Analog Devices ADSP-TS101 TigerSHARC Application guide

a
ADSP-TS101 TigerSHARC®Processor
Hardware Reference
Revision 1.1, May 2004
Part Number
82-001996-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
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Copyright Information
© 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, EZ-ICE, SHARC, TigerSHARC, and the
TigerSHARC logo are registered trademarks of Analog Devices, Inc.
VisualDSP++, Static Superscalar, and EZ-KIT Lite are trademarks of
Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
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CONTENTS
PREFACE
Purpose of This Manual ................................................................. xix
Intended Audience ......................................................................... xix
Manual Contents ............................................................................ xx
Additional Literature ..................................................................... xxii
What’s New in This Manual .......................................................... xxii
Technical or Customer Support ..................................................... xxii
Processor Family ......................................................................... xxiii
Product Information ................................................................... xxiii
DSP Product Information ...................................................... xxiii
Product Related Documents ................................................... xxiv
Technical Publications Online or on the Web .......................... xxiv
Printed Manuals ...................................................................... xxv
VisualDSP++ and Tools Manuals ......................................... xxv
Hardware Manuals ............................................................. xxvi
Data Sheets ........................................................................ xxvi
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Recommendations for Improving Our Documents .................. xxvi
Conventions ............................................................................... xxvii
INTRODUCTION
DSP Architecture ......................................................................... 1-6
Compute Blocks ..................................................................... 1-8
Arithmetic Logic Unit (ALU) .............................................. 1-9
Multiply Accumulator (Multiplier) .................................... 1-11
Bit Wise Barrel Shifter (Shifter) ........................................ 1-11
Integer Arithmetic Logic Unit (IALU) ................................... 1-12
Program Sequencer ............................................................... 1-13
Quad Instruction Execution .............................................. 1-14
Relative Addresses for Relocation ...................................... 1-15
Nested Call and Interrupt ................................................. 1-15
Context Switching ............................................................ 1-15
Internal Memory and Other Internal Peripherals .................... 1-16
Internal Buses ................................................................... 1-16
Internal Transfer ............................................................... 1-17
Data Accesses ................................................................... 1-17
Quad Data Access ............................................................. 1-17
Scalability and Multiprocessing ............................................. 1-18
External Port ......................................................................... 1-19
External Bus and Host Interface ........................................ 1-19
External Memory .......................................................... 1-19
Multiprocessing ............................................................ 1-20
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Host Interface ............................................................... 1-21
DMA Controller ............................................................... 1-22
Link Ports ......................................................................... 1-23
Miscellaneous ........................................................................ 1-23
Timers .............................................................................. 1-23
Clock Domains ................................................................. 1-23
Booting ...................................................................................... 1-24
Emulation and Test Support ........................................................ 1-24
Programming Model ................................................................... 1-25
MEMORY AND REGISTER MAP
Memory Access Features ................................................................ 2-1
Host Address Space ................................................................. 2-2
External Memory Bank Space .................................................. 2-4
Multiprocessor Space ............................................................... 2-5
Internal Address Space ............................................................. 2-6
Internal Memory Access ........................................................... 2-7
Broadcast Write .................................................................. 2-8
Merged Distribution ........................................................... 2-8
Broadcast Distribution ........................................................ 2-8
Data Alignment Buffer ............................................................ 2-9
Register Access Features ................................................................. 2-9
Register Space ......................................................................... 2-9
Compute Block Register Files ................................................ 2-10
Merged Access .................................................................. 2-11
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Broadcast Transfer ............................................................ 2-11
Unmapped Compute Block Registers ................................ 2-12
Global Registers—XSTAT/YSTAT
Compute Block Status Registers ................................. 2-13
ALU Registers .............................................................. 2-13
Multiplier Registers ...................................................... 2-13
Shifter Registers ............................................................ 2-13
Communications Logic Unit (CLU) Registers ............... 2-13
IALU Registers ...................................................................... 2-14
Register J31 – JSTAT ........................................................ 2-15
Register K31 – KSTAT ..................................................... 2-15
Sequencer Register Groups .................................................... 2-15
Sequencer Control Register – SQCTL ............................... 2-16
Sequencer Control Register Set Bits – SQCTLST .............. 2-16
Sequencer Control Register Clear Bits – SQCTLCL .......... 2-16
Sequencer Status Register – SQSTAT ................................ 2-16
SFREG Register ............................................................... 2-16
ILAT Registers .................................................................. 2-19
IMASK Register ............................................................... 2-19
PMASK Register ............................................................... 2-19
Interrupt Vector Table Register Groups ............................. 2-20
Debug Register Groups ......................................................... 2-21
Performance Monitor Counter – PRFCNT ....................... 2-23
Performance Monitor Mask – PRFM ................................ 2-23
Watchpoint Control – WP0CTL, WP1CTL and WP2CTL 2-25
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Watchpoint Status – WP0STAT, WP1STAT and WP2STAT 2-27
Cycle Counters – CCNT0 and CCNT1 ............................ 2-29
Trace Buffer – TRCB0 to TRCB7 and TRCBPTR ............. 2-29
Watchpoint Address Pointers – WP0L, WP1L, WP2L, WP0H,
WP1H and WP2H ......................................................... 2-29
External Port Registers ........................................................... 2-30
Bus Control/Status (BIU) Register Group .......................... 2-30
SYSTAT/SYSTATCL Register ........................................ 2-31
SYSCON Register (DMA 0x180480) ............................ 2-34
SDRCON (SDRAM Configuration) (DMA 0x180484) . 2-36
BUSLK System Control ................................................ 2-38
BMAX Current Value .................................................... 2-39
BMAX Register ............................................................. 2-39
External Port Configuration and Status Registers ............... 2-41
DMA Registers ................................................................. 2-41
External Port DMA Register .......................................... 2-43
AutoDMA Registers ...................................................... 2-43
AutoDMA0 Register ..................................................... 2-44
AutoDMA1Register ...................................................... 2-44
Link Port Transmit DMA Register ................................. 2-45
Link Port Receive DMA Register ................................... 2-45
DMA Control and Status Register ................................. 2-46
Link Registers ................................................................... 2-47
Link Port Control and Status Register ............................ 2-47
Link Port Receive and Transmit Buffers ......................... 2-48
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CORE CONTROLS
Clock Inputs ................................................................................ 3-1
Operation Modes ......................................................................... 3-2
Emulation Mode ..................................................................... 3-3
Supervisor Mode ..................................................................... 3-4
User Mode .............................................................................. 3-5
Low Power Mode .......................................................................... 3-6
Entering Low Power Mode ...................................................... 3-6
Single Processor System ...................................................... 3-6
Multiprocessing Systems ..................................................... 3-7
Return to Normal Operation ................................................... 3-8
Flag Pins ...................................................................................... 3-8
Timers ......................................................................................... 3-9
Timer Registers ....................................................................... 3-9
Timer Operations ................................................................... 3-9
Timer 0 Output Pin .............................................................. 3-10
INTERRUPTS
Interrupt I/O Pins ........................................................................ 4-2
Interrupt Vector Table .................................................................. 4-2
Interrupt Types ............................................................................. 4-3
Level or Edge Interrupts .......................................................... 4-3
Interrupts Generated by On-Chip Modules ................................... 4-4
Timers .................................................................................... 4-4
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Link Interrupts ........................................................................ 4-5
DMA Interrupts ...................................................................... 4-5
Interrupt Pins (IRQ) ............................................................... 4-6
Vector Interrupt (VIRPT) ........................................................ 4-7
Bus Lock Interrupt .................................................................. 4-7
Hardware Error Operations ..................................................... 4-8
Software Exceptions ...................................................................... 4-9
Emulation Debug .................................................................. 4-10
Other Interrupt Registers ............................................................ 4-11
ILAT Register ........................................................................ 4-11
IMASK Register .................................................................... 4-12
PMASK Register ................................................................... 4-13
Interrupt Service ......................................................................... 4-14
Interrupt Handling ................................................................ 4-19
Returning From Interrupt ........................................................... 4-22
Exceptions .................................................................................. 4-23
CLUSTER BUS
External Bus Features .................................................................... 5-2
Bus Interface I/O Pins ................................................................... 5-3
Processor Microarchitecture ........................................................... 5-3
SYSCON Programming .............................................................. 5-11
Bus Width ............................................................................. 5-14
Slow Device Protocol ............................................................. 5-14
Pipelined Protocol ................................................................. 5-15
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Initial Value .......................................................................... 5-15
TigerSHARC Pipelined Interface ................................................ 5-15
Control Signals ..................................................................... 5-16
Basic Transaction .................................................................. 5-16
Pipelining Transactions ......................................................... 5-18
Wait Cycles ........................................................................... 5-23
Slow Device Protocol .................................................................. 5-27
EPROM Interface ....................................................................... 5-31
Flyby Transactions ...................................................................... 5-34
Multiprocessing .......................................................................... 5-38
Bus Arbitration Protocol ....................................................... 5-41
Core Priority Access (CPA) ............................................... 5-43
DMA Priority Access (DPA) ............................................. 5-43
Bus Fairness — BMAX ..................................................... 5-47
Bus Lock .......................................................................... 5-47
Host Interface ....................................................................... 5-48
Backoff ............................................................................. 5-50
SDRAM INTERFACE
SDRAM I/O Pins ......................................................................... 6-7
SDRAM Physical Connection ....................................................... 6-8
Internal TigerSHARC processor Address and SDRAM Physical
Connection ........................................................................ 6-11
SDRAM Programming ............................................................... 6-19
SDRAM Control Register (SDRCON) .................................. 6-19
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SDRAM Enable .................................................................... 6-22
Selecting the CAS Latency Value (CL) ................................... 6-22
Setting the SDRAM Buffering Option (Pipeline depth) .......... 6-23
Selecting the SDRAM Page Size (Page Boundary) ................... 6-25
Setting the Refresh Counter Value (Refresh Rate) ................... 6-25
Selecting the Precharge to RAS Delay (tRP) ........................... 6-25
Selecting the RAS to Precharge Delay (tRAS) ......................... 6-26
Setting the SDRAM Power-Up Mode (Init Sequence) ............. 6-27
SDRAM Interface Throughput .................................................... 6-27
Multiprocessing Operation .......................................................... 6-28
Understanding DQM Operation ................................................. 6-29
Powering Up After Reset ............................................................. 6-29
SDRAM Controller Commands .................................................. 6-30
Mode Register Set (MRS) Command ..................................... 6-30
Precharge (PRE) Command ................................................... 6-31
Terminating Read/Write Cycles ......................................... 6-32
Precharging ....................................................................... 6-32
Bank Active (ACT) Command ............................................... 6-33
Read Command .................................................................... 6-34
Bus Width = 64 ................................................................ 6-36
Bus Width = 32 ................................................................ 6-37
Write Command ................................................................... 6-38
Bus Width = 64 ................................................................ 6-40
Bus Width = 32 ................................................................ 6-41
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Refresh (REF) Command ...................................................... 6-42
Self-Refresh (SREF) Command ............................................. 6-42
Programming Example ................................................................ 6-43
DIRECT MEMORY ACCESS
DMA Controller Features ............................................................. 7-7
Cluster Bus Transfers ............................................................... 7-7
AutoDMA Transfers ................................................................ 7-9
Link Transfers ......................................................................... 7-9
Two-Dimensional DMA ........................................................ 7-10
Chained DMA ...................................................................... 7-11
DMA Architecture ...................................................................... 7-11
DMAR I/O Pins ................................................................... 7-12
Terminology ......................................................................... 7-13
Setting Up DMA Transfers ......................................................... 7-14
DMA Transfer Control Block Registers ....................................... 7-15
DMA Channel Control ......................................................... 7-15
Transfer Control Block (TCB) Registers ............................ 7-15
DIx Register ................................................................. 7-16
DXx Register ................................................................ 7-17
DYx Register ................................................................ 7-17
DPx Register ................................................................ 7-18
DMA Control and Status Registers ............................................. 7-23
DMA Status Register (DSTAT/DSTATC) .............................. 7-23
DMA Control Registers ........................................................ 7-26
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DCNT Register ................................................................ 7-26
DCNTST Register ............................................................ 7-28
DCNTCL Register ............................................................ 7-28
DMA Control Register Restrictions ....................................... 7-28
Operand Length Setup (Len) ............................................. 7-28
Count (XCOUNT and YCOUNT) ................................... 7-28
Type Setup – Links Transmit (Channels 4 to 7) ................. 7-29
Type Setup – Links Receive (Channels 8 to 11) .................. 7-29
Type Setup – EP (Channels 0 to 3) .................................... 7-30
Type Setup – AutoDMA (Channels 12, 13) ....................... 7-30
DMA Request ................................................................... 7-30
Alignments ....................................................................... 7-30
Address Range .................................................................. 7-31
DMA Controller Operations ....................................................... 7-32
Link Port DMA Control ........................................................ 7-32
External Port DMA Control .................................................. 7-32
AutoDMA Register Control ................................................... 7-33
DMA Transfers ...................................................................... 7-33
Internal Memory Buses ..................................................... 7-33
DMA Channels ................................................................. 7-34
DMA Memory Accesses ......................................................... 7-34
DMA Channel Prioritization ................................................. 7-36
Internal Memory Bus Priority ............................................ 7-36
DMA Channel Priority ..................................................... 7-36
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Rotating Priority .............................................................. 7-39
DMA Chaining ..................................................................... 7-41
Enabling and Disabling Chaining ..................................... 7-42
Interrupting Chaining ...................................................... 7-42
Transfer Control Blocks and Chain Loading ...................... 7-43
Setting Up and Starting the Chain .................................... 7-43
Chain Insertion ................................................................ 7-44
Two-Dimensional DMA ........................................................ 7-45
Two-Dimensional DMA Channel Organization ................. 7-45
Two-Dimensional DMA Operation ................................... 7-46
DMA Interrupts .................................................................... 7-48
Starting and Stopping DMA Sequences ................................. 7-48
Starting a DMA Sequence ................................................. 7-48
Ending a DMA Sequence .................................................. 7-49
Suspending a DMA Sequence ........................................... 7-49
Resuming a DMA Sequence .............................................. 7-49
External Port DMA .................................................................... 7-50
Internal and External Address Generation .............................. 7-50
External Port DMA Transfer Types ........................................ 7-51
External to Internal Memory ............................................. 7-51
Internal to External Memory ............................................. 7-54
External I/O Device to External Memory (Flyby) .............. 7-55
External Memory to External I/O Device (Flyby) .............. 7-57
DMA Semaphores ........................................................ 7-59
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Handshake Mode .............................................................. 7-61
Flyby Mode ...................................................................... 7-61
Link Ports DMA ......................................................................... 7-63
Link Ports DMA Transfer Types ............................................. 7-63
Link Port to Internal/External Memory ............................. 7-63
Internal/External Memory to Link ..................................... 7-63
Receiving Link Port to Link Port ....................................... 7-64
DMA Throughput ...................................................................... 7-66
Internal Memory DMA ......................................................... 7-67
External Memory DMA ......................................................... 7-67
DMA Operation on Boot ............................................................ 7-68
LINK PORTS
Link Architecture .......................................................................... 8-2
Link I/O Pins .......................................................................... 8-2
Transmitting and Receiving Data ............................................. 8-4
DMA ...................................................................................... 8-5
Interrupts ................................................................................ 8-7
Reset and Boot ........................................................................ 8-7
Link Port Communication Protocol ............................................... 8-8
Transmission Delays .................................................................... 8-15
Error Detection Mechanisms ....................................................... 8-17
Transmitter Error Detection .................................................. 8-18
Receiver Error Detection ....................................................... 8-18
Control Register (LCTLx) ........................................................... 8-19
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Status Register (LSTATx) ............................................................ 8-23
DEBUG FUNCTIONALITY
Operating Modes .......................................................................... 9-2
Debug Resources .......................................................................... 9-2
Special Instructions ................................................................. 9-2
Watchpoints ........................................................................... 9-3
Programming – Control and Address Pointer Registers ........ 9-4
Watchpoint Operation ........................................................ 9-7
Watchpoint Status (WPiSTAT) ........................................... 9-8
Instruction Address Trace Buffer (TBUF) ................................ 9-9
Performance Monitors ................................................................ 9-10
Cycle Counter (CCNT1–0) .................................................. 9-11
Performance Monitor Mask – PRFM ..................................... 9-11
Performance Monitor Counter .............................................. 9-12
JTAG Functionality .................................................................... 9-12
Pins ...................................................................................... 9-12
JTAG Instruction Register ..................................................... 9-14
Data Registers ....................................................................... 9-14
SYSTEM DESIGN
Overview .................................................................................... 10-1
TigerSHARC Processor Pins ....................................................... 10-3
Pin Definitions ..................................................................... 10-4
Strap Pin Function Descriptions ................................................. 10-7
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Pin Usage .............................................................................. 10-8
Pin States At Reset .......................................................... 10-10
Power, Reset, and Clock Input Considerations ........................... 10-11
Power Supply Sequencing .................................................... 10-11
Reset ................................................................................... 10-11
Timers ................................................................................ 10-11
Timer Interrupt and FLAG I/O Examples ........................ 10-12
Clock Description and Jitter ...................................................... 10-15
Clock Distribution .............................................................. 10-15
General High Speed Clock Distribution Issues ................. 10-16
Reset and Boot .......................................................................... 10-17
Booting .................................................................................... 10-18
Software Development Tools Support for Booting ................ 10-18
Selecting the Booting Mode ................................................. 10-18
Handling BMS ............................................................... 10-19
Master Mode Boot ...................................................... 10-19
Slave Boot Mode ......................................................... 10-19
General Boot Scenario ......................................................... 10-19
No Boot Mode .................................................................... 10-20
Booting a Single TigerSHARC Processor .............................. 10-20
EPROM/Flash Device Boot ................................................. 10-20
Host Boot ....................................................................... 10-22
Link Port Boot ................................................................ 10-24
Booting a Multiprocessor System ......................................... 10-26
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Multiprocessor EPROM Booting .................................... 10-26
All DSPs Boot in Turn From a Single EPROM ............ 10-26
A Single TigerSHARC Processor Boots Other Processors 10-28
Multiprocessor Host Booting .......................................... 10-30
Memory Initialization During Boot ............................. 10-31
Multiprocessor Link Port Booting ................................... 10-32
DMA Operation on Boot .......................................................... 10-32
Boot EPROM to Internal Memory ...................................... 10-33
EPROM TCB ................................................................ 10-34
Internal Memory TCB .................................................... 10-35
Boot Link to Internal Memory ............................................ 10-36
Boot AutoDMA Register to Internal Memory ...................... 10-37
JTAG Issues .............................................................................. 10-38
Resources and References .......................................................... 10-38
Decoupling Capacitors and Ground Plane Recommendations 10-38
Signal Integrity ................................................................... 10-39
IBIS Models ................................................................... 10-39
Output Pin Drive Strength Control ................................ 10-39
ADSP-TS101 Processor EZ-KIT Lite .............................. 10-40
Recommended Reading References ...................................... 10-40
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Preface
PREFACE
Thank you for purchasing and developing systems using Digital Signal
Processors (DSPs) from Analog Devices.
Purpose of This Manual
The ADSP-TS101 TigerSHARC Processor Hardware Reference provides
architectural information about the TigerSHARC® processors. The archi-
tectural descriptions cover functional blocks, buses, and ports, including
all features and processes that they support. For programming informa-
tion, see the ADSP-TS101 TigerSHARC Processor Programming Reference.
For timing, electrical, and package specifications, see the ADSP-TS101
TigerSHARC Embedded Processor Data Sheet.
Intended Audience
This manual is intended for TigerSHARC processor system designers and
programmers who are familiar with digital signal processing (DSP) con-
cepts. Users should have a working knowledge of microcomputer
technology and DSP related mathematics.
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Manual Contents
xx ADSP-TS101 TigerSHARC Processor
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Manual Contents
This manual provides detailed information about the TigerSHARC pro-
cessor in the following chapters:
• “Introduction”
This chapter provides an architectural overview of the Tiger-
SHARC processor.
• “Memory and Register Map”
This chapter defines the memory map of the TigerSHARC proces-
sor. The memory space defines the location of each element on the
TigerSHARC processor.
• “Core Controls”
This chapter discusses clocking inputs, including the three differ-
ent types of operating modes in which the TigerSHARC processor
can operate and the boot modes from which the TigerSHARC pro-
cessor initiates.
• “Interrupts”
This chapter discusses the various types of interrupts supported by
the TigerSHARC processor. Some of the interrupts are generated
internally or externally.
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