MITS altair 8800b Operator's manual

Figure 1-1
ALTAIR BBOOb COMPUTER
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PAGE I 0

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©MITS, Inc. 1976
Reprinted, June, 1977
0~~00[? ffiffi®®~
00®@[1[](1'.urnGffiJ & TI~®~
a subsidiary of Pertee Computer Corporation
2450 Alamo S.E. / Albuquerque, New Mexico 87106

Section
LIST OF TABLES
LIST OF ILLUSTRATIONS
I. INTRODUCTION
1-1. Scope ••••.
1-2. Arrangement
1-3. Description
II. OPERATORS GUIDE
ALTAIR 8800b
TABLE OF CONTENTS
Page
ii
iii
1-1
1-1
1-1
2-1. General .................... . . . . . . .
2-1
2-2. Front Pane 1 Switches and Indicators . . . • • . •
2-12. Loading A Sample Program ••• · ..••.•••...
2-14. Intel 8080 Microcomputer System User's Information .
III. THEORY OF OPERATION
3-1 • Genera 1 L • • • • • • • • • • • • • • • • • •
3-2. Logic Circuits • . . .. • ........•...
3-3. Intel 8080 Microcomputer System User's Information
3-5. 8080b Block Diagram Description ..•.
3-11. 8800b Data Processing Operation
• . . . 2-1
. . 2-11
2-15
3-3
3-3
3-8
. • • . 3-39
3-44
3-12. Instruction Fetch Cyc 1e • . . .
3-15. Memory Read Cycle .•.•...
3-18. External Device to CPU Data Transfer
3-21. CPU to Memory Data Transfer •...
3-23. Memory Write Cycle Detailed Operation
3-24. Memory to CPU Data Transfer .•..
3-25. CPU To External Device Data ·Transfer
. . . . . . 3-44
3-49
· · · · · ... 3-54
· · .••.. 3-59
. 3-61
. . . . . . 3-63
. . • . 3-64
3-28. Front Panel Operation ..••. . . . . . ..... 3-68
3-39. 8800b Options • . . . .
3-42. 8800b Power Supp 1i es . . . . . .
IV. TROUBLESHOOTING
4-1. Introduction to Traub 1eshooti ng . . • . .
4-2. Visual InspPction ...•...
4-3. Prel imfnary Check ·. . . . . . • •
4-4. Non-PROM Related Switch Problems
4-5. PROM Related Switch Problems
V. ASS8'1BLY
5-1. General .......... ·· ... .
5-2. Assembly Hints ..•..•..•.•....
5-3. Component Installation Instructions
5-9. Interface Card Assembly
5-19. Display/Control Board Assembly
5-32. CPU Board Assembly ....•.
5-44. Power Supply Board Assembly
5-53. Back Panel Assembly ...•
5-69. 18-Slot Motherboard Assembly
APPENDIX
April, 1977
8800b
. • 3-88
. • 3-89
. . . . 4-5
. 4-14
. . 4-15
. 4-31
.. 4-54
. 5-3
. . 5-3
. . . • . 5-5
. . 5-13
. . 5-19
. . 5-37
. 5-47
. 5-54
. . 5-69
i
- J,

Number
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
27"10
2-ll
2-12
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
ii
LIST OF TABLES
Altair 8800b Switches and Indicators
Power On Sequenc~ •.••
Run Operation .•.••••••
Stop Operation •••..•••
Examine Memory Operation •••
Altering Memory Contents ••.
Examine Next Memory Location •
Altering Next Memory Contents •••.
Loading and Displaying Accumulator Data
Machine Language Bit Patterns ·•
Addition Program .....
Addition .Program Loading .
Symbol Definitions •..
PRCJt1 Programs ••..•.
Static Levels of the Most Common
Mother Board Static Levels
Voltage and Waveform Check
Reset Check •....
Stop Check •...•.•
Run.Check . ~ .•..•.
Single Step/Slow Check •
Protect/Unprotect Check
Sense Switch Check . • . . • • .
Status Check ••.••.
PROM Related Switch Problems
Problem Areas
Page
2-2
2-6
2-6
2-7
2-7
2-8
_2-8
2-9
2-10
2-12
2-13
2-14
3-5
3-76
4-9
4-11
4-18
4-32
4-34
4-43
4-44
4-48
4-50
4-53
4.,.55
April, 1977
8800b

Number
1-1
1-2
1-3
1-4
1-5
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-1
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-15
3-15
3-16
3-16
3-16
3-17
3-18
3-1.9
3-20
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9"
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
LIST OF ILLUSTRATIONS
Title
Altair 8800b Computer ..••..
Power Supply Board .•.
Interface Board .. .
CPU Board ..... .
Display/Control Board ••••
Altair 8800b Front Panel •
8800b Block Diagram ••••••
Instruction Fetch Cycle Block Diagram •..•..
Instruction Fetch Cycle Timing ••
Memory Read Cycle Block Diagram
Memory Read Cycle Timing ...•..•....•••.
Input Read Cycle Block Diagram •.
Input Read Cycle Timing •..••
Memory Write Cycle Block Diagram
Memory Write Cycle Timing ••.•
Output Write Cycle Block Diagram.
Output Write Cycle Timing .•
Front Panel Block Diagram .
PRCM Block Diagram ....•••..
CPU Schematic •.••••••.•
Interface Schematic (sheet 1 of 3) •
Interface Schematic (sheet 2 of 3) .•
Interface Schematic (sheet 3 of 3) ...•...
Display/Control Schematic (sheet 1 of 3) .
Display/Control Schematic (sheet 2 of 3) •.
Display/Control Schematic (sheet 3 of 3) .
Power Supply Board Schematic .•••••••
CPU Voltage Regulator Schematic •••.•.•.
Interface Voltage Regulator Schematic •.
Display/Control Voltage Regulator Schematic.
Typi ca 1 Si 1kscreen • -. • • • • • • • • • • • • • • • • .
Interface IC Installation . • • • • • • • • . • ••.
Interface Resistor Installation •.•••••••••••.
Interface Suppressor Capacitor and Capacitor Installation •
Interface Jumper Connections. • • . • • • • : •••
Interface Ferrite Bead Installation ••.••
Interface Voltage Regulator Installation .•.
Interface Male Connector Installation •• ~ .•.••...
Interface Ribbon Cable Plug Installation •.•
Display/Control IC Socket and IC Installation
Display/Control IC Installation •••.••••
Display/Control Resistor Installation ••..•
Display/Control Resistor Pack Installation ••
Display/Control Substitute Resistor Assembly.
Display/Control Jumper Connections • ~. . • . . •
Display/Control Suppressor Capacitor Installation
Display/Control Capacitor Installation •.•••.
Display/Control Diode and Ferrite Bead Installation •.•.
Apr-11, 1977
8800b
Page
1-0
1-2
1-2
1-4
1-4
2-1
3-40
3-46
3-47
3-50
3-53
3-56
3-57
· 3-60
3-62
3-65
3-67
3-69
3-75
3-91
3-93
3-95
3-97
3-99
3-101
3-103
3-105
3-107
3-109
3-111
5-4
5-2
5-14
5-15
5-16
5-15
5-17
5-18
5-19
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
; ; ;

Number
5-19
5-20A
5-20B
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40.
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49A
5-49B
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
iv
LIST OF ILLUSTRATIONS - Continued
Title Page
Display/Control Voltage Regulator Installation. • • 5-30
Display/Control Switch Installation ••••••••••••• 5-31
Display/Control Switch Installation • • • . • • • 5-32
Display/Control Switch Nut Placement. • • • • • • • • 5-33
Covering LED Holes on Sub Panel • • • • • • • • • • 5-33
Display/Control LED Orientation and Installation. • • ~. 5-34
Securing Sub Panel Over Display/Control Board. • 5-34
Display/Control LED Adjustment. • • • • • • .• • 5-35
CPU IC Iristallation. • • . • • • . • • •• 5-37
CPU Resistor Installation. • • • • • • • 5-38
CPU Suppressor Capacitor Installation. • • 5-39
CPU Capacitor Installation. • • • • • • • • • • 5-40
CPU Diode Installation. • • • • • . • • ••••••••• 5-41
CPU Ferrite Bead Installation • • • • • • • • .• • . • 5-42
CPU Voltage Regulator Installation. • • . • • •••• 5-43
CPU Transistor and Male Connector Installation. • • 5-44
CPU Crystal Installation. • • • • . . • . • • • • ••• 5-45
CPU IC Socket and IC Installation •.•••••••.•••. 5-46
Power Supply Capacitor and Resistor Installation. • • 5-47
Power Supply Diode Installation • • • • • • • •• 5-48
Power Supply Transistor Installation. • • • • • • • 5-49
Power Supply Bridge Rectifier . . • • • . • . • • • . •. 5-50
Power Supply Terminal Bl eek Screw Removal • • • • . . •• 5-51
·Power Supply Terminal Block Screw Insertion • • • • • 5-51
Power Supply Terminal Block Shorting Link Insertion ••••• 5-51
Power Supply Board Mounting to Cross Member. • ..••• 5-52
Power Supply Capacitor and Clamp Installation
. (For One Capacitor) • •
5-53
Power Supply Capacitor and Clamp Installation
· (For Two Capacitors) •.••
. 5-53
5-54
Completed Back Panel Assembly ••.••••.•
Terminal End Sizes •••••••.•.•••••
• 5-55
. 5-56
Termi na 1 End Attachment • • • • • • • • • • • • •
Connector Pin and Connector Socket Wire lrisert,on
•••••• 5-57
Pin and Socket Housing Assembly
Wiring Diagram •••.. _ •• - ••
Bridge Rectifier Installation •
Fan Mounting ••••.••
Fuse Hrilder Installation
AC Power Cord Installation
11
L
11
Bracket_ Mounting ••
Terminal End Attachment
Terminal Block Mounting
Pin Housing Insertion ••
Transformer Mounting •••••
Back Panel Mounting ••••
Motherboard Wire Connections
Card Guide Mounting ._ •••••
Chassis Ground Connection •••••.
On/Off Switch Wiring • • ._ •
Female Connector Wiring for P3
••• 5-57
• . • • . 5-58
. • • . • • 5-60
• . • • • • 5-61
..••• 5-62
• 5-62
• 5-63
••• 5-63
• 5-63
• 5-65
. ......• 5-66
. . • . . .. 5-67
• • • • • 5-68
• 5-70
.• 5-71
•••• 5-73
. • • . • • . 5-75
April, 1977
8800b

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-

1-1. SCOPE
This ALTAIRrM8800b Documentation
provides a general description of
the various printed circuit cards
contained in the ALTAIR 88OOb and
detailed theory of their operation.
Included in the documentation is
an operator's guide which famili-
arizes the operator with the var-
ious switches and indicators on
the ALTAIR 88OOb front panel. De-
tailed assembly instructions are
a1 so provided.
1-2. ARRANGEMENT
This manual contains five sections
as follows:
1. Section I contains a general
description of the ALTAIR 88OOb
computer and associated printed
circuit cards.
2. Section II contains information
on the controls and indicators
which are located on the ALTAIR
88OOb front panel.
3: Section III contains a detailed
theory explanation of the ALTAIR
88OO~ circuit operation.
4. Section IV contains trouble-
shooting information for the
ALTAIR 88OOb.
5. Section Vcontains the detailed
assembly instructions for the
ALTAIR 88OOb.
Apri 1, 1977
8800b
SECTION. I
INTRODUCTION
1~3. DESCRIPTION
The ALTAIR 88OOb computer (Figure
1-1) is a general purpose, byte-
oriented machine (8-bit word).
It uses a common 1OO-pin bus struc-
ture that allows for expansion of
either standard or custom plug-in
modules. It supports up to 64K of
directly addressable memory and
can address 256 separate input and
output devices. The ALTAIR 88OOb
computer has 78 basic machine lan-
guage instructions and consists of
a power supply board, an interface
board, a central processing unit
(CPU) board, and a display/control
board.
1-4. POWER SUPPLY BOARD (Figure 1-2)
The Power Supply Board provides two
of the three output voltages to the
ALTAIR,88OOb computer bus, a posi-
tive and negative 18 volts. It
includes a bridge rectifier circuit
and associated filter capacitors, a
1O-pin terminal block connector,
and the regulating transistors for
the positive and negative 18 volt
supplies.
1-5. INTERFACE BOARD (Figure 1-3)
The Interface Board buffers all
signals between the display/control
board and the ALTAIR 88OOb bus. It
also contains eight parallel data
lines which transfer data to the CPU
from the Display/Control board.
Page T-1

~ ~
i1oozz A~zd"oozz"
Figure 2. Povver Supply Board
Figure 3. Interface Board -
2

Figure 4. CPU Board
Figure 5. Display/Control Board
3

4
1-6. ~PU BOARD (Figure 1-4)
The CPU board controls and processes
all instructions and data within
the ALTAIR 88OOb computer. It-con-
fai ns the Intel Corporation model
8O8OA microprocessor circuit, the
master timing circuit, eight input
and eight output data lines to the
ALTAIR bus control circuits.
1-7. DISPLAY/CONTROL BOARD (Figure
.81
The Display/Control Board conditions
all ALTAIR 88OOb front panel switches
and receives information to be dis-
played on the front panel. It con-
tains a programmable read only
memory (PROM), switch ·and display
control circuits, and control cir-
cuits to condition the CPU.
--

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-2-1.
GENERAL
The Operators Guide contains information on the ALTAIR 8800b
computer (8800b) front panel controls and indicators. It includes
general switch operation exercises and a sample program which is
intended to familiarize the operator with the various front panel
operations. Provided in this section are portions of the Intel 8080
Microcomputer Systems Users Manual which contain Central Processor
Unit, Interface and Software information. Additional programs available
to the user are described in the ALTAIR Software Library. Update infor-
mation is contained with your unit.
2-2. FRONT PANEL SWITCHES AND INDICATORS
The Front Panel switches permit the operator to perform various
ALTAIR 8800b operations, and the indicators display address informa-
tion, data information, and primary status control line information.
Refer to Figure 2-l for the location of the switches and indicators
and Table 2-l for an explanation of each.
Figure 2-1. Altair 8800b Front Panel
2-1

Table 2-1. ALTAIR 8800b Switches and Indicators
Switch
POWER ON/OFF
STOP/RUN
SINGLE STEP/
SLOW
EXAMINE/
EX NEXT
[2-2
Function or Indication
Applies power to the ALTAIR 8800b
The RUN position allows the CPU to process
data and disables all functions on the
front panel except reset. The STOP pos-
ition conditions the CPU to a wait state
and enables all functions on the front
panel.
The SINGLE STEP position allows execu-
tion of one machine cycle or one instruc-
tion cycle (depending upon the option
selected). SLOW position allows execu-
tion of machine or instruction cycles
at a rate of approximately 2 cycles per
second. (Normal speed is approximately
500,000 ·machine cycles per second.)
The CPU will execute the cycles as·long
as the SLOW position is maintained.
The EXAMINE position allows the operator
to examine the memory address selected
on the AO-Al5 MEMORY switches. The
contents at that address are displayed
on the DATA D0-D7 indicators. The EX
NEXT position allows the operator to
examine the next sequential memory
address. Each time EX NEXT is actuated,
the contents of the next sequential
memory address are displayed.
)

Table 2-1. ALTAIR 8800b Switches and Indicators -Continued
Switch Function or Indication
DEPOSIT/ The DEPOSIT position stores the contents
DEP NEXT of the lower address switches (AO-A?)
RESET/
EXT CLR
PROTECT/
UN PROTECT*
ACCUMULATOR
DISPLAY/LOAD
into the memory address that is displayed
on the MEMORY address AO-Al5 indicators.
The DEP NEXT position stores the contents
of the lower address switches (AO-A?) into
the next successive memory address.
The RESET position resets the program
counter to zero and the interrupt enable
flag in the CPU. The EXT CLR position
produces an external clear signal on the
system bus which generally clears an
input/output.
The PROTECT position conditions the
write protect circuits on the currently
addressed memory board, preventing data
in that block of memory from being
changed. The front panel or the CPU
cannot affect the memory when protected.
UNPROTECT position allows the contents
of memory to be changed.
The DISPLAY position allows the contents
of the CPU accumulator register to be
displayed on the DATA D0-07 indicators.
The LOAD position allows the lower
eight address switch (AO-A?) information
to be stored in the CPU accumulator
register.
*Protect switch only applies to memory boards with a arotect
circuit.
Aoril, 197i
BSOOb
2-3

Table 2-1. ALTAIR 88OOb Switches and Indicators -Continued
Switch or Indicator Function or Indication
2-4
INPUT/ The INPUT position allows an external
OUTPUT device, selected on the I/O AO-A7 switches
(upper eight address switches), to input
data into the CPU accumulator. The
Address Switches
AO-Al5
SENSE switches
A8-Al5
MEMORY AO-AlS
PROTECT
INTE
MEMR
!NP
Ml
OUT
OUTPUT position allows an external de-
vice, selected on the I/O AO-A7 switches,
to receive data from the CPU accumulator
register.
These switches are used to select an
address in memory or to enter data. The
up position denotes a one bit and the
down position denotes a zero bit.
· The upper eight address switches (A8-
Al5) also function as SENSE switches.
The data present on these switches is
stored in the accumulator if an input
from channel 377
8
(front panel) is exe-
cuted.
Display the memory address being examined
or loaded with data.
Memory is protected.
Interrupts are enabled.
The CPU is reading data from memory.
An external device is inputting data
to the CPU.
The CPU is in machine cycle one of an
instruction cycle.
The CPU is outputting data to an
external device.
April, i977
SSOOb

Table 2-1.
Indicator
HLTA
STACK
WO
INT
ALTAIR 8800b Switches and Indicators -Continued
Function or Indication
The CPU is in a halt condition.
The address bus contains the address
of the stack pointer.
The CPU is writing out data to an
external device or memory.
The CPU has acknowledged an interrupt
request.
DATA 00-07
Data from memory, an external device,
or the CPU
.Acri l , 1977
SSCCb
WAIT
HLDA
The CPU is in a wait condition.
The CPU has acknowledged a hold
signal .
2-5

2-3. FRONT PANEL SWITCH APPLICATIONS
The following switch applications are intended to familiarize
the operator with the ALTAIR 880Gb front panel switches and indica-
tors. Perform the operations in a sequential manner as shown in the
following tables.
2-4. POWER ON SEQUENCE (Table 2-2)
The power on sequence resets the CPU program counter to the first
memory address and places the CPU in a wait condition at the beginning
of an instruction cycle.
Table 2-2. Power On Sequence
Step Function Indication
1 Position the
POWER ON/
MEMR, Ml, and WAIT indica-
OFF switch to ON.
tors are on.
Some DATA
00-07 indicators may also
be on. All
other indicators
are off.
2-5. RUN OPERATION (Table 2-3)
The run operation releases the CPU from a wait condition, and
allows it to execute a program. When the run operation is enabled,
all other front panei switches are inactive except the RESET switch.
Table 2-3. Run Operation
Step Function Indication
1 Momentarily
position the
WAIT
indicator is off
STOP/RUN switch to RUN.
(or may be dimly 1it).
The machine can
now exe-
cute a program.
,, ~
'--o Apr~l, 1977
8800b

2-6. STOP OPERATION {Table 2-4)
The stop operation places the CPU in a wait condition and allows
the operator to use the switches on the 8800b front panel.
Table 2-4. Stop Operation
Step Function Indication
l Position the STOP/RUN WAIT,
MEMR, and Ml
indicators
switch to STOP.
are on. The operator now
has control of the front
l panel.
2-7. EXAMINE MEMORY OPERATION (Table 2-5)
This procedure allows the operator to select a memory address
and examine its contents.
Table 2-5. Examine Memory Operation
Step Function Indication
l Position the address
switches AO-A15
I
down.
I
I 2 Position the
EXAMINE/ AO through Al5 indicators are
I
'
i
EX NEXT switch
EXAMINE.
to off, indicating memory address
location 000
8
is being examined. 1
DATA DO through 07 indicators i
3
4
Aori 1, i 977
8800!::i
Position address
switches Al and A2
up.
Position the EXAMINE/
EX NEXT switch to
EXAMINE.
are displaying the contents
of location 000
8.
Al and A2 indicators are on,
indicating memory address 006
8
is being examined. DATA DO
through 07 indicators are dis-
playing the contents of loca-
tion 006
8.
I
2-7

2-8
2-8. ALTERING MEMORY CONTENTS (Table 2-6)
This procedure allows the operator to select a memory address
and change its contents.
Table 2-6. Altering Memory Contents
Step Function Indication
1 Position address switch
AS up and the remaining
switches down.
2 Position the
EXAMINE/
AS indicator is on, indi-
EX NEXT switch to EXAMINE
eating memory address 040
8.
DATA DO through 07 indi-
caters are displaying the
contents of location 040
8.
3 Position the
AO through
A7 address switches up.
4 Position the
DEPOSIT/DEP
DATA DO through 07 indi-
NEXT to DEPOSIT
caters are on, indicati~g
the new data that has been
placed in address location
0408.
2-9. EXAMINE NEXT MEMORY LOCATION (Table 2-7)
t
I
I
1
i
I
I
I
I
I
This procedure allows the operator to examine the next sequential
memory location, as determined by the address switches.
Table 2-7. Examine Next Memory Location
Step Function Indication
1 Position address switches
AO and AS up, and the re-
maining switches down.
2 Position the EXAMINE/EX AO and AS indicators are
NEXT switch to EXAMINE
on, indicating memory
address 041
8.
I
!
April, 1977
8800!:>