MITS altair 8800b Operator's manual

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Figure 1-1 ALTAIR BBOO b COMPUTER
PAGE 10

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© MITS, Inc. 1976
Reprinted, June, 1977
0~~0D[f ffiffi®®~
[ID®®[l[J~rn[Jmj' ill TI~®~
a subsidiary of Pertec Computer Corporation
2450 Alamo S.E. / Albuquerque, New Mexico 87106

Section
LIST OF TABLES • • . •
LIST OF ILLUSTRATIONS
ALTAIR 8800b
TABLE OF CONTENTS
Page
ii
iii
1-1
1-1
1-1
2-1
2-1
.2-11
· . 2-15
. . . 4-5
.
4-14
· . 4-15
· . 4-31
· . 4-54
I. INTRODUCTION
1-1. Scope
1-2. Arrangement
1-3. Description
II. OPERATORS GUIDE
2-1. General .
2-2. Front Panel Swi tches and Indi cators ..•••.•
2-12. Loading A Sample Program ••• " •.• '0' •••••
2-14. Intel 8080 Microcomputer System User's Information .
III. THEORY OF OPERATION
3-1 • General... . . • • • • . • • . . . . . 3-3
3-2.
Logic Circuits •. '.' .••... . . . • . . . 3-3
3-3. Intel 8080 Microcomputer System User's Information 3-8
3-5. 8080b Block Diagram Description . . • •. . ••.. 3-39
3-11. 8800b Data Processing Operation . . • • • • 3-44
3-12. Instruction Fetch Cycle ••.• . ••...•••..• 3-44
3-15. Memory Read Cycle ...••.• . •..... 3-49
3-18. External Device to CPU Data Transfer. . .....•.• 3-54
3-21. CPU to Memory Data Transfer ••... • .....••.. 3-59
3-23. Memory Wri te Cycle Deta 11 ed Opera ti on . . • . .... 3-61
3-24. Memory to CPU Data Transfer .••. .... . . 3-63
3-25. CPU To External Devi ce Data 'Trans fer . ..•. ..• • 3-64
3-28. Front Panel Operation • • . . . . . •. 3-68
3-39. 8800b Opti ons .... . ...•.. • • • 3-88
3-42. 8800b Power Supp 1i es . . . . . • . . . • . . • 3-89
IV. TROUBLESHOOTING
4-1. Introduction to Troubleshooting
4-2.
Visual Insp~ction ...•..•
4-3. Prel imfnary Check '........
4-4. Non-PROM Related Switch Problems
4-5. PROM Related Switch Problems
V. ASSEMBLY
5-1. General. .........'. .... .........5-3
5-2. Assembly Hints •..•••..•.••..•....•...• ,5-3
5-3.
Component Installation Instructions ...•.•. 5-5
5-9. Interface
Card Assembly . . . . . • . . . .. . 5-13
5-19. Display/Control Board Assembly . • . .. . ..... 5-19
5-32. CPU Board Assembly . ',' • . . • • . • . 5-37
5-44. Power Supply Board Assembly . . . . . 5-47
5-53. Back Panel Assembly ...•. • . • • . • . . . 5-54
5-69. 18-S10t Motherboard Assembly . . • . . . • • . •. 5-69
APPENDIX
April t1977
8800b i
- j

Number
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2,:,,10
2-,.,
2-12
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
;;
LIST OF TABLES
Altair 880Ub Switches and Indicators •.
Power On Sequenc~ ••••
Run Operation .•.••
Stop Operation • • • . . • • • • • • ••
Examine Memory Operation • • • • ••••
A1 teri ng Memory Contents • • • • • .
Exami ne Next Memory Loca ti on • • • • • . • • •
Altering
Next Memory Contents •••.
Loading and Displaying Accumulator Data
Machine Language Bit Patterns ".
Addition Program
Addition program Loading •
Symbol Definitions • . .
PRCJt1 Programs ••••••
Static Levels of the Most Common Problem Areas
Mother Board Static Levels .••...••
Voltage and Waveform Check • . .•••
Reset Check •.••. ~
Stop Check . . . . . . . . . . . .
Run.Check . ~ . . . . . . . .
Single Step/Slow Check • . .•••••••
Protect/Unprotect Check •••.
Sense Switch Check . • •
Status
Check • • . • • . • • • •
PROM Related Switch Problems
Page
2-2
2-6
2-6
2-7
2-7
2-8
_2-8
2-9
2-10
2-12
2-13
2-14
3-5
3-76
4-9
4-11
4-18
4-32
4-34
4-43
4-44
4-48
4-50
4-53
4-55
April. 1977
8800b

Number
1-1
1-2
1-3
1-4
1-5
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-15
3-15
3-16
3-16
3-16
3-17
3-18
3-1.9
3-20
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-g
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
LIST OF ILLUSTRATIONS
Title
Altair 8800b Computer
Power Supply Board . •
Interface
Board • . .
CPU Board • • • • . •
Display/Control
Board • • ••
Altair 8800b Front Panel •
8800b Block Diagram ••••••
Instruction Fetch Cycle Block Diagram
Instruction Fetch Cycle Timing • • • .
Memory Read Cycle Block Diagram
Memory Read Cycle Timing ••.••
Input Read Cycle Block Diagram.
Input
Read Cycle Timing •..•
Memory Write Cycle Block Diagram
Memory Write Cycle Timing ••.•.•.....•••
Output Write Cycle Block Diagram.
Output Write Cycle Timing ••.
Front Panel Block Diagram .
PRCM Block Di agram • • . • • • •
CPU Schematic •.••••••••
Interface Schematic (sheet 1 of 3) •
Interface.
Schematic (sheet 2of 3)
Interface Schematic (sheet 3of 3) •..•.•.
Display/Control Schematic (sheet 1of 3) •
Display/Control Schematic (sheet 2of
3)
Display/Control Schematic (sheet 3of 3) .
Power Supply Board Schematic • • • • ••
CPU Voltage Regulator Schematic •••.•••.
Interface Voltage Regulator Schematic ••.•••
Display/Control Voltage Regulator Schematic.
Typical Si 1kscreen .-. • • • • • • • • • • •
Interface
IC Installation •••••••••
Interface Resistor Installation ••••••••••••••
Interface Suppressor Capacitor and Capacitor Installation •
Interface
Jumper Connections •• • . • • ..
Interface Ferrite Bead Installation ••.••
Interface Voltage Regulator Installation .•.
Interface Male Connector Installation •••.•.••••.
Interface Ribbon Cable Plug Installation •..
Display/Control IC Socket and IC Installation
Display/Control IC Installation •••.••••
Display/Control Resistor Installation •••••
Display/Control Resistor Pack Installation ••••
Display/Control Substitute Resistor Assembly.
Display/Control
Jumper Connections • ~.' •..•
Display/Control Suppressor Capacitor Installation
Display/Control Capacitor Installation ••••••
Display/Control Diode and Ferrite Bead Installation
Page
1-0
1-2
1-2
1-4
1-4
2-1
3-40
3-46
3-47
3-50
3-53
3-56
3-57
.3-60
3-62
3-65
3-67
3-69
3-75
3-91
3-93
3-95
3-97
3-99
3-101
3-103
3-105
3-107
3-109
3-111
5-4
5-2
5-14
5-15
5-16
5-15
5-17
5-18
5-19
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
April, 1977
8aOOb
; ; ;

LIST OF ILLUSTRATIONS - Continued
• 5-53
April. 1977
8800b
• • • • . 5-53
• • • • • 5-54
• 5-55
5-56
••••• 5-57
• •• 5-57
• 5-58
•• 5-60
• 5-61
• • • 5-62
.. 5-62
•
5-63
• •• 5-63
• 5-63
• 5-65
5-66
. . . . . . . . .5-67
.. 5-68
• 5-70
•• 5-71
• • • • 5-73
...... .5-75
Title Page
Display/Control Voltage Regulator Installation. • • •• 5-30
Display/Control Switch Installation • • • • • • • •••• 5-31
Display/Control Switch Installation • • • • • • • •••• 5-32
Display/Control Switch Nut Placement. • • • • • • • ••• 5-33
Covering LED Holes on Sub Panel • • • • • • • .. • • 5-33
Display/Control LED Orientation and Installation. • 5-34
Securing Sub Panel Over Display/Control Board. • 5-34
Display/Control LED Adjustment. • • •• • • .• • • • 5-35
CPU IC Installation • • • • • • • . • • • • • • •• 5-37
CPU Resistor Installation. • • • • • • 5-38
CPU Suppressor Capacitor Installation •••• 5-39
CPU Capacitor Installation. • • • • • • • • • • 5-40
CPU Diode Installation. • • • • • • • • ••• 5-41
CPU Ferri te Bead Install ati on • • • • • • • •.• • 5-42
CPU Voltage Regulator Installation. • • • • • 5-43
CPU Transistor and Male Connector Installation. • • 5-44
CPU Crystal Installation. • • • • • • • • • • • • 5-45
CPU IC Socket and IC Install ati on • . • • • • • • • 5-46
Power Supply Capacitor and Resistor Installation. • ••• 5-47
Power Supply Diode Installation • • • • • • • •• 5-48
Power Supply Transistor Installation. • • • • • • • 5-49
Power Supply Bridge Rectifier . • • • • • • • • • • . •• 5-50
Power Supply Terminal Block Screw Removal • • • • • • •• 5-51
. Power Supply Terminal Block Screw Insertion. • • • 5-51
Power Supply Terminal Block Shorting Link Insertion ••••• 5-51
Power Supply Board Mounting to Cross Member • • ••••• 5-52
Power Supply Capacitor and Clamp Installation
.(For One Capacitor) •
Power Supply Capacitor and Clamp Installation
.(For Two Capacitors)
Completed Back Panel Assembly • • • • • • • • •
Terminal End Sizes ••••••••• ••••••
Terminal End Attachment • • • • • • • • • • • • •
Connector
Pin and Connector Socket Wire Insertlon •
Pin and Socket Housing Assembly
Wi ring Di agram ...... _. .-.
Bridge Rectifier Installation •
Fan Mounting .
Fuse Holder Installation .
AC Power Cord Installation
IILl! Bracket. Mounting ••
Terminal End Attachment
Terminal Block Mounting
Pin Housing Insertion .. • • ••••
Transformer Mounting •••••• ..
Back Panel Mounting • •
Motherboard Wire Connections
Card Gui de Mounting ._. • • • •
Chassis
Ground Connection •••
On/Off Swi tch Wi ri ng ..._.
Female Connector Wiring for P3
Number
5-19
5-20A
5-20B
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40.
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49A
5-49B
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
iv

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1-1. SCOPE
This ALTAI~M8800b Documentation
provides ageneral description of
the various printed circuit cards
contained in the
ALTAIR 8800b and
detailed theory of their operation.
Included in the documentation
is
an operator's guide which famili-
arizes the operator with the var-
ious switches
and indicators on
the ALTAIR 8800b front panel. De-
tailed assembly instructions are
also provided.
1-2.
ARRANGEMENT
This manual contains five sections
as follows:
1. Section Icontains ageneral
description
of the ALTAIR 8800b
computer and associated printed
circuit cards.
2. Section II contains information
on the controls and indicators
which are located on the ALTAIR
8800b front panel.
3: Section III contains adetailed
theory explanation of the
ALTAIR
8800~ circuit operation.
4. Section IV contains trouble-
shooting information for the
ALTAIR 8800b.
5. Section Vcontains the detailed
assembly instructions for the
ALTAIR 8800b.
April, 1977
8S00b
SECTION. I
INTRODUCTION
1~3. DESCRIPTION
The ALTAIR 8800b computer (Figure
1-1)
is ageneral purpose, byte-
oriented
machine (8-bit word).
It uses a common lOO-pin bus struc-
ture that allows for expansion of
either standard or custom plug-in
modules. It supports up to 64K of
directly addressable memory and
can address 256 separate input and
output devices. The ALTAIR 8800b
computer has 78 basic machine lan-
guage instructions and consists of
a power supply board, an interface
board, acentral processing unit
(CPU) board, and adisplay/control
board.
1-4.
POWER SUPPLY BOARD (Figure 1-2)
The Power Supply Board provides two
of the three output voltages to the
ALTAIR.8800b computer bus, aposi-
tive and negative 18 volts. It
includes abridge rectifier circuit
and associated filter capacitors, a
lO-pin terminal block connector,
and the regulating transistors for
the positive
and negative 18 volt
supplies.
1-5.
INTERFACE BOARD (Figure 1-3)
The Interface Board buffers all
signals between the display/control
board and the ALTAIR 8800b bus. It
also contains eight parallel data
lines
which transfer data to the CPU
from the Display/Control board.
Page T-1

2
Figure 2. Povver Supply Board
Figure 3. Interface Board --

Figure 4. CPU Board
Figure 5. Display/Control Board
3

4
1-6. ~PU BOARD (Figure 1~4)
The CPU board controls and processes
all instructions and data within
the
ALTAIR 8800b computer. It·con-
fai ns the Intel Corporation model
8080A microprocessor circuit, the
master timing
circuit, eight input
and eight output data lines to the
ALTAIR bus control circuits.
1-7. DISPLAY/CONTROL BOARD (Figure
Ell
The Display/Control Board conditions
all ALTAIR 8800b front panel switches
and receives information to be dis-
played on the front panel. It con-
tains a programmable read only
memory (PROM), switch "and display
control
circuits, and control cir-
cuits to condition the CPU.

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2-1. GENERAL
The Operators Guide contains information on the ALTAIR 8800b
computer (8800b) front panel controls and indicators. It includes
general switch operation exercises
and asample program which is
intended to familiarize the operator with the various front panel
operations. Provided in this section are portions of the Intel 8080
Microcomputer Systems Users Manual which contain Central Processor
Unit,
Interface and Software information. Additional programs available
to the user are described in the ALTAIR Software Library. Update infor-
mation is contained with your unit.
2-2. FRONT PANEL SWITCHES AND INDICATORS
The Front Panel switches permit the operator to perform various
ALTAIR 8800b operations, and the indicators display address informa-
tion, data information, and primary status control line information.
Refer to Figure
2-1 for the location of the switches and indicators
and Table 2-1 for an explanation of each.
Figure 2-1.
Altair 8800b Front Panel
2-1

Switch
Table 2-1.
ALTAIR 8800b Switches and Indicators
Function or Indication
POWER ON/OFF
STOP/RUN
SINGLE STEP/
SLOW
EXAMINE/
EX NEXT
2-2
Applies power to the ALTAIR 8800b
The RUN position allows the CPU to process
data
and disables all functions on the
front panel except reset. The STOP pos-
ition conditions the CPU to await state
and enables all functions on the front
panel.
The SINGLE STEP position allows execu-
tion of
one machine cycle or one instruc-
tion cycle (depending upon the option
selected). SLOW position allows execu-
tion of
machine or instruction cycles
at a rate of approximately 2cycles per
second.
(Normal speed is approximately
500,000 'machine cycles per second.)
The CPU will execute the cycles as'long
as the SLOW position is maintained.
The EXAMINE position allows the operator
to
examine the memory address selected
on the AO-A15 MEMORY switches. The
contents at that address are displayed
on the DATA 00-07 indicators. The EX
NEXT position allows the operator to
examine the next sequential memory
address. Each time EX NEXT is actuated,
the contents
of the next sequential
memory address are displayed.
)

Table 2-1.
Swi tch
DEPOSIT/
DEP NEXT
RESET/
EXT CLR
ALTAIR 8800b Switches and Indicators -Continued
Function or Indication
The DEPOSIT position stores the contents
of the lower address switches (AO-A?)
into the memory address that is displayed
on the MEMORY address AO-A15 indicators.
The DEP NEXT position stores the contents
of the lower address switches
(AO-A?) into
the next successive
memory address.
The RESET position resets the program
counter to zero and the interrupt enable
flag in the
CPU. The EXT CLR position
produces
an external clear signal on the
system
bus which generally clears an
input/output.
PROTECT/
UNPROTECT*
ACCUMULATOR
DISPLAY/LOAD
*Protect switch only
circuit.
Aoril, 19n
8300b
The PROTECT position conditions the
write protect
circuits on the currently
addressed
memory board, preventing data
in
that block of memory from being
changed.
The front panel or the CPU
cannot affect the memory when protected.
UNPROTECT position allows the contents
of memory to be changed.
The DISPLAY position allows the contents
of the
CPU accumulator register to be
displayed on the DATA DO-o? indicators.
The LOAD position allows the lower
eight address switch
(AD-A?) information
to
be stored in the CPU accumulator
register.
applies to memory boards with aprotect
2-3

Table 2-1.
Switch or Indicator
INPUT/
OUTPUT
Address Switches
AO-A15
SENSE swi tches
A8-A15
MEMORY AO-A15
PROTECT
INTE
MEMR
INP
Ml
OUT
2-4
ALTAIR 8800b Switches and Indicators -Continued
Function or Indication
The INPUT position allows an external
device, selected
on the I/O AO-A7 switches
(upper eight address switches), to input
data into the
CPU accumulator. The
OUTPUT position allows an external de-
vice, selected
on the I/O AO-A7 switches,
to receive data
from the CPU accumulator
register.
These switches are used to select an
address in memory or to enter data. The
up position denotes a one bit and the
down position denotes azero bit .
.
The upper eight address switches (A8-
A15) also function as SENSE switches.
The data present on these switches is
stored in the accumulator if an input
from channel 377
8
(front panel) is exe-
cuted.
Display the
memory address being examined
or loaded with data.
Memory is protected.
Interrupts are enabled.
The CPU is reading data from memory.
An external device is inputting data
to the
CPU.
The CPU is in machine cycle one of an
instruction cycle.
The CPU is outputting data to an
external device.
April. i97i
8800b

Table 2-1. ALTAIR 8800b Switches and Indicators -Continued
Indicator Function or Indication
.Aoril. 197i
saCCb
HLTA
STACK
WO
INT
DATA 00-07
WAIT
HLoA
The CPU is in a halt condition.
The address bus contains the address
of the stack pointer.
The CPU is writing out data to an
external device or memory.
The CPU has acknowledged an interrupt
request.
Data from memory, an external device,
or the CPU
The CPU is in await condition.
The CPU has acknowledged ahold
signal.
2-5

2-3. FRONT PANEL SWITCH APPLICATIONS
The following switch applications are intended to familiarize
the operator with the ALTAIR 8800b front panel switches and indica-
tors. Perform the operations in asequential manner as shown in the
following
tables.
2-4. POWER ON SEQUENCE (Table 2-2)
The power on sequence resets the CPU program counter to the first
memory address and places the CPU in await condition at the beginning
of
an instruction cycle.
Table 2-2.
Power On Sequence
Step Function Indication
1Position the
POWER ON/ r~EMR ,
Ml, and WAIT indica-
OFF switch to ON.
tors are on. Some DATA
00-07 indicators may also
be on.
All other indicators
are
off.
2-5. RUN OPERATION (Table 2-3)
The run operation releases the CPU from await condition, and
allows it to execute aprogram. When the run operation is enabled,
all other front panel switches are inactive except the RESET switch.
Table 2-3.
Run Operation
Step Function Indication
1Momentarily position the
\~AIT
indicator is off
I
STOP/RUN switch to RUN.
(or may be dimly lit).
The machine can
now exe-
cute aprogram.
" ~
",-0 Apr~l, 1977
880Gb

2-6. STOP OPERATION (Table 2-4)
The stop operation places the CPU in await condition and allows
the operator to
use the switches on the 8800b front panel.
Table 2-4. Stop Operation
Step Function Indication
1Position the
STOP/RUN WAIT, MEMR, and Ml indicators
switch to
STOP.
are on.
The operator now
I
has control of the front
1panel.
2-7.
EXAMINE MEMORY OPERATION (Table 2-5)
This procedure allows the operator to
select a memory address
and examine its contents.
,
i
I
I
Al and A2 indicators are on,
indicating
memory address 006
8
is being examined. DATA DO
through 07 indicators are dis-
playing the contents of loca-
tion
006
8.
AO through A15 indicators are
off, indicating memory address
location
000
8
is being examined.
DATA DO through 07 indicators
are displaying the contents
of location
000
8.
Function Indication
Table 2-5.
Examine Memory Operation
Position the address
switches
AO-A15
down.
Position the EXAMINE/
EX NEXT switch to
EXAMINE.
2
3Position address
switches
Al and A2
up.
Position the EXAMINE/
EX NEXT switch to
EXAMINE.
4
Step
I
I
I
I
I
Aoril. 1977
880Gb
2-7

2-8. ALTERING MEMORY CONTENTS (Table 2-6)
This procedure allows the operator to select a memory address
and change its contents.
Table 2-6. Altering
Memory Contents
Step Function Indication
1Position address switch
AS up and the remaining
switches
down.
2Position the
EXAMINE/
AS indicator is on, indi-
!
I
EX NEXT switch to EXAMINE
eating memory address 040
8.I
1
DATA DO through 07 indi-
i
I
cators are displaying the
contents
of location 040
8.I
3Position the
AO through I
I
A7 address switches up.
I
I
I
4Position the
DEPOSIT/DEP
DATA DO through 07 indi-
I
I
NEXT to DEPOSIT
cators are on, indicati8g !
the new data that has been
l
I
I
placed in address location
I
040
8.
2-9.
EXAMINE NEXT MEMORY LOCATION (Table 2-7)
This procedure allows the operator to
examine the next sequential
memory location, as determined by the address switches.
Table 2-7.
Examine Next Memory Location
2-8
Step Function Indication
1Position address switches I
AO and AS up, and the re-
maining switches down.
2Position the
EXAMINE/EX
AO and AS indicators are
NEXT switch to EXAMINE
on, indicating memory
!
address 041
8.i
I
April, 1977
880Cb