Mitsubishi M16C/60 Series Mounting instructions

ADVANCED AND EVER ADVANCINGMITSUBISHI ELECTRIC
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY
740
Family
MITSUBISHI
ELECTRIC
Software Manual

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Rev. Rev.
No. date
1.0 First Edition 970829
REVISION DESCRIPTION LIST 740 Family Software Manual
(1/1)
Revision Description

Preface
This software manual is for users of the 740 Family.
Register structures, addressing modes and instructions
are introduced in each section.
The enhanced instruction set with enhanced data and
memory operations enable efficient programming.
Please refer to the “USER’S MANUAL” appropriate
for the hardware device or the development support
tools used.

I
Table of contents
CHAPTER 1. OVERVIEW ............................................................................................ 1
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)..............................................2
2.1 Accumulator (A) ........................................................................................................................2
2.2 Index Register X (X), Index Register Y (Y)........................................................................ 2
2.3 Stack Pointer (S).......................................................................................................................3
2.4 Program Counter (PC) .............................................................................................................4
2.5 Processor Status Register (PS).............................................................................................4
CHAPTER 3. INSTRUCTIONS ....................................................................................6
3.1 Addressing Mode ......................................................................................................................6
3.2 Instruction Set .........................................................................................................................26
3.2.1 Data transfer instructions................................................................................................26
3.2.2 Operating instruction .......................................................................................................27
3.2.3 Bit managing instructions ...............................................................................................28
3.2.4 Flag setting instructions..................................................................................................28
3.2.5 Jump, Branch and Return instructions......................................................................... 28
3.2.6 Interrupt instruction (Break instruction)........................................................................ 29
3.2.7 Special instructions..........................................................................................................29
3.2.8 Other instruction ..............................................................................................................29
3.3 Description of instructions...................................................................................................30
CHAPTER 4. NOTES ON USE...............................................................................102
4.1 Notes on interrupts ..............................................................................................................102
4.1.1 Setting for interrupt request bit and interrupt enable bit......................................... 102
4.1.2 Switching of detection edge........................................................................................ 102
4.1.3 Distinction of interrupt request bit.............................................................................. 103
4.2 Notes on programming........................................................................................................104
4.2.1 Processor Status Register........................................................................................... 104
4.2.2 BRK instruction ..............................................................................................................105
4.2.3 Decimal calculations......................................................................................................105
4.2.4 JMP instruction ..............................................................................................................106
APPENDIX 1. Instruction Cycles in each Addressing Mode ........................ 107
APPENDIX 2. 740 Family Machine Language Instruction Table.................. 173
APPENDIX 3. 740 Family list of Instruction Codes.........................................179
Table of contents

II
Table of contents
<Addressing Mode>
Immediate.................................. 7
Accumulator .............................. 8
Zero Page ................................. 9
Zero Page X ...........................10
Zero Page Y ...........................11
Absolute................................... 12
Absolute X .............................. 13
Absolute Y .............................. 14
Implied ..................................... 15
Relative.................................... 16
Indirect X................................. 17
Indirect Y................................. 18
Indirect Absolute ....................19
Zero Page Indirect .................20
Special Page .......................... 21
Zero Page Bit .........................22
Accumulator Bit ......................23
Accumulator Bit Relatibe.......24
Zero Page Bit Relative..........25
<Instructions>
ADC ..........................31
AND ..........................32
ASL ...........................33
BBC...........................34
BBS ...........................35
BCC ..........................36
BCS...........................37
BEQ ..........................38
BIT ............................39
BMI............................40
BNE...........................41
BPL ...........................42
BRA...........................43
BRK...........................44
BVC...........................45
BVS ...........................46
CLB ...........................47
CLC ...........................48
CLD ...........................49
CLI ............................50
CLT ...........................51
CLV ...........................52
CMP .......................... 53
COM..........................54
CPX...........................55
CPY...........................56
DEC ..........................57
DEX...........................58
DEY...........................59
DIV ............................60
EOR ..........................61
INC............................62
INX ............................63
INY ............................64
JMP ...........................65
JSR ...........................66
LDA ...........................67
LDM ..........................68
LDX ...........................69
LDY ...........................70
LSR ...........................71
MUL ..........................72
NOP ..........................73
ORA ..........................74
PHA...........................75
PHP...........................76
PLA ...........................77
PLP ...........................78
ROL...........................79
ROR .......................... 80
RRF...........................81
RTI ............................82
RTS ...........................83
SBC...........................84
SEB ...........................85
SEC...........................86
SED...........................87
SEI ............................88
SET ...........................89
STA ...........................90
STP ...........................91
STX ...........................92
STY ...........................93
TAX ...........................94
TAY ...........................95
TST ...........................96
TSX ...........................97
TXA ...........................98
TXS ...........................99
TYA .........................100
WIT .........................101

1
OV ERV IEW
1. OVERVIEW
The distinctive features of the CMOS 8-bit microcomputers 740 Family’s software are described
below:
1) An efficient instruction set and many addressing modes allow the effective use of ROM.
2) The same bit management, test, and branch instructions can be performed on the Accu-
mulator, memory, or I/O area.
3) Multiple interrupts with separate interrupt vectors allow servicing of different non-periodic
events.
4) Byte processing and table referencing can be easily performed using the index addressing
mode.
5) Decimal mode needs no software correction for proper decimal operation.
6) The Accumulator does not need to be used in operations using memory and/or I/O.

2
C EN TRAL PROC ESSIN G UN IT
2. CENTRAL PROCESSING UNIT (CPU)
Six main registers are built into the CPU of the 740 Family.
The Program Counter (PC) is a sixteen-bit register; however, the Accumulator (A), Index
Register X (X), Index Register Y (Y), Stack Pointer (S) and Processor Status Register (PS)
are eight-bit registers.
☞Except for the I flag, the contents of these registers are indeterminate after a hardware
reset; therefore, initialization is required with some programs (immediately after reset the I
flag is set to “1”).
Fig.2.1.1 Register Configuration
Accumulator (A)
Index Register X (X), Index Register Y (Y)
2.1 Accumulator (A)
The Accumulator, an eight-bit register, is the main register of the microcomputer.
This general-purpose register is used most frequently for arithmetic operations, data transfer,
temporary memory, conditional judgments, etc.
2.2 Index Register X (X), Index Register Y (Y)
The 740 Family has an Index Register X and an Index Register Y, both of which are eight-
bit registers.
When using addressing modes which use these index registers, the address, which is added
the contents of Index Register to the address specified with operand, is accessed. These
modes are extremely effective for referencing subroutine and memory tables.
The index registers also have increment, decrement, compare, and data transfer functions;
therefore, these registers can be used as simple accumulators.
Negative Flag
Overflow Flag
X Modified Operation Mode Flag
Break Flag (BRK)
Decimal Mode Flag
Interrupt Disable Flag
Zero Flag
Carry Flag
Processor
Status Register(PS)
Program Counter(PC)
Stack Pointer(S)
Index Register Y(Y)
Index Register X(X)
Accumulator(A)
A
X
Y
S
NVTBDI ZC
0
0
0
0
00
0
7
7
7
7
77
7
HPCL
PC

3
2.3 Stack Pointer (S)
The Stack Pointer is an eight-bit register used for generating interrupts and calling subroutines.
When an interrupt is received, the following procedure is performed automatically in the
indicated sequence:
(1) The contents of the high-order eight bits of the Program Counter (PCH) are saved to
an address using the Stack Pointer contents for the low-order eight bits of the address.
(2) The Stack Pointer contents are decremented by 1.
(3) The contents of the low-order eight bits of the Program Counter (PCL) are saved to an
address using the Stack Pointer Contents for the low-order eight bits of the address.
(4) The Stack Pointer contents are decremented by 1.
(5) The contents of the Processor Status Register (PS) are saved to an address using the
Stack Pointer contents for the low-order eight bits of the address.
(6) The Stack Pointer contents are decremented by 1.
The Processor Status Register is not saved when calling subroutines (items (5) and (6) above
are not executed). The Processor Status Register is saved by executing the PHP instruction
in software.
To prevent data loss when generating interrupts and calling subroutines, it is necessary to
save other registers as well. This is done by executing the proper instruction in software while
in the interrupt service routine or subroutine.
The high-order eight bits of the address are determined by the Stack Page Selection Bit.
For example, the PHA instruction is executed to save the contents of the Accumulator.
Executing the PHA instruction saves the Accumulator contents to an address using the Stack
Pointer contents as the low-order eight bits of the address.
The RTI instruction is executed to return from an interrupt routine.
When the RTI instruction is executed, the following procedure is performed automatically in
sequence.
(1) The Stack Pointer contents are incremented by 1.
(2) The contents of an address using the Stack Pointer contents as the low-order eight bits
of the address is returned to the Processor Status Register (PS).
(3) The Stack Pointer contents are incremented by 1.
(4) The contents of an address using the Stack Pointer as the low-order eight bits of the
address is returned to the low-order eight bits of the Program Counter (PCL).
(5) The Stack Pointer contents are incremented by 1.
(6) The contents of an address using the Stack Pointer as the low-order eight bits of the
address is returned to the high-order eight bits of the Program Counter (PCH).
Steps (1) and (2) are not performed when returning from a subroutine using the RTS
instruction. The Processor Status Register should be restored before returning from a
subroutine by using the PLP instruction. The Accumulator should be restored before returning
from a subroutine or an interrupt servicing routine by using the PLA instruction.
The PLA and PLP instructions increment the Stack Pointer by 1 and return the contents of an
address stored in the Stack Pointer to the Accumulator or Processor Status Register, respec-
tively.
☞Saving data in the stack area gradually fills the RAM area with saved data; therefore,
caution must exercised concerning the depth of interrupt levels and subroutine nesting.
CENTRAL PROCESSING UNIT
Stack Pointer (S)

4
2.4 Program Counter (PC)
The Program Counter is a sixteen-bit counter consisting of PCHand PCL, which are each
eight-bit registers. The contetnts of the Program Counter indicates the address which an
instruction to be executed next is stored.
The 740 Family uses a stored program system; to start a new operation it is necessary to
transfer the instruction and relevant data from memory to the CPU.
Normally the Program Counter is used to indicate the next memory address. After each
instruction is executed, the next instruction required is read. This cycle is repeated until the
program is finished.
☞The control of the Program Counter of the 740 Family is almost fully automatic. However,
caution must be exercised to avoid differences between program flow and Program
Counter contents when using the Stack Pointer or directly altering the contents of the
Program Counter.
2.5 Processor Status Register (PS)
The Processor Status Register is an eight-bit register consisting of 5 flags which indicate the
status of arithmetic operations and 3 flags which determine operation.
Each of these flags is described below. Table 2.5.1 lists the instructions to set/clear each flag.
Refer to the section “Appendix 2 MACHINE LANGUAGE INSTRUCTION TABLE” or “3.3
INSTRUCTIONS” for details on when these flags are altered.
[ Carry flag C ]------------------------------------------------------ Bit 0
This flag stores any carry or borrow from the Arithmetic Logic Unit (ALU) after an arithmetic
operation and is also changed by the Shift or Rotate instruction.
This flag is set by the SEC instruction and is cleared by the CLC instruction.
[ Zero flag Z ] ------------------------------------------------------- Bit 1
This flag is set when the result of an arithmetic operation or data transfer is “0” and is
cleared by any other result.
[ Interrupt disable flag I ] ---------------------------------------- Bit 2
This flag disables interrupts when it is set to “1.” This flag immediately becomes “1” when
an interrupt is received.
This flag is set by the SEI instruction and is cleared by the CLI instruction.
[ Decimal mode flag D ] ----------------------------------------- Bit 3
This flag determines whether addition and subtraction are performed in binary or decimal
notation. Addition and subtraction are performed in binary notation when this flag is set to
“0” and as a 2-digit, 1-word decimal numeral when set to “1.” Decimal notation correction
is performed automatically at this time.
This flag is set by the SED instruction and is cleared by the CLD instruction.
Only the ADC and SBC instructions are used for decimal arithmetic operations.
Note that the flags N, V and Z are invalid when decimal arithmetic operations are per-
formed by these instructions.
[ Break flag B ] ----------------------------------------------------- Bit 4
This flag determines whether an interrupt was generated with the BRK instruction. When a
BRK instruction interrupt occurs, the flag B is set to “1” and saved to the stack; for all other
interrupts the flag is set to “0” and saved to the stack.
C EN TRAL PROC ESSIN G UN IT Program Counter (PC)
Processor Status Register (PS)

5
[ X modified operation mode flag T ] ----------------------- Bit 5
This flag determines whether arithmetic operations are performed via the Accumulator or
directly on a memory location. When the flag is set to “0”, arithmetic operations are
performed between the Accumulator and memory. When “1”, arithmetic operations are
performed directly on a memory location.
This flag is set by the SET instruction and is cleared by the CLT instruction.
(1) When the T flag = 0
A ← A * M2
* : indicates an arithmetic operation
A: accumulator contents
M2: contents of a memory location specified by the addressing mode of the
arithmetic operation
(2) When the T flag = 1
M1 ← M1 * M2
* : indicates arithmetic operation
M1: contents of a memory location, designated by the contents of Index
Register X.
M2: contents of a memory location specified by the addressing mode of
arithmetic operation.
[ Overflow flag V ] ------------------------------------------------- Bit 6
This flag is set to “1” when an overflow occurs as a result of a signed arithmetic operation.
An overflow occurs when the result of an addition or subtraction exceeds +127 (7F16) or
–128 (8016) respectively.
The CLV instruction clears the Overflow Flag. There is no set instruction.
The overflow flag is also set during the BIT instruction when bit 6 of the value being tested
is “1.”
☞Overflows do not occur when the result of an addition or subtraction is equal to or
smaller than the above numerical values, or for additions involving values with different
signs.
[ Negative flag N ] ------------------------------------------------- Bit 7
This flag is set to match the sign bit (bit 7) of the result of a data or arithmetic operation.
This flag can be used to determine whether the results of arithmetic operations are positive
or negative, and also to perform a simple bit test.
Table 2.5.1 Instructions to set/clear each flag of processor status register
C EN TRAL PROC ESSIN G UN IT
Processor Status Register (PS)
Flag N
Set instruction
Clear instruction
Flag C
SEC
CLC
Flag Z Flag I
SEI
CLI
Flag D
SED
CLD
Flag B Flag T
SET
CLT
Flag V
CLV

6
Fig.3.1.1 Byte Structure of Instructions
IN STRUC TION S
Addressing mode
3. INSTRUCTIONS
3.1 Addressing Mode
The 740 Family has 19 addressing modes and a powerful memory access capability. When
extracting data required for arithmetic and logic operations from memory or when storing the
results of such operations in memory, a memory address must be specified. The specification
of the memory address is called addressing. The data required for addressing and the
registers involved are described below. The 740 Family instructions can be classified into three
kinds, by the number of bytes required in program memory for the instruction: 1-byte, 2-byte
and 3-byte instructions. In each case, the first byte is known as the “Op-Code (operation
code)” which forms the basis of the instruction. The second or third byte is called the “oper-
and” which affects the addressing. The contents of index registers X and Y can also effect the
addressing.
Although there are many addressing modes, there is always a particular memory location
specified. What differs is whether the operand, or the index register contents, or a combination
of both should be used to specify the memory or jump destination. Based on these 3 types
of instructions, the range of variation is increased and operation is enhanced by combinations
of the bit operation instructions, jump instruction, and arithmetic instructions.
As for 1-byte instruction, an accumulator or a register is specified, so that the instruction does
not have “operand,” which specify memory.
AAAAA
AAAAA
Op-Code
Operand I
Operand II
3-byte instruction Index Register
AAAAA
AAAAA
Op-Code
1-byte instruction
AAAAA
AAAAA
Op-Code
Operand I
2-byte instruction
X
Y
Y

7
IN STRUC TION S
Immediate
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Immediate
Specifies the Operand as the data for the instruction.
ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY,
ORA, SBC
Mnemonic Machine code
∆ADC∆#$A5 6916 A516
Addressing mode
This symbol(#) indicates the Immediate addressing mode.
AAAAAA
AAAAAA
Op-code (69 16 )
Operand (A5
16 )
Memory
(A) ←(A) + (C) + A5 16

8
IN STRUC TION S
Ac c u m u la t o r
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Accumulator
Specifies the contents of the Accumulator as the data
for the instruction.
ASL, DEC, INC, LSR, ROL, ROR
Mnemonic Machine code
∆ROL∆A2A16
Addressing mode
Accumulator
C
Carry flag
bit
7bit 0

9
Ze ro Pa g e
IN STRUC TION S
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Zero Page
Specifies the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
using Operand as the low-order byte of the address
and 0016 as the high-order byte.
ADC, AND, ASL, BIT, CMP, COM, CPX, CPY, DEC,
EOR, INC, LDA, LDM, LDX, LDY, LSR, ORA, ROL, ROR,
RRF, SBC, STA, STX, STY, TST
Mnemonic Machine code
∆ADC∆$40 6516 4016
Addressing mode
4016
0016
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
AAAAAA
AAAAAA
AAAAAA
A
AAAA
A
AAAAAA
FF16
(A) ←(A) + (C) + XX16
Zero page
designation
Data(XX16)
Op-code(6516)
Operand (4016)
Zero page
Memory

10
IN STRUC TION S
Zero Page X
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Zero Page X
Specified the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
the following:
(a) Operand and the Index Register X are added. (If as
a result of this addition a carry occurs, it is
ignored.)
(b) The result of the addition is used as the low-order
byte of the address and 0016 as the high-order
byte.
ADC, AND, ASL, CMP, DEC, DIV, EOR, INC, LDA, LDY,
LSR, MUL, ORA, ROL, ROR, SBC, STA, STY
Mnemonic Machine code
∆ADC∆$5E,X 7516 5E16
Addressing mode
44 16
00 16
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Zero page
Data(XX 16 )
FF
16
Op-code (75 16 )
Operand (5E 16 )
(A) ←(A) + (C) + XX 16
+ E6 16 = 1 44 16
Ignored
Zero page X
designation
Memory
Contents of Index Register X

11
Zero Page Y
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
IN STRUC TION S
Zero Page Y
Specifies the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
the following:
(a) Operand and the Index Register Y are added (if as
a result of this addition a carry occurs, it is ig-
nored).
(b) The result of the addition is used as the low-order
byte of the address and 0016 as the high-order
byte.
LDX, STX
Mnemonic Machine code
∆LDX∆$62,Y B616 6216
Addressing mode
68 16
00 16
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Zero page
Data(XX 16 )
FF
16
Op-code (B6 16 )
Operand (62 16 )
(X) ←XX 16
+ 06 16 = 68 16
Zero page Y
designation
Memory
Contents of Index Register Y

12
IN STRUC TION S
Ab s o lu te
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Absolute
Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by using Operand I as the low-
order byte of the address and Operand II as the high-
order byte.
ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC,
JMP, JSR, LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC,
STA, STX, STY
Mnemonic Machine code
∆ADC∆$AD12 6D16 1216 AD16
Addressing mode
AAAAAA
AAAAAA
Op-code (6D 16 )
Operand I (12 16 )
Operand II (AD 16 )
(A) ←(A) + (C) + XX 16
Data (XX 16 )
Memory
AD12 16
Absolute
designation

13
IN STRUC TION S
Ab s o lu te X
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Absolute X
Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) Operand I is used as the low-order byte of an
address, Operand II as the high-order byte.
(b) Index Register X is added to the address above.
The result is the address in the memory location.
ADC, AND, ASL, CMP, DEC, EOR, INC, LDA, LDY, LSR,
ORA, ROL, ROR, SBC, STA
Mnemonic Machine code
∆ADC∆$AD12, X 7D16 1216 AD16
Addressing mode
+ EE 16 = AE00 16
AAAAA
AAAAA
Op-code (7D 16 )
Operand I (12 16 )
Operand II (AD 16 )
(A) ←(A) + (C) + XX 16
Data(XX 16 )
Memory
AE00 16
Absolute X
designation
Contetns of Index
Register X

14
IN STRUC TION S
Ab s o lu te Y
Addressin g m ode :
Function :
In stru ction s :
Ex a m p le :
Absolute Y
Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) Operand I is used as the low-order byte of an
address, Operand II as the high-order byte.
(b) Index Register Y is added to the address above.
The result is the address in the memory location.
ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA
Mnemonics Machine code
∆ADC∆$AD12, Y 7916 1216 AD16
Addressing mode
+ EE 16 = AE00 16
AAAAAA
AAAAAA
Op-code (79 16 )
Operand I (12 16 )
Operand II (AD 16 )
(A) ←(A) + (C) + XX 16
Data(XX 16 )
Memory
AE00 16
Absolute Y
designation
Contents of Index Register Y