MSC 8009 User manual

USER'S MANUAL
FOR
MSC 8C)09
Infcrmaticn contained in this manual is disclosed in
confidence and may not be duplicated in full or in part by any
person without priolr written approval of Mcneli thic Systems
Corporation. Its sole purpcse is to provide the user with
adequately
detailed documentation so as to efficiently
install, operate', maintain, and order spare parts for the
system supplied. The use of this doc~~ent for all other
purpcses is specifically prohibited.
C:OPYRIGHT © 1980 BY
MONOLITHIC SYSTEMS CORPORATION
84 In~erness Circle East
Englewood, Colorado, 80112
[phone]
PRELIMINARY
2-26-81
~-------------------------,--------- ,---------------------------------,--~

1. 1
1. 2
1. 3
1. 4
1. 5
1. 6
1. 7
1. 8
1. 9
1.10
1. 11
1. 12
1. 13
1• 14
SCOPE
SPECIFICATIONS
FUNCTIONAL DESCRIPTION
Z80A PROCESSOR
MSC 8009
TABLE OF CONTENTS
SECTION 1
INTRODUCTION
ARITHMETIC PROCESSING UNIT (Optional)
1. 5. 1 9511 APU
1. 5. 2 9512 APU
BUS INTERFACE
MODE STATUS REGISTER
1. 7. 1 Bus Exchange Modes
READ/WRITE MEMORY
1. 8. 1 Refresh Cycle
READ ONLY MEMORY
1. 9. 1 Protection PROM
DUAL MAP CONFIGURATION (Optional)
I/O
INTERFACE
1.11. 1 Serial I/O Interfaces
FLOPPY DISK INTERFACE
1.12. 1 Disk Format
~.12. 2 Status Register
1.12. 2. 1 Address Marks
1.12. 2. 2 Cyclic Redundancy Check Characters (CRC)
INTERRUPT
1.13. 1 Non-Maskable Interrupt
SYSTEM CONTROL
1.14. 1 System ~lock
1.14. 2 Power Up
1.14. 3 Memory And I/O Addressing
1.14. 4
Watchdog Timer
1- 1
1- 2
1- 7
1- 7
1- 8
1- 8
1- 8
1- 9
1- 9
1- 9
1-10
1-10
1-10
1-10
1-11
1-11
1-11
1-12
1-12
1-12
1-13
1-13
1-13
1-14
1-14
1-14
1-14
1-15
1-15

2. 1
2. 2
2. 3
2. 4
2. 5
2. 6
SCOPE
INSTRUCTION AND DATA FORMAT
ADDRESS MODES
SECTION 2
zao PROCESSOR
2. 3. 1 Branching Instructions
2. 3. 2 Restart Instruction (RST)
FLAG
2. 4. 1
2. 4. 2
2. 4. 3
Carry Flag (C)
Add/Subtr' act Flag (N)
Parity/Overflow Flag (P/V)
2. 4. 3 .. 1 Arithmetic Operations
2. 4. 3 .. 2 Logical Operations
2. 4. 4 Half-Carry Flag (H)
2. 4. 5 Zero Flag (Z)
2. 4. 6 Sign Flag (S)
OP CODE SUMMARY
2. 5. 1 Mnemonic Operand Symbols
2. 5. 1. 1 8-Bit Operation
2. 5. 1~ 2 16-Bit Operation
2. 5. 2 Flag Symbols
2. 5. 3 8-Bit Data Transfer Group
2. 5. 4 16-Bit Data Transfer Group
2. 5. 5 Exchange t Block Transfer and Search Group
2.
5. 6 8-Bit Ari.thmetic And Logical Group
2. 5. 7 General Purpose Arithmetic And Control Group
2.
5. 8 16-Bit Arithmetic Group
2. 5. 9 Rotate And Shift Group
2. 5.10 Bit Set, Reset And Test Group
2. 5.11 Program Transfer Group
2. 5.12 Call And Return Group
2. 5.13 Input/Output Group
OPCODE FORMAT AND DESCRIPTION
2. 6. 1 8-Bit Data Transfer Group
2. 6. 2 16--Bit Data Transfer Group
,.. 6. 3 Exc!hange, Block Transfer And Search Group
2. 6. 4 8-Bit Arithmetic And Logical Group
2 .. 6. 4. 1 Arithmetic Instructions
2 .. 6. 4. 2 Logical Group
2. 6. 5 General Purpose Arithmetic And Control Group
2. 6. 6 16-Bit Ar'ithmetic Group
2. 6. 7 Rotate And Shift Group
2. 6. 8 Bit Set, Reset And Test Group
2. 6. 9 Program Transfer Group
2. 6.10 Call And Return Group
2. 6.11 Input/Output Group
2- 1
2- 1
2- 1
2- 2
2- 2
2- 3
2- 3
2- 4
2- 4
2- 4
2- 5
2- 5
2- 5
2- 6
2- 6
2- 7
2- 7
2- 8
2- 8
2- 9
2-10
2-11
2-12
2-13
2-14
2-15
2-17
2-18
2-19
2-20
2-21
2-21
2-23
2-35
2-41
2-41
2-53
2-59
2-63
2-67
2-81
2-85
2-94
2-106

3. 1 SCOPE
SECTION 3
MULTI BUS
3. 2 MULTIBUS CONVENTION
3. 3 MULTIBUS CONTROL
3. 3. 1 Bus Contention Resolution
3.. 3. 1. 1 Serial Bus Priority
3. 3. 1. 2 Parallel Bus Priority
3. 3. 1. 3 Bus Exchange Modes
3. 3. 2 Acknowledge Signals
3. 3. 2. 1 Transfer Acknowledge (XACK/)
3.. 3. 2. 2 Advance Acknowledge (AACK/)
3. 4 SPECIFICATIONS
3. 4. 1 Electrical Characteristics
3. 4. 2 Mechanical Characteristics
3. 4. 3 Signal Description
3. 4. 4 Data Transfer Timing
3. 5 MSC 8009 CONFIGURATION
Figure 3- 1
Figure 3- 2
Figure 3- 3
Figure 3- 4
Table 3- 1
Table 3- 2
4. 1
SCOPE
SERIAL-BUS CONTENTION CONFIGURATION
Z80 READ OPERATION
Z80 WRITE OPERATION
MULTI BUS DATA TRANSFER TIMING
MULTI BUS LEVEL SPECIFICATIONS
MULTI BUS ELECTRICAL REQUIREMENTS
SECTION 4
MEMORY
4. 2 R~~ CONFIGURATION
4. 2. 1 Addressing
4. 2. 2
Memory Read
4. 2. 3 Memory Write
4. 2. 4 Refresh Cycle
4. 3
EPROM/R~1 CONFIGU HATION
4. 3. 1 EPROM/HOM Addressing
4. 3. 2
Memory Protect
4. 4 DUAL MAP CONFIGURATION (OPTIONAL)
Table 4- 1
Table
4- 2
PROGRAM ~IEMORY JUMPER CONNECTIONS
MEMORY ALLOCATION
3- 1
3- 1
3- 2
3- 2
3- 3
3- 4
3- 4
3- 5
3- 5
3- 8
3- 8
3- 8
3- 8
3-10
3-11
3-13
3- 3
3- 6
3- 7
3-14
3- 9
3-15
4- 1
4- 1
4- 2
4- 2
4- 2
4- 3
4- 4
4- 4
4- 5
4- 5
4- 3
4- 6

SECTION 5
SERIAL I/O INTERFACE
5. 1 SCOPE 5- 1
5. 2
CONFIGURING THE SERIAL I/O PORT 5- 1
5. 2. 1 Terminal/Communication Configuration 5- 1
5. 2. 2 Programmable Timer Configuration 5- 1
5. 2. 2. 1
BAUD Rate Configuration 5- 5
5. 2. 3 Clock Configurations
5- 5
5. 2. 4
EIA RS·-232-C Configuration 5- 6
5. 2. 5 TTL Conflguration 5- 6
5. 2. 6 Current. Loop Operation 5- 1
5. 2. 1 Interrupt Configuration 5- 1
5. 3 PROGRAMMING THE SERIAL I/O INTERFACE 5- 9
5. 3. 1
Initialization 5- 9
5. 3. 2 Clock Set
5- 9
5.
3. 3 Control ~lord Programming 5- 9
5
.. 3. 3. 1 Mode Instruction 5-11
5. 3. 3. 2 Command Instruction 5-11
5. 3. 4
Status Word Format 5-13
5
.. 3. 4. 1 Parity Error 5-13
5. 3. 4. 2 Overrun Error 5-14
5
.. 3. 4. 3 Framing Error 5-14
5. 4
DATA COMMUNICATION 5-14
5. 4. 1
Asynchl"onous Transmission 5-14
5. 4. 2 Asynchronous Receive 5-14
5. 4. 3 Synchronous Transmission 5-15
5. 4. 4 Synchronous
Rece i ve 5-15
5. 5
TIMER INTERFACE 5-17
5.5. 1 JJJode Definitions 5-18
5
.. 5. 1. 1 HODE 0 - Interrupt On Tenninal Count 5-19
5.. 5. 1. 2 MODE 1 - Progralmnable One Shot 5-20
5. 5. 1. 3 MODE 2 - Rate Generator 5-21
5. 5. 1. 4
MODE 3 - Square Wave Generator 5-22
5. 5. 1. 5 MODE 4 - Software Triggered Strobe 5-23
5. 5. 1. 6 MODE 5 - Hardware Trigger Strobe 5-24
5. 5. 2
On-The--FlY Readout 5-25
5. 5. 3
BAUD Rate Generator 5-25
Figure
5-
Figure 5- 2
Figure
5- 3
Figure 5- 4
Figure
5- 5
Figure
5- 6
Figure 5- 1
Figure 5- 8
Figure
5- 9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
CONTROL WORD SEQUENCE
MODE INSTRUCTION CONTROL WORD FORMAT
COMMAND INSTRUCTION CONTROL WORD FORMAT
STATUS WORD FORMAT
SYNC CHARACTER TRANSMISSION
8253 INTERVAL TIMER CONTROL WORD FORMAT
MODE 0 TIMING DIAGRAM
MODE 1 TIMING DIAGRAIJJ
MODE 2 TIMING DIAGRAM
MODE 3 TIMING DIAGRAM
MODE 4 TllV1ING DIAGRAM
MODE 5 TIMING DIAGRAM
BAUD RATE GENERATOR ROUTINE
5- 8
5-10
5-12
5-13
5-16
5-17
5-19
5-20
5-21
5-22
5-23
5-24
5-26

Table
5-
SERIAL 1/0 CABLE CONNECTION FOR
DATA COM~1UNICATIONS EQUIPMENT (DCE)
Table 5- 2 SERIAL 1/0 CABLE CONNECTION FOR
DATA COMMUNICATIONS EQUIPMENT (DTE)
Table
5- 3
SERIAL I/O PORT CONFIGURATION
Table
5- 4
PRCXJ RA]-1MABLE TIME R SIGNALS
Table
5- 5
8253 TIMER PORT ADDRESSES
Table
5- 6
8253 TIMER REGISTER BAUD RATE
VALUES
SECTION 6
FLOPPY-DISK FORMATTER/CONTROLLER
6. 1 SCOPE
6. 2 DESCRIPTION
6. 3 CONTROL REGISTERS
6. 3. 1 Command Hegister
6. 3. 1. 1 Unit Register
6. 3. 1. 2 Command Register
6. 3. 2 Status Register
6. 3. 3 Track Register
6. 3. 4 Sector Register
6. 3. 5 Data Register
6. 4 COMHAND STRUCTURE
6. 4. 1 Head Positioning Commands (Type 1)
6. 4. 2 Sector Comnands (Type 2)
6. 4. 3 Track Commands (Type 3)
6. 4. 4 Reset Interrupt (Type 4)
6. 4. 5 Write Precompensation
6. 5 FORMATTING THE DISK
6. 6. 1 Shugart Drives
6. 6. 1. 1 Gaps
6. 6. 1. 2 Address Marks
6. 6. 1. 3 Cyclic Redundancy Check Character
6. 6. 1. 4 Setting Up The Disk
6. 6. 2
IBM Format
Figure 6- 1
Figure
6- 2
Figure 6- 3
Figure 6- 4
Figure 6- 5
Figure 6- 6
Figure 6- 7
Figure 6- 8
Figure 6- 9
Figure 6-10
6. 6. 2. 1 IBM 3740 (Single Density)
6. 6. 2. 2 IBM System 34 (Double Density)
COMMAND FtOUTINE
STATUS REGISTER READ
DISK SECTOR FORMAT
TRACK SEEK FROM TRACK 00
TRACK SEEK
SECTOR READ ROUTINE
SECTOR WRITE ROUTINE
READ ADDRESS ROUTINE
RESET INTERRUPT ROUTINE
DISK INITIALIZATION ROUTINE
5-
?
<-
5- 3
5- 4
5- 4
5-25
5-25
6-
1
6- 1
6-
1
6-
4
6-
4
6-
4
6-
4
6- 8
6- 8
6- 8
6- 9
6- 9
6-11
6-11,.
6-15
6-15
6-15
6-17
6-18
6-19
(CRC)
6-19
6-19
6-20
6-20
6-21
6-
3
6- 5
6-17
6-22
6-24
6-26
6-28
6-30
6-32
6-33

Table 6- 1
Table
6- 2
Table 6- 3
Table 6- 4
Table 6- 5
Table 6- 6
Table
6- 7
7. 1
SCOPE
DRIVE DESIGNATION
HEAD POSITION STATUS
READ/WRITE STATUS
FLOPPY-DISK COMMAND SUMMARY
FORMATTER/CONTROLLER CONTROL BYTES
GAP DEFINITIONS
ADDRESS MARK DEFINITION
SECTION 7
INTERRUPT
7. 2 Z80 INTERRUPT CONTROL
7. 3 8214 INTERRUPT CONTROLLER
7. 3. 1 Initialization
7. 3. 2 MULTIBUS Interrupt
7. 3. 3 Progranming Multi-Level Interrupts
7. 4 8214 PRIORITY INTERRUPT CONTROLLER
7. 4. 1 Address And Bit Assignments
7. 4. 2 Vectors
7. 5 NON-MASKABLE INTEHRUPT (NMI)
Table 7- 1
DATA BIT FUNCTIONS FOR OUTPUT TO
INTERRUPT CONTROU.ER (Device Code D7)
8. 1 SCOPE
8. 2 SYSTEM DESCRIPTION
SECTION 8
THEORY OF OPERATION
8. 2. 1 Local Control Bus
8. 2. 1. 1 MULTIBUS Control
8. 2. 2 Local Address Bus
8. 2. 2. 1 MULTIBUS Addressing
8. 2. 3 Data Channel
8. 2. 4 Z80 Processor
8. 2. 5 Floppy Disk Formatter/Controller
8. 2. 6 Arithmetio Processing Unit (APU)
8. 2. 7 System Clock
6- 1
6- 6
6- 7
6-10
6-16
6-18
6-19
7- 1
7- 1
7- 2
7- 4
7- 4
7- 5
7- 6
7- 7
7- 7
7- 8
7- 3
8- 1
8- 1
8- 1
8- 1
8- 3
8- 3
8- 3
8- 3
8- 4
8- 4
8- 5

8. 3 SYSTEM OPERATION
8. 3. 1 Wait Operation
8. 3 .. 1. 1 Watchdog Timer
8. 3. 2 OP Fetch Cycle
8. 3. 3 Memory Read Or Write
8. 3. 3. 1 Address Decoding
8. 3. 4 1/0 Cycles
8. 3. 4. 1 Arithmetic Processor Cycles
8. 3. 5 Disk Formatter/Controller
8. 3. 5. 1 Register Selection
8. 3. 5. 2 Clock Circuit
8. 3. 5. 3 Data Exchange
8. 3. 5.4 Disk Read
8. 3. 5. 5 Disk Write
8. 3. 5. 6 Head Loading Delay
8. 3. 6 Acknowledge Cycle
8. 3. 7 Interrupt Request
8. 3. 7. 1 Non-Maskable Interrupt
8. 3. 8 HALT Request
8. 3. 9 System Reset
8. 4 SYSTEM CONTROL
8. 4. 1 Bus State Machine
8. 4. 1 .. 1 Bus Exchange
8. 4. 2 Memory State Machine
Figure 8- 1
Table 8- 1
Table
8- 2
9. 1 SCOPE
8. 4. 2. 1 Refresh
Z80 MICROPROCESSOR
CLOCK RATE CONFIGURATION
SYSTEM CONTROL PROM SIGNAL IDENTIFICATION
SECTION 9
ARITHMETIC PROCESSOR UNIT
g. 2 CAPABILITIES
9. 2. 1 I/O Addressing
9. 3
9511 ARITHMETIC PROCESSOR UNIT
9. 3. 1 Initialization
9. 3. 2 Stack Control
9. 3. 3 Data Format
9. 3. 3. 1 Command Format
9. 3. 3. 2
Status Register
9. 3. 3. 3 Floating Point Format
8- 6
8- 6
8- 6
8- 7
8- 7
8- 8
8- 8
8- 8
8- 9
8- 9
8-10
8-10
8-10
8-11
8-11
8-12
8-12
8-12
8-13
8-15
8-15
8-15
8-16
8-17
8-17
8- 2
8- 5
8-14
9- 1
9- 1
Q- 1
9- 2
9- 2
9- 2
9- 2
9- 4
9- 4
9- 5

9. 4 9511 INSTRUCTIONS
9. 4. 1 Data And Stack Manipulation Operations
g. 4. 2 16-Bit F:ixed-Point Operations
9. 4. 3 32-Bit F:ixed-Point Operations
9. 4. 4 32-Bit Floating-Point Primary Operations
9. 4. 5 32-Bit Floating-Point Derived Operations
9. 5 9511 OP CODE FORM1\T:S
9. 6 9512 ARITHMETIC PROCESSOR UNIT
9. 6. 1 Stack Control
9. 6. 1. 1
Double Precision
9. 6. 2 Co~~and Format
9. 6. 3
Status Register
9. 7
9512 INSTRUCTIONS
9. 7. 1 Data And Stack Manipulation Operations
9. 7. 2 Single Precision Operations
9. 7. 3. Double Precision Operation
9. 8 9512 OP CODE FORMLATS
Figure 9- 1
Table
9- 1
Table 9- 2
Table 9- 3
Appendix A
Appendix B
Appendix C
Appendix D
303-0271-000
305-0271-000
9511 INITIALIZATION SEQUENCE
STACK CONFIGURATIONS
STATUS BIT DEFINITION
STACK CONFIGURATIONS
APPENDICES
MSC 8009 PIN ASSIGNMENT
MSC 8009 JUMPER REQUIREMENT
FLOPPY-DISK JUMPER CONFIGURATION
9511 APPLICATION NOTE
DRAWINGS
MSC 8009 BOARD LAYOUT
MSC 8009 SCHEMATIC
9- 6
9- 7
9- 8
9- 8
9- 9
9- 9
9-14
9-34
9-34
9-35
9-35
9-36
9-38
9-39
9-40
9-40
9-43
9- 3
9-10
9-37
9-41

SECTION '1
INTRODUCTION
1.1 SCOPE
The Monolithic Systems Corporation MSC 8009 is a single-board OEM
computer that is dlirectly compatible with the industry standard
MULTIBUS* . As software development is a major cost of any computer
system,
the 8080 software compatibility of the MSC 8009 provides an
advanced, high-speed, next-generation system without incurring the costs
and delays associatedl with developing new software. New systems can now
be designed taking full advantage of the Z80A* instruction set and
optional floating-point arithmetic unit.
The MSC 8009 operates in a multimaster system with either parallel or
serial priority resolution. An on-board bus plus the MULTIBUS structure
allows other operations to proceE~d on the MULTIBUS while the Z80A
processor uses local memory and 1/0 devices. Since the on-board memory
and 1/0 resources are extensive, bus access is usually needed only for
communication between tasks. System throughput with multiple masters is
greatly enhanced because of the light MULTI BUS traffic load. MULTIBUS
compatibility means that the MSC 8009 can be used either to expand
existing SBC 80-based systems or as the basis of a new design.
An on-board floppy-disk formatter/controller in addition to two serial
ports will increase' the computing power for most applications. Via a
17q3 Floppy-Disk FormatterlController, the floppy-disk interface of the
MSC 800Q offers a soft-sector format that can be made IBM compatible
with
the proper softw'are. Variable length sectors and the self-clocking
feature of the 1793 means more data per track. The system uses Z80
block 1/0 instructions to transfer data. Write pre-compensation reduces
error rate; and the data separator is crystal controlled. Programmable
stepping rates from 3 to 15 milliseconds lets the MSC 8009 operate with
drives having different track-to-track access time.
*MULTIBUS is a registered trademark of Intel
Corporation
Z80A is a registered trademark of Zilog Inc.
100-0123-001
1-1