MYiR FZ3 User manual

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FZ3 Deep Learning Accelerator Card
Hardware Manual
FZ3 Deep Learning
Accelerator Card
Hardware Manual
Version V1.0

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FZ3 Deep Learning Accelerator Card
Hardware Manual
Revision History
Version Description Date
V1.0 Initial Version 2020/06/23

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FZ3 Deep Learning Accelerator Card
Hardware Manual
Table of contents
Table of contents ............................................................................................................... 3
Chapter 1 Overview ........................................................................................................... 5
1.1 Product Description ....................................................................................................... 5
1.2 Picture.............................................................................................................................. 5
Chapter 2 SOC introduction ............................................................................................. 6
2.1 SoC features..................................................................................................................... 6
2.2 SoC BANK ......................................................................................................................... 8
Chapter 3 Onboard Resources ......................................................................................... 9
3.1 Hardware resources .................................................................................................... 9
3.2 Boot Mode & JTAG Mode ......................................................................................... 10
3.3 DDR4 ........................................................................................................................... 10
3.4 Storage ........................................................................................................................ 10
3.4.1 SPI Flash .............................................................................................................. 10
3.4.2 eMMC ................................................................................................................... 12
3.5 Erthernet ...................................................................................................................... 13
3.6 USB .............................................................................................................................. 14
3.7 Multi-channel programmable clock generator ....................................................... 15
3.8 External watchdog and reset .................................................................................... 15
Chapter 4 Hardware Introduction ................................................................................... 17
4.1 Interface summary ........................................................................................................ 17
4.2 PS Unit ........................................................................................................................... 18
4.2.1 DisplayPort ........................................................................................................... 18
4.2.2 PCIe 1x ................................................................................................................. 18
4.2.3 Erthernet ............................................................................................................... 18
4.2.4 USB3.0 HOST ..................................................................................................... 18
4.2.5 TF Card ................................................................................................................ 18
4.2.6 MicroUSB to UART ............................................................................................. 18
4.2.7 JTAG ..................................................................................................................... 18

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4.3 PL Unit ........................................................................................................................... 19
4.3.1 MIPI-CSI ............................................................................................................... 19
4.3.2 BT1120 ................................................................................................................. 19
4.3.3 Expansion IO ....................................................................................................... 20
4.4 Other interface .............................................................................................................. 21
4.4.1 Power input .......................................................................................................... 21
4.4.2 RTC bat connector.............................................................................................. 21
4.4.3 Fan connector...................................................................................................... 21
4.4.4 CAN ....................................................................................................................... 22
4.4.5 RS485 ................................................................................................................... 22
Chapter 5 Mechanical parameters ................................................................................. 23
Appendix 1 Warranty & Technical Support Services .................................................. 24

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FZ3 Deep Learning Accelerator Card
Hardware Manual
Chapter 1 Overview
1.1 Product Description
The FZ3 Deep learning computing card is an embedded intelligent AI development platform
with Xilinx XCZU3EG as the core launched by Shenzhen Myir Technology Co., Ltd. Using
Xilinx's latest 16nm process-based Xilinx Zynq UltraScale + MPSoC platform, integrated
quad-core Cortex ™ -A53 processor, dual-core Cortex ™ -R5 real-time processing unit
and Mali-400 MP2 graphics processing unit and 16nm FinFET + programmable logic The
heterogeneous processing system has high performance, low power consumption, high
expansion and other characteristics, and can meet various needs in industrial design.
At the same time, Shenzhen Myir Technology Co., Ltd. provides a variety of mature
hardware solutions, provides a wealth of embedded operating system software resources,
through supporting design tools to help embedded developers give full play to the synergy
of hardware and software to achieve innovation beyond traditional architecture design.
1.2 Picture
Figure 1-2
Product difference
FZ3A 2GB DDR4 64bit 2400Mbps
FZ3B 4GB DDR4 64bit 2400Mbps

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Chapter 2 SOC introduction
2.1 SoC features
The XCZU3EG used in this development platform belongs to the Zynq UltraScale +
MPSoC series SoC, integrating ARM quad-core Cortex-A53 (PS), dual-core Cortex-R5
(PS), Mali-400 MP2 graphics processing unit and Kintex Ultrascale + FPGA (PL). The
quad-core Cortex-A53 has powerful computing capabilities, the dual-core Cortex-R5 can
be used for real-time processing applications, the Mali-400 MP2 can be used to
accelerate graphics processing, and the FPGA is fully programmable. With the
expandable I / O ports, it can adapt to a variety of application AI development scenarios.
The main chip of the AI development platform uses Xilinx XCZU3EG-SFVC784 devices
with a speed grade of -1 (MYC-CZU3EG SOM is designed to support all speed grades of
XCZU3EG-SFVC784 devices). XCZU3EG-SFVC784 supports 1.5GHz (max -1) APU
speed, 600MHz (max -1) RPU speed, 667MHz (max -1) GPU speed, and DDR4 speed
up to 2400Mbps. The XCZU3EG-SFVC784 device has the following resources:
Figure 2-1

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Hardware Manual
 Processing System (PS)
 Processor Core: Quad-core ARM Cortex-A53 MPCore up to 1.5GHz
 Maximum Frequency: 1.5Ghz
 APU: L1 Cache 32KB I / D per core, L2 Cache 1MB.
 RPU：L1 Cache 32KB I / D per core.
 On-Chip Memory: 256 KB
 External Memory: LPDDR4，DDR4，DDR3, DDR3L LPDDR3 with ECC
 External Static Memory: 2x Quad-SPI, NAND, NOR
 DMA Channels: 8 Programmable Logic（4 for PL）
 Peripherals:
 High speed: PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode
Gigabit Ethernet.
 Regular speed: 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x
32b GPIO
 Programmable Logic (PL)
MYC-XCZU3EG
Logic Equivalent Xilinx Kintex Ultrascale+®FPGA
Programmable Logic Cells 154K
Look-Up Tables 71K
Flip-Flops 141K
Block RAM Distributed RAM 1.8Mb /
Block RAM 7.6Mb
DSP slice 360
AMS-System Monitor 1
Table 2-1

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2.2 SoC BANK
Figure 2-2 XCZU3EG SFVC784 Banks
 BANK 0 : humidity Sensor, XADC , Other configuration signals
 BANK 24：PL HD BANK, 24Pin(12 pairs of differential signal)
 BANK 25：PL HD BANK, 24Pin(12 pairs of differential signal)
 BANK 26：PL HD BANK, 24Pin(12 pairs of differential signal)
 BANK 44：PL HD BANK, 24Pin(12 pairs of differential signal)
 BANK 64：PL HP BANK, 52Pin(26 pairs of differential signal)
 BANK 65：PL HP BANK, 52Pin(26 pairs of differential signal)
 BANK 66：PL HP BANK, 52Pin(26 pairs of differential signal)
 BANK 500: PS side, MIO[00:25] 26pin，multiplex pin
 BANK 501: PS side, MIO[26:51] 26pin，multiplex pin
 BANK 502: PS side, MIO[52:77] 26pin，multiplex pin
 BANK 503: PS side, PS configuration pin, includeJTAG boot configuration reset, etc.
 BANK 504: PS side, DDR BANK
 BANK 505: PS side, MGTR BANK

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FZ3 Deep Learning Accelerator Card
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Chapter 3 Onboard Resources
3.1 Hardware resources
Figure 3-1
 Hardware resources
 2GB/4GB DDR4 SDRAM（64bit 2400Mbps）
 8GB eMMC
 32MB QSPI
 Gigabit Ethernet
 RS485*1，CAN*1
 Peripheral interface and resources
 1 Channel SD/MMC interface
 1 Channel USB2.0 tyepA，1 Channel USB3.0 typeA
 1 Channel RJ45 Ethernet interface
 1 Channel Mini Displayport interface
 1 Channel PCIe x1 interface
 1 system reset key，1 FPGA reset key

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FZ3 Deep Learning Accelerator Card
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 1 Channel MIPI-CSI interface，1 Channel BT1120 interface
 1 Channel JTAG interface，1 Channel USB to UART debug interface
 2 Channel 40PIN 2.54mm spacing IO expander
 4 onboard LED status indicators
3.2 Boot Mode & JTAG Mode
The development board provides two boot modes by default. Users can select to boot the
system from the TF CARD or the QSPI flash. For detailed information, refer to the table
below.
Name PS_MODE0 PS_MODE1 PS_MODE2 PSMODE3
SW1 M0 M1 M2 /
JTAG ON ON ON /
QSPI32 ON OFF ON /
SD1 OFF ON OFF /
eMMC ON OFF OFF /
Table 3-2
PS: OFF=1.ON=0
3.3 DDR4
The development Board incorporates four Micron DDR4 memory chips
(MT40A256M16LY-062E IT:F) forming a 256M x 64-bit interface with a total of 2GB
RAM(optional 4GB). The DDR4 memorys are connected to the memory controller in the
PS of the Zynq® UltraScale+™ MPSoC, which supports access speed up to 2400
MT/s。
3.4 Storage
3.4.1 SPI Flash