National Semiconductor ADC122S101 User manual

National Semiconductor August 2005
Rev -
Evaluation Board User's Guide
12-, 10- and 8-Bit General Purpose
Analog-to-Digital Converters with Input Multiplexer
ADC122S101 / ADC102S101 / ADC082S101
ADC122S051 / ADC102S051 / ADC082S051
ADC122S021 / ADC102S021 / ADC082S021
ADC124S101 / ADC104S101 / ADC084S101
ADC124S051 / ADC104S051 / ADC084S051
ADC124S021 / ADC104S021 / ADC084S021
© 2005 National Semiconductor Corporation.
1 http://www.national.com

Table of Contents
1.0 Introduction.............................................................................................................................3
2.0 Board Assembly .....................................................................................................................3
3.0 Quick Start..............................................................................................................................3
4.0 Functional Description............................................................................................................4
4.1 Input (signal conditioning) circuitry............................................................................4
4.2 The ADC reference ...................................................................................................4
4.3 ADC clock circuit .......................................................................................................4
4.5 Digital Data Output....................................................................................................4
4.6 Power Supply Connections .......................................................................................4
4.7 Power Requirements.................................................................................................5
4.8 Analog Inputs ............................................................................................................5
5.0 Installing and Using the ADCxx1S101 Evaluation Board .......................................................5
5.1 Software Installation ..................................................................................................5
5.2 Setting up the ADCxx1S101 Evaluation Board .........................................................5
5.2.1 Board Set-up .............................................................................................5
5.2.2 Quick Check of Analog Functions.............................................................5
5.2.3 Quick Check of Software and Computer Interface Operation...................5
5.2.4 Getting Consistent Readings.....................................................................6
5.2.5 Troubleshooting.........................................................................................6
6.0 Evaluation Board Specifications.............................................................................................6
7.0 Hardware Schematic..............................................................................................................7
8.0 ADCxx1S101 Evaluation Board Bill of Materials....................................................................8
A1 Summary Tables of Test Points and Connectors ...................................................................9
2 http://www.national.com

1.0 Introduction The board inputs are provided at BNC1 and BNC2.
Jumper headers JP1 and JP3 allow these inputs to be
either a.c. or d.c. coupled to the DUT. Provision is made
to adjust the DUT supply voltage (measured at TP1) with
potentiometer VR1.
These ADC Design Kits (consisting of one of these
evaluation boards: ADC12xS101, ADC10xS101,
ADC08xS101, ADC12xS051, ADC10xS051,
ADC08xS051, ADC12xS021, ADC10xS021,
ADC08xS021 and WaveVision4 hardware, where "x" in
the device types here could be a 2 or a 4, indicating the
number of multiplexer inputs) is designed to ease
evaluation and design-in of these National
Semiconductor Analog-to-Digital Converters. These
evaluation boards allow the desivgner to evaluate product
performance in a choice of two ways: in standalone mode
with a logic analyzer and appropriate software (including
National's WaveVision software), or with a personal
computer and WaveVision4 hardware and software.
VR2 is used to set the input offset.
2.0 Board Assembly
These Evaluation Boards come fully assembled and
ready to use. Refer to the Bill of Materials for a
description of components, to Figure 1 for major
component placement and to Figure 2 for the Evaluation
Board schematic.
3.0 Quick Start
Refer to Figure 1 for locations of test points and major
components.
Reference in this Guide to DUT is meant to refer to the
particular device for which you have the evaluation board.
1. Connect the evaluation board to the Capture Board
(order number WAVEVSN BRD 4.0). See the
Capture Board Manual for operation of that board.
For operation with a computer system, this evaluation
board should be coupled to a WaveVision4 data capture
board (National part number WAVEVSN BRD 4.0) using
the WaveVision software operating under Microsoft
Windows. The analog signal presented to the DUT is
captured by the WaveVision4 data capture board, and
displayed on the computer screen as a dynamic
waveform, FFT, and/or histogram. The software also
computes and displays dynamic performance in the form
of SNR, SINAD, THD, SFDR, and ENOB.
2. Connect a clean power supply to the terminals of
connector P1. Adjust power supply to a voltage of
±5.5V to ±5.7V before connecting it to the board.
3. Connect a voltmeter to TP1 and use VR1 to set the
DUT analog supply voltage for the desired value
between +2.7V and +5.0V.
4. Set the jumper to short pins 1 and 2 of JP6 and be
sure there is a clock oscillator of the appropriate
frequency at Y1.
Important Note: The evaluation boards for all of these ADCs
look identical. The actual device placed on your evaluation
board can be identified by the label on the board and verified
by looking at the DUT (Device Under Test) top mark. The
devices have the following top marks:
5. Put a jumper between pins 1 and 2 of JP1 and pins
1 and 2 of JP2.
6. Connect a signal, through an appropriate bandpass
filter, to BNC1. The peak-to-peak amplitude of this
signal at TP6 should be the same as or just under
the power supply voltage setting.
Device Top Mark
ADC082S101 X22C
ADC082S051 X04C
ADC082S021 X16C 7. Connect a USB cable between the WaveVision
Capture Board and the PC.
ADC084S101 X25C
ADC084S051 X10C 8. Run the WaveVision 4 software and click on
Settings, then click on Capture. Under "Board Type"
select "WaveVision 4.0 (USB)".
ADC084S021 X19C
ADC102S101 X23C
ADC102S051 X05C 9. Under "Communication" press the "Test" button. If
you get a "Communication Failed" message, check
all connections and be sure the power supply is on.
ADC102S021 X17C
ADC104S101 X26C 10. If the appropriate sample rate (not clock rate) is not
reported, check to be sure the clock signal has
adequate amplitude and repeat the previous step.
ADC104S051 X11C
ADC104S021 X20C
ADC122S101 X24C 11. Click "Accept" then gather data by pressing F1 on
the keyboard. Perform an FFT on the data by
clicking on the FFT tab.
ADC122S051 X06C
ADC122S021 X18C
ADC124S101 X27C
ADC124S051 X12C See the WaveVision Capture Board Manual for complete
data gathering instructions.
ADC124S021 X21C
The signal at the Analog Input to the board is digitized
and is available at FutureBus connector J2.
3 http://www.national.com

J2
Y1
BNC1
BNC2
BNC3
JP1
JP3
National Semiconductor
G/P ADC, MSOP, Evaluation Board
Rev. 1.1
JP5
BNC1
BNC2
BNC3
CLK INPUT
GND
TPG4
LA1
VR2
VR1
P1
GND
TPG1
GND
TPG2
TP8
+5.5V IN 1
TP6
Input1
Input2
TP7
GND
TPG3
U2, U3, U4
TP1
+V
JP6
INPUT 2
INPUT 1
POWER
L1
L2
TP2 TP5 TP4 TP3
JP2
JP4
VR2
Offset
Adjust
TP6
INPUT 1
Test Point
VR1
VA Supply
Adjust
TP8
+5.5V Input
Test Point
JP6
Clock
Select
BNC3
Ext. Clock
Connection
BNC1
INPUT 1
Connection
BNC2
INPUT 2
Connection
JP2
Input 1 Chan
Select
TP2, TP3,
TP4, TP5
Serial Lines
Test Points
TP7
INPUT 2
Test Point
JP6
Clock
Select
JP1
INPUT 1
AC/DC Couple
JP3
INPUT 2
AC/DC Couple
JP2
Input 1 Chan
Select
Figure 1. Major Components and Test Points of the Evaluation Board
4.0 Functional Description 4.3 ADC Input Bias
The Evaluation Board component locations are shown in
Figure 1. The board schematic is shown in Figure 2.To maximize ADC performance it is necessary that the
input signal swing cover nearly the entire ADC input
range. If the input biasing is not at the center of the signal
swing, it will not be possible to get maximum signal swing
without clipping of the signal, at which point there will be
excessive distortion.
4.1 Input (signal conditioning) circuitry
The input signal to be digitized should be applied to BNC
connector BNC1 or to BNC2, or to both through (an)
appropriate filter(s). These 50 Ohm inputs are intended to
accept a low-noise sine wave signal of peak-to-peak
amplitude up to the power supply level. To accurately
evaluate the ADC dynamic performance, the input test
signal should be a single frequency passed through a
high-quality band pass filter as described in Section 5.0.
VR2 is provided to allow adjustment of the input bias
point when a.c. input coupling is used. VR2 should be
adjusted to provide a d.c. voltage at TP6 and TP7 that
are one half the DUT supply voltage at TP1.
4.4 ADC clock circuit
The input signal may be either a.c. or d.c. coupled to the
DUT with the setting of jumpers on J1 and JP3. See
schematic Figure 2.
The clock signal applied to the ADC can come from
BNC3 or from an on-board oscillator at position Y1 or Y2.
Y1 is for a through-hole TTL oscillator, while Y2 is for a
surface mounted TTL oscillator. Only one oscillator
should be mounted at a time and either an oscillator or
an external generator should be connected. JP6 is used
to select the oscillator source. Shorting pins 1 and 2 of
JP6 selects the on-board oscillator, while shorting pins 2
and 3 selects the oscillator signal at BNC3.
4.2 The ADC reference
The reference voltage for the DUT is the device supply
voltage. Therefore, adjusting this voltage will change the
full scale range of the DUT. Since the operational supply
voltage range of the these ADCs is 2.7V to 5.25V, this is
also the range of the reference voltage.
4 http://www.national.com

4.5 Digital Data Output. input to the evaluation board when evaluating sinusoidal
signals to be sure there are no unwanted frequencies
(harmonics and noise) presented to the ADC. It is
important to realize that no frequency generator or
synthesizer produces a pure enough sine wave to
evaluate an A/D Converter without the use of a good
filter. If the WaveVison4 capture board is used, a USB
cable must be connected between the WaveVision4
Capture Board and the host computer. See the
WaveVision4 Capture Board User's Guide for details.
The digital output data from the DUT is available at
Header LA1 for connection to a logic analyzer. Data is
transferred over FutureBus J5 for use with the
WaveVision4 data capture board.
4.6 Power Supply Connections
Power to this board is supplied through power connector
J6. The only Voltage needed for the evaluation board is a
single +5.5V to +5.7V supply.
5.1 Software Installation
When using this evaluation Board with the WaveVision4
Capture Board, the +5V logic power supply for that
Capture board and the +5V of the DUT evaluation board
are connected together through pins A1, B1, A2 and B2
of J2. Diode D1 between P1 and the WaveVision4 board
is meant to prevent the higher voltage at DUT board P1
from getting to the WaveVision4 board. Providing the
+5.5V to +5.7V to the DUT board will provide +5V to the
WaveVision4 board through D1 and the WaveVision4
board pins A1, B1, A2 and B2 of J2.
The WaveVision4 software provided requires about 6
Megabytes of hard drive space, including the Java files,
and runs under Windows. See the WaveVision4 Capture
Board Users' Guide for WaveVision4 software installation
instructions.
5.2 Setting up the Evaluation Board
This evaluation package was designed to be easy and
simple to use, and to provide a quick and simple way to
evaluate the DUT. The procedures given here will help
you to properly set up the board.
4.7 Power Requirements 5.2.1 Board Set-up
Refer to Figure 1 for locations of the major components
on the board.
Voltage and current requirements for the DUT Evaluation
Board are 1. Connect The evaluation board to a WaveVision4
Capture Board, WAVEVSN BRD 4.0.
•Pin 1 of P1: +5.5V to 5.7V at 50 mA
•Pin 2 of P1: Ground 2. Connect the desired jumper to JP1, JP2, JP3 and
JP4. (See Section 4.8).
4.8 Analog Inputs 3. Connect power to the board per requirements of
paragraph 4.7.
The evaluation board input channel is composed of
termination components and a user choice of a.c. or d.c.
signal coupling to the DUT, as well as a choice of DUT
multiplexer inputs that are connected to inputs BNC1 and
BNC2. Short together pins 1 and 2 of JP1 and JP3 to a.c.
couple the input signals. Short pins 5 and 6 of JP1 and
JP3 to d.c. couple the input signal to the DUT. Shorting
together pins 3 and 4 of JP1 or JP3 will ground the
corresponding ADC input.
4. Connect a USB cable between the WaveVision4
Capture Board and a USB port on your computer.
5. Connect a clean power supply to the terminals of
connector P1. Adjust power supply to a voltage of
±5.5V to ±5.7V before connecting it to the board.
Apply power to the WaveVision4 Capture Board.
6. Connect an appropriate test signal source to
connector BNC1 and/or BNC2 of the evaluation
board through (an) appropriate filter(s).
JP2 and JP4 determine which BNC connector is
connected to which ADC input. See Figure 2 for the
device schematic. 5.2.2 Quick Check of Analog Functions
Refer to Figure 1 for locations of major components on
the board. If at any time the expected response is not
obtained, see section 5.2.5 on Troubleshooting.
Caution: Be sure that the input signals to the DUT do
not go more negative than -0.3V or more than 0.3V
above the DUT power supply. 1. Perform steps 1 through 6 of Section 5.2.1.
2. Adjust VR1 for the desired DUT supply voltage at
TP1.
5.0 Installing and Using the ADCxx1S101
Evaluation Board 3. Adjust VR2 for a voltage at TP6 and TP7 that are
1/2 that at TP1.
The evaluation board requires a power supply as
described in Section 4.7. An appropriate signal generator
with 50 Ohm source impedance should be connected to
the Analog Input BNC1 and/or BNC2. A bandpass filter
should be inserted between the generator output and the
4. Apply a signal to BNC1 and scope TP6 to be sure
the input signal is present.
5. Apply a signal to BNC2 and scope TP7 to be sure
the input signal is present.
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This completes the testing of the analog portion of the
evaluation board. cleanly "wrap around" itself, providing coherent sampling. This eliminates the distortion that would otherwise be
present in an FFT and greatly increases its spectral
resolution. This, in turn, allows us to more accurately
evaluate the spectral response of the A/D converter.
5.2.3 Quick Check of Software and Computer
Interface Operation
1. Perform the steps of Paragraph 5.2.2, above. When we do this, however, we must be sure that the
input signal has high spectral purity and stability and that
the sampling clock signal is extremely stable with
minimal jitter.
2. Put a jumper between pins 1 and 2 of JP1 and
between pins 1 and 2 of JP2.
3. Apply a signal to BNC1. Adjust the signal source at
Analog Input BNC1 for a peak-to-peak signal
amplitude at TP6 that is very slightly below the value
of the d.c. voltage at TP1.
Coherent sampling of a periodic waveform occurs when
an integer number of cycles exists in the sample window.
The relationship between the number of cycles sampled
(CY), the number of samples taken (SS), the signal input
frequency (fin) and the sample rate (fs), for coherent
sampling, is
4. Be sure there is an interconnecting cable between
the Capture Board and your computer USB port.
5. Run the WaveVision4 program and click on
Settings, then click on Capture. Under "Board Type"
select "WaveVision 4.0 (USB)". CY
SS
fin
fs
=
6. Under "Communication" press the "Test" button. If
you get a "Communication Failed" message, test all
connections and be sure the power supply to the
boards is turned on. Click on "Accept".
CY, the number of cycles in the data record, must be a
prime integer number and SS, the number of samples in
the record, must be a power of 2 integer.
Further, fin (signal input frequency) and fs(sampling rate)
should be locked to each other. Then, if they come from
the same generator, whatever frequency instability (jitter)
is present in the two signals will cancel each other.
7. Acquire data by pressing the computer F1 key. Data
transfer can take a few seconds.
8. When transfer is complete, the data window should
show many sine waves. The display may show a
nearly solid area of red, which is O.K. Windowing (an FFT Option under WaveVision) should
not be used for coherent sampling.
9. With the mouse, you may click on the magnifying
glass, then and drag (top left to bottom right) to
select a portion of the displayed waveform for better
examination.
5.2.5 Troubleshooting
Nothing happens when F1 is pressed: Select Settings,
then Capture Board Settings and look at the top for
"Board Properties" If you see "No WaveVision hardware
is present", be sure that the WaveVision Capture Board
is connected to an USB port and has power, that the
evaluation board has power and is properly connected to
and seated with the WaveVision4 Capture Board.
10. Click on the FFT tab to compute the FFT and
display a frequency domain plot.
The FFT data will provide a measurement of SINAD,
SNR, THD SFDR and ENOB, simplifying the
performance verification of the DUT. There is no output from the DUT: perform the following:
Note: Be sure to use a band pass filter between the
signal source and this board for accurate dynamic
performance measurement.
•Be sure the appropriate input channel is selected
through the WaveVision4 software.
•Be sure that a shorting jumper is appropriately
placed on JP1 through JP4.
To change the selected input channel, click on the
"Settings" pull-down, then on "Product Board Settings"
and choose the selected channel. Choosing "GND" will
internally ground the ADC input. It is necessary to select
the mainWaveVision4 window before capturing data.
•Be sure that the proper voltage and polarity is
present at Power Connector J6.
•Check to see that the DUT input signal does not go
below ground or above the DUT supply voltage.
5.2.4 Getting Consistent Readings
•Be sure there is a clock signal is present at TP5.
Artifacts can result when we perform an FFT on a
digitized waveform, producing inconsistent results when
testing repeatedly. The presence of these artifacts means
that the ADC under test may perform better than our
measurements would indicate. Windowing is a common
method of improving FFT results of finite data.
The PC displayed waveform appears to be noisy, or the
FFT plot shows nothing but noise with no apparent
signal:
•Be sure the appropriate input channel is selected
through the WaveVision4 software.
We can eliminate the need for windowing and get more
consistent results if we observe the proper ratios between
the input and sampling frequencies, forcing the data to
•Be sure shorting jumpers are appropriately on JP1
through JP4.
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•Check to see that the DUT input signal does not go
below ground or above the DUT analog supply
voltage.
•Be sure that a minimum of +2.7V is at pin 1 of TP1.
•Be sure that only one clock source (oscillator at Y1
or signal at BNC3) is active on the board.
6.0 Evaluation Board Specifications
Board Size: 3.1" x 3.8" (8.0 cm x 9.6 cm)
Power Requirements: + 5.5V to 5.7 @ 15 mA
Clock Frequency Range: 1 MHz to 20 MHz
Analog Input
Nominal Voltage: Supply peak-to-peak Voltage
Impedance: 50 Ohms
7 http://www.national.com

7.0 Hardware Schematic
Figure 2. ADC12xSxx1 / ADC10xSxx1 / ADC08xSxx1 Evaluation Board Schematic
+5p5V
AIN1
JP3
IN2_SEL
1 3 5
2 4 6
+
+ +
+
+ +
R14
5.1K
C1
0.1uF
EEPROM_Power
TP2
ADC_CS#
1
LA1
Logic Analyzer Header
1 2 3 4 5 6 7 8 9 10
D1
1N4001
C16
0.1uF
U2
MSOP10-2
1
2
3
6 5
7
4
8 9
10
CS#
VA
GND
AIN1
AIN2
VD
N/C
DIN
DOUT
SCLK
ADC_DIN
C9 0.1uF
EXT
C5
10uF, 6.3V
U1 LM4041DIZ-1.2
3 2
TPG3
GND
1
TP6
Input_1
1
C14
0.1uF
C8 0.1uF
ADC_DOUT
TP3
ADC_DIN
1
C15
10uF, 6 .3V
P1
POWER_IN
1 2
+5V
EEPROM_SCL
ADC_SCLK
R18
5.1K
VR1 1k
EEPROM_Power
AIN2
C11
0.1uF
R8
not used
JP4
IN2_CH_SEL
1 2 3 4 5 6 7 8
R11
100
ADC_CSb
L1
100 uH Choke
C7 1uF
U4
MSOP10-1
1
23
7 6 5 4
8 9
10
CS#
VAGND
AIN1 AIN2
AIN3
AIN4
DIN
DOUT
SCLK
ADC_DIN
D2
1N4148
R13
100
R12
100
R9
100
ADC_SCLK
AIN4
R4
0
C2
68uF
TP1
+V
1
INPUT_OFFSET
ADC_DOUT
R6 1k
BNC2
INPUT_2
1
2
TPG1
GND
1
Y2
8 MHz OSC (SM T)
42
13
VDDGND
OEOUT
C17
0.1uF
R10
100
TPG2
GND
1
Q2
2N3904
3
1
2
R16
51
BNC3
INPUT_1 1
2
EEPROM_SDA
Y1
8 MHz OSC (THROUGH-HOLE)
147
18
VDDGND
OEOUT
C3 0.1uF
AIN1
ADC_DOUT
SCLK_SEND
AIN2
SCLK_SEND
TP7
Input_2
1
C4 0.1uF
+3P3V
EEPROM_SCL
U5
24C02/SO8
1 2 3
4
5
6 7
8
A0 A1 A2
GND
SDA
SCL
WP
VCC
ADC_CSb
ADC_SCLK
D.C. COUP.
EEPROM_Power
AIN3
JP6
HEADER 3X 1
1 2 3
ADC_SCLK
ADC_SCLK
C19
10uF, 6.3V
JP1
IN1_SEL
1 3 5
2 4 6
+
+ +
+
+ +
JP2
IN2_CH_SEL
1 2 3 4 5 6 7 8
TPG4
GND
1
C12
10uF, 6 .3V
AIN1
R3
51.1
C18
0.1uF
L2
100 uH Choke
ADC_CSb
ADC_DIN
AIN4
A.C. COUP.
TP8
+5.5V_IN
1
INPUT2
ADC_CSb
+5p5V
ADC_DIN
ADC_DOUT
D.C. COUP.
TP4
ADC_DOUT
1
BNC1
INPUT_1
1
2
+5p5V
AIN2
A.C. COUP.
+5V
AIN2
TP5
ADC_SCLK
1
ADC_DIN
JP5
CLK_ENABLE
1 2
INPUT1
AIN1
Q1 2N3904
3
1
2
CLK
R5 1.8k
+1p2V
+5p5V_IN
C13
0.1uF
ADC_DOUT
ADC_SCLK
C10
0.1uF
U3
MSOP8-1
1
23
5 46
7 8
CS#
VAGND
AIN1 AIN2 DIN
DOUT
SCLK
ADC_CSb
J2 FUTUREBUS_96
A1
B1
C1
D1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
A1
B1
C1
D1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
VR2 1k
R2
51.1
C6
10uF, 6.3V
AIN3
R7 1k
INT
R17
5.1K
+V
EEPROM_SDA
R15
5.1K
R19
51
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8.0 ADC12/10/08xSxx1 Evaluation Board Bill of Materials
Item Qty Reference Part Source
1 12 C1, C3, C4, C8, C9, C10, C11, C13, C14, C16,
C17, C18 0.1uF Type 0805
2 1 C2 68uF Type 7343
3 5 C5, C6, C12, C15, C19 10uF, 6.3V Type 3216
4 1 C7 1uF, 6.3V or 10V Type 3216
5 3 BNC1, BNC2, BNC3 BNC Connector DigiKey # ARF1177-ND
6 1 D1 1N4001 - DO-41 Pkg Various
7 1 JP1, JP3 3x2 Pin Post Header DigiKey # 22-28-4065-ND
8 2 JP2, JP4 2x2 Pin Post Header [2 input]
2x4 Pin Post Header [4 input]
DigiKey # 10-89-9047-ND
DigiKey # 22-28-4085-ND
9 0 JP5 not used n/a
10 1 JP6 3-pin Post Header DigiKey # A19351-ND
11 1 J2 FUTUREBUS Connector AMP/Tyco 536501-1
12 1 LA1 2 x 10 pin Post Header DigiKey # 10-89-2101-ND
13 2 L1, L2 100uH Inductor DigiKey # 445-1152-1-ND
14 1 P1 2-Pin Terminal Block DigiKey # ED1609-ND
15 2 Q1, Q2 MMBTN3904 (SOT-23) Various
16 2 R2, R3 51.1, 1%, 1/8 Watt Size 0603
17 1 R4 0 Size 0603
18 1 R5 1.8k, 5%, 1/10 W Size 0603
19 2 R6, R7 1k, 5%, 1/10 W Size 0603
20 2 VR1, VR2 1k DigiKey # 3386F-102-ND
21 0 R8 not used n/a
22 5 R9, R10, R11, R12, R13 100, 5%, 1/10 W Size 0603
23 4 R14, R15, R17, R18 5.11K, 1%, 1/10 W Size 0603
24 2 R16, R19 51, 5%, 1/8 W Size 0603
25 1 TP1, TP2, TP3, TP4, TP5 ,TP6, TP7, TP8,
TPG1, TPG2, TPG3, TPG4 Breakable Header DigiKey # S1012-36-ND
26 1 U1 LM4041DIZ-1.2 National Semiconductor
27 0 U2 not used n/a
28 1 U3 ADCxx2Sxx1 National Semiconductor
29 0 U4 ADCxx4Sxx1 National Semiconductor
30 1 U5 24C02/SO8 Various
31 1 Y1 4 MHz OSC fo 50 ksps
20 MHz OSC for 200 ksps
20 MHz OSC for 1 Msps
DigiKey # CTX107-ND
DigiKey # CTX114-ND
DigiKey # CTX119-ND
32 0 Y2 - optional, not provided not used n/a
33 1 OSC Socket For Y1 DigiKey # A400-ND
34 5 Shorting Jumpers For JP1, JP2, JP3, JP4, JP6 DigiKey #S9601-ND
9 http://www.national.com

APPENDIX
A1 Summary Tables of Test Points and Connectors
P1 Connector - Power Supply Connections
Pin Iput Voltage Function
P1-1 +5.5V to +5.7V Positive Power Supply
P1-2 GND Power Supply Ground
LA1 - Logic Analyzer Header
Pin Function
1 Ground
3 ADC Serial Data Output
5 ADC Chip Select (active low)
7 ADC serial Clock
9 ADC Serial Data Input
2 Ground
4 Ground
6 Ground
8 Ground
10 Ground
JP1 - Input 1 Select
Jumper Function
none Input 1 not connected to DUT
1 - 2 Input 1 a.c. coupled
3 - 4 Input 1 path grounded
5 - 6 Input 1 d.c. coupled
JP2 - Input 1 Channel Select
Jumper Function
none Input 1 NOT connected to DUT
1 - 2 Input 1 connected to IN1
3 - 4 Input 1 connected to IN2
5 - 6 Input 1 connected to IN3 (ADCxx4Sxx1 only)
7 - 8 Input 1 connected to IN4 (ADCxx4Sxx1 only)
JP3 - Input 2 Select
Jumper Function
none Input 2 not connected to DUT
1 - 2 Input 2 a.c. coupled
3 - 4 Input 2 path grounded
5 - 6 Input 2 d.c. coupled
10 http://www.national.com

JP4 - Input 2 Channel Select
Jumper Function
none Input 2 NOT connected to DUT
1 - 2 Input 2 connected to IN1
3 - 4 Input 2 connected to IN2
5 - 6 Input 2 connected to IN3 (ADCxx4Sxx1 only)
7 - 8 Input 2 connected to IN4 (ADCxx4Sxx1 only)
JP5 - Clock Enable
Jumper Function
none Clock at Y1 or Y2 is disabled if oscillator has enable input
1 - 2 Clock at Y1 or Y2 is enabled
Test Points on the Evaluation Board
Test Point Function
TP 1 DUT supply voltage
TP 2 ADC CSb
TP 3 ADC D
IN
TP 4 ADC D
OUT
TP 5 SCLK
TP 6 INPUT1 Signal input to DUT
TP 7 INPUT2 Signal input to DUT
TP 8 Board +5.5V Supply Input voltage
TPG1 thru
TPG4 Ground
J10 - FutureBus Connector
Pin(s) Function
A1, B1, A2, B2 +5V from WaveVision4 Capture Board
D2 ADC Serial Clock
B3 EEPROM SDA (Data)
C3 EEPROM SCL (Clock)
D3 EEPROM Power
A4 ADC Data Output
D17 SCLK SEND
D18 ADC SCLK
D19 ADC CS#
D20 ADC Data Input
A23, B23, A24, B24 +3.3V from WaveVision4 Capture Board
All Others Ground
11 http://www.national.com

These Evaluation Boards are intended for product evaluation purposes only and are not intended for resale to end
consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC.
National does not assume any responsibility for use of any circuitry or software supplied or described. No circuit patent
licenses are implied.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform, when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component in a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor Corporation
Americas
Tel: [phone]
Fax: [phone]
Email: [email protected]
National Semiconductor Europe
Fax: [phone]
Email: [email protected]
Deutsch Tel: [phone]
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Tel: [phone]
Fax: [phone]
Email: [email protected]
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Tel: [phone]
Fax: [phone]
www.national.com
National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right
at any time without notice to change said circuitry and specifications.
12 http://www.national.com

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