NEC UPD98413 User manual

µPD98413
(NEASCOT-P65)
QUAD 622M ATM/POS SONET FRAMER
Preliminary User’s Manual rev0.1
Document No. 2SYSM-FAD-0166
Date Published September 2001 CP (K)
NEC Corporation

PRELIMINARY NEC confidential and Proprietary
2
• The information contained in this document is being issued in advance of the production cycle for
the device. The parameters for the device may change before final production or NEC Corporation, at
its own discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may
appear in this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability
arising from use of such device. No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Corporation or of others.
• Descriptions of circuits, software, and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software, and information in the design of the customer’s equipment shall be done under the
full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by
the customer or third parties arising from the use of these circuits, software, and information.

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SUMMARY OF CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................................................9
CHAPTER 2 PIN FUNCTION.................................................................................................................................................17
CHAPTER 3 FUNCTIONAL OUTLINE ..................................................................................................................................39
CHAPTER 4 INTERFACES .................................................................................................................................................113
CHAPTER 5 REGISTERS....................................................................................................................................................159
CHAPTER 6 JTAG BOUNDARY SCAN.............................................................................................................................305

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CONTENTS
CHAPTER 1 GENERAL 9
1.1 Features 9
1.2 Ordering Information 10
1.3Application 11
1.4 Block Diagram 12
1.5 Pin Configuration 13
1.6Reference 14
CHAPTER 2 PIN FUNCTION 15
2.1 Pin Configuration 15
2.2 Pin Function 17
2.2.1 Line Interface 17
2.2.2 ATM/POS Interface 19
2.2.3 Management Interface 26
2.2.4 Overhead Interface 27
2.2.5 Section and Line DCC Interface 29
2.2.6 Frame Pulse input pins 30
2.2.7 General-Purpose I/O Port 30
2.2.8 Alarm Signal Input / Output 31
2.2.9 JTAG Boundary Scan 32
2.2.10 Reset pin 32
2.2.11 Power and Grounding Pins 32
2.2.12 Others 32
2.2.13 Handling Unused Pins 33
2.2.14 Initial States of Each Pin 34
CHAPTER 3 FUNCTIONAL OUTLINE 37
3.1 SONET Overhead Processing 41
3.1.1 Transmission Function 41
3.1.2 Reception Function 47
3.2 ATM Function 59
3.2.1 Transmit ATM function 60
3.2.2 Receive ATM function 62
3.3 POS FUNCTIONS 66
3.3.1 Transmission POS functions 67
3.3.2 Reception POS functions 72
3.4 OAM Function 77
3.4.1 Transmitting Alarm 77
3.4.2 Detection of Alarm and Failure 81
3.4.3 Alarm management 85
3.4.4 APS (Automatic Protection Switching) 87
3.4.5 Monitoring Signal Label Byte 90
3.4.6 Monitoring Line Quality (Performance Monitoring) 92
3.5 Overhead Insert/Drop Function 99
3.5.1 Insert Register 100

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3.5.2 Drop Register 100
3.6 Transmission/Reception of J0/J1 Trace Message 101
3.6.1 Transmitting Trace Message 101
3.6.2 Receiving Trace Message 104
3.7 Transmitting Pseudo Frame for Testing 110
3.8 Loopback Function 111
CHAPTER 4 INTERFACES 111
4.1LineInterface 111
4.2ATMInterface 116
4.2.1 Signals 116
4.2.2 Cell Formats 119
4.2.3 Transmit operation 120
4.2.4 Receive operation 123
4.2.5Parity 127
4.2.6 ATM Interface Error Detection 127
4.3POSInterface 129
4.3.1 Signals 129
4.3.2 Packet Formats 133
4.3.3 Transmit operation 134
4.3.4 Receive operation 135
4.3.5Parity 138
4.3.6 POS Interface Error Detection 138
4.4 Overhead Insert/Extract Interfaces and Section/Line DCC Insert/Extract Interface 140
4.4.1 OH Insert Interface 141
4.4.2 OH Extract Interfaces 144
4.4.3 Transmit Section and Line DCC Insert Interface 145
4.4.4 Receive Section and Line DCC Extract Interface 145
4.5 Frame Pulse input pins 146
4.6 General-Purpose Input and Output Ports 147
4.7 Alarm Insertion / Detection Pins 148
4.7.1 Alarm Insertion Pins 148
4.7.2 Alarm Detection Pins 148
4.8 Management Interface 149
4.8.1 Endian 149
4.8.2 Access timing 150
4.8.3 Interrupt 152
CHAPTER 5 REGISTERS 159
5.1 Register Map 160
5.2 Register summary 166
5.3 Function of Registers 169
CHAPTER 6 JTAG BOUNDARY SCAN 305
6.1 Features 305
6.2 Internal Configuration of Boundary Scan Circuit 307
6.2.1 Instruction Register 307

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6.2.2 TAP (Test Access Port) Controller 307
6.2.3 Bypass Register 307
6.2.4 Boundary Scan Register 307
6.3 Pin Function 308
6.3.1 JCK (JTAG Clock) Pin 308
6.3.2 JMS (JTAG Mode Select) Pin 308
6.3.3 JDI (JTAG Data Input) Pin 308
6.3.4 JDO (JTAG Data Output) Pin 308
6.3.5 JRST_B (JTAG Reset) Pin 308
6.4 Operation Description 309
6.4.1 TAP Controller 309
6.4.2 TAP Controller State 309
6.5 TAP Controller Operation 314
6.6 Initializing TAP Controller 317
6.7 Instruction Register 317
6.7.1 BYPASS Instruction 318
6.7.2 EXTEST Instruction 318
6.7.3 SAMPLE/PRELOAD Instruction 318
6.7.4 Boundary Scan Data Bit Definition 318

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CHAPTER 1 GENERAL
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CHAPTER 1 GENERAL
The µPD98413 is a quad 622Mbits/s SONET STS-12c / SDH STM-4c framer. The µPD98413 performs all functions
necessary to insert and extract ATM cells or POS (PPP over SONET) packets into and from SONET/SDH payload.
Applications include ATM/IP switches, Routers, and Access concentrators.
1.1 Features
General
• Quad SONET STS-12c / SDH STM-4 (622Mbps) framing function in compliance with ITU-T G.707, ANSI
T1.105 and Bellcore GR-253-CORE
• Mapping ATM cell or Packet into SONET/SDH payload
• Generic 32-bit microprocessor interface for device control and status monitoring
• 32-bit 104MHzLVTTL interface to be connected with ATM device (UTOPIA level3) or POS device (POS-PHY
level3)
• Four serial 622MHz PECL line interface
• Integrated SERDES, Clock data recovery and Clock synthesis
• Provides loopback functions (line and equipment loopback)
• 1024-byte FIFO for each transmit and receive FIFO
• Provides IEEE 1149.1 JTAG testing
• Industrial temperature range (-40 to 85)
• 576 BGA package and 2.5V power supply
SONET
• Detects LOS, OOF, LOF, Line AIS, Line RDI, LOP, Path AIS, Path RDI (Enhanced and One-bit), Path PLM
and Path UNEQ
• Inserts, detects and counts B1, B2, B3, Line REI and Path REI
• Detects signal fail (SF) and signal degrade (SD) conditions
• Provides buffers to transmit and receive the 16 or 64 bytes section trace (J0) and path trace (J1) message,
also detects Section TIM and Path TIM
• Provides insertion and extraction registers for APS (K1, K2) byte, also detects PSBF
• Generates and interprets payload pointer
• Inserts and extracts registers of overhead bytes, ex. C2 byte
• Inserts and extracts Section and Line DCCs by serial interface
• Inserts and extracts whole overhead bytes by dedicated interface

CHAPTER 1 GENERAL
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ATM • Detects OCD and LCD
• Provides idle/unassigned cell insertion
• Provides cell delineation from SONET/SDH payload and idle/unassigned cell filtering
• Cell scrambling and descrambling
• HEC generation, detection and correction
• Provides performance counters
Transmit valid cell, Receive valid cell, Receive idle cell, HEC error correct cell, HEC error drop cell, Receive
FIFO overflow drop cell
POS • PPP/HDLC processing compliant with RFC 2615(1619) and 1662
• Inserts flag sequence between each POS packet
• Provides packet delineation from SONET/SDH payload by detection flag sequence
• Byte stuffing and destuffing
• Generates and checks 32/16-bit FCS
• Data scrambling and descrambling
• Inserts address and control fields and detects address and control error
• Detects minimum and maximum size packet errors
• Provides performance counters
Transmit valid packet and byte, Transmit abort packet, Transmit FIFO underflow packet, Receive valid
packet and byte, Receive abort packet, Receive address error packet, Receive FCS error packet, Receive
short packet, Receive long packet, Receive FIFO overflow drop packet
1.2 Ordering Information
TBD

CHAPTER 1 GENERAL
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1.3 Application
• Routers
• ATM switches
• Access concentrators
• Add/drop multiplexers and Digital cross connects
Typical Application
P65
Optical
Transceiver
Serial 622MHz
PECL
ATM/POS
Device
UTOPIA L3/
POS-PHY L3
MPU
Control
32-bit LVTTL
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
32-bit 104MHz
LVTTL

CHAPTER 1 GENERAL
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1.4 Block Diagram
Management Interface
Serial
→Parallel
Rx FIFO
Rx FIFO Control
Tx OAM
Processor Block
Line Interface
Registers
Parallel
→Serial
General I/O
32
32
MCLK
AD[32]
CS_B
UWE_B
R/W_B
RDY_B
INT_B
Connect to peripheral devices
Overhead Insert
Interface
ATM/POS Device
Port0
Processor
Alarm Instruction
JTAG
JCK
JDI
JMS
JRST_B
JDO
TFPI
TOHCK (19.44M)
TTOHFP
TPOHFP
TOHD[2]
TOHAV
Rx OAM
Processor Block
RALMA
RALMB
RALMC
ROHCK (19.44M)
RTOHFP
RPOHFP
ROHD[2]
ROHAV
PIO[8]
Alarm Detection
RCS
(
19M
)
TCS
(
19M
)
Rx ATM
Processor
Rx POS
Processor
Payload Type Selector
Clock
Recovery
Tx FIFO Control
Tx FIFO
Tx POS
Processor
Tx ATM
Processor
Tx POH Processor
Frame Gen. BIP
Tx SOH Processor BIP
Clock
Synthesizer
ATM/POS Interface
Rx SOH Processor Rx POH Processor
Frame Sync.
BIP, OAM Pointer Control
BIP
Overhead
Insertion Block
REFCLK
Tranceiver
REFCLK
_
P/N
Registers
Section / Line DCC
Extraction Block Overhead
Extraction Block
Section / Line DCC
Insertion Block
TSDCLK(192k)
TSD
TLDCLK(576k)
TLD
RSDCLK(192k)
RSD
RLDCLK(576k)
RLD
Overhead Extract
Interface
Section / Line DCC
Extract Interface
Section / Line DCC
Insert Interface
TALMA
TALMB
TALMC

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1.5 Pin Configuration
ATM/POS Interface
Management
Interface
Line Interface
JTAG Interface
General I/O Ports
µ
µµ
µ PD98413
NEASCOT-P65
R
X
CLK/RFCLK
R
X
CLAV0/RMOD0
R
X
SOC/RSOP
RXPRTY
/
RPRTY
R
X
DATA
[
31:0
]
/RDAT
[
31:0
]
R
X
ENB
_
B/RENB
_
B
T
X
CLAV0/DTPA0
(
PTPA
)
TXDATA
[
31:0
]
/TDAT
[
31:0
]
TXENB_B/TENB_B
T
X
SOC/TSOP
T
X
PRTY/TPRTY
T
X
CLK/TFCLK
MCLK
A
D
[
32:0
]
CS
_
B
UWE
_
B
R/W
_
B
RDY
_
B
32
32
32
TOHCK0-3
TSDCLK0-3 / TTOHFP0-3
TLD0-3 / TOHD
[
1
]
0-3
TOHAV0-3
TLDCLK0-3 / TPOHFP0-3
PIO[7:0]
JCK
JMS
JDI
JRST_B
JDO
Receive Alarm Pins RALMA0-3
RALMC0-3
RALMB0-3
Overhead Insert/
Extract Interface
Power and Ground
VDD
GND
INT
_
B
Transmit Alarm Pins
IC
Others
RVAL
RS
X
TEOP
TMOD
[
1:0
]
TERR
TS
X
STPA
TXADDR
[
1:0
]
/TADR
[
1:0
]
RXADDR
[
1:0
]
TDOT0-3
TDOC0-3
R
X
CLAV1/RMOD1
RXCLAV2/REOP
R
X
CLAV3/RERR
T
X
CLAV1/DTPA1
T
X
CLAV2/DTPA2
T
X
CLAV3/DTPA3
TALMA0-3
TALMC0-3
TALMB0-3
8
Section / line DCC
Interface
TFPI
ROHCK0-3
RSDCLK0-3 / RTOHFP0-3
RLD0-3 / ROHD
[
1
]
0-3
ROHAV0-3
RLDCLK0-3 / RPOHFP0-3
RFCKPLT
RFCKPLC
RFCKSEL
LPFP
LPFC0-3
BIASP
BIASC0-3
RESET_B
RSD0-3 / ROHD
[
0
]
0-3
TSD0-3 / TOHD
[
0
]
0-3
or
RFCKTTL
RDIT0-3
RDIC0-3
LPFPGND
LPFCGND0-3
CD0-3
CDVREF
Frame Pluse
input pin
Reset pin

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1.6 Reference
• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
• ATM Forum - UTOPIA 3 Physical Layer Interface, af-phy-0136.000, November, 1999
• Bell Communications Research - GR-253-CORE “SONET Transport Systems: Common Generic Criteria”,
Issue 2, revision 2 1999.
• IETF Network Working Group - RFC-2615 “Point to Point Protocol (PPP) over SONET/SDH Specification”,
June 1999.
• IETF Network Working Group - RFC-1662 “PPP in HDLC like framing”, July 1994.
• ITU, Recommendation G.707 - "Network Node Interface For The Synchronous Digital Hierarchy", 1996.
• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment
Functional Blocks", 1996.
• ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.
• ANSI - T1.105 “Synchronous Optical Network (SONET)-Basic Description including Multiplex Structure,
Rate, and Format ”, 1995
• ANSI - T1.231 “Digital Hierarchy –Layer 1 In-Service Digital Transmission Performance Monitoring ”,
October 20,1997
• PMC-1980495 “Saturn Compatible Packet over SONET Interface Specification for Physical and Link Layer
Devices”, June 2000

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CHAPTER 2 PIN FUNCTION
2.1 Pin Configuration
TBD

CHAPTER 2 PIN FUNCTION
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Pin Arrangement Table
TBD

CHAPTER 2 PIN FUNCTION
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2.2 Pin Function
2.2.1 Line Interface
The line interface connects with an optical transceiver. (1/2)
Pin Name Serial No. Address No. I/O Level Function
TDOT0-3
TDOC0-3
O
2.5V
Differential
PECL
Transmit serial data output pins.
Transmit data is output from these pins.
RFCKPLT
RFCKPLC
I
2.5V
Differential
PECL
The differential reference clock inputs.
Inputs the reference clock for both the CDR and the
synthesizer PLL circuits. RFCKPLT must be connected to
a logic one and RFCKPLC to a logic zero state when
RFCKTTL is used.
RFCKTTL I
LVTTL
TTL reference clock input.
TTL reference clock inputs for both the CDR and the
TxPLL circuits. RFCKTTL must be tied high if RFCKPLT/
RFCKLC is used.
LPFP Analog Loop Filter Capacitor for synthesizer PLL.
The TxPLL loop filter capacitor is connected to this pin.
LPFPGND Analog Loop Filter Capacitor for synthesizer PLL. (GND)
The TxPLL loop filter capacitor is connected to this pin.
BIASP Analog Bias pin for TxPLL
Connects to analog VDD via 1.1KΩregister

CHAPTER 2 PIN FUNCTION
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(2/2)
Pin Name Serial No. Address No. I/O Level Function
RDIT0-3
RDIC0-3
I
2.5V
Differential
PECL
Receive serial data input.
The input data is sampled with the recovered clock from
the internal CDR when the internal CDR mode.
CD0-3 I
3.3V
Single-ended
PECL
Carrier Detect.
The receive signal detect PECL input indicates the loss
of receive signal power from the Optical module and it is
active high.
Each port has one pin. CD0 corresponds to PORT0,
while CD3 corresponds to PORT3.
CDVREF I
3.3V
PECL
This pin input reference potentials (intermediate
potentials) for single-ended PECL input signals (CD0-3).
LPFC0-
LPFC3 Analog Loop Filter Capacitor the CDR.
The CDR loop filter capacitor is connected to this pin.
Each port has one pin.
LPFCGND0-
LPFCGND3
Analog Loop Filter Capacitor the CDR.(GND)
The CDR loop filter capacitor is connected to this pin.
Each port has one pin.
BIASC0-3 Analog Bias pin for CDR
Connects to analog VDD via 1.1KΩregister

CHAPTER 2 PIN FUNCTION
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2.2.2 ATM/POS Interface
The ATM/POS interface transfers ATM cells or POS packets to and from an ATM/POS device.
ATM Interface (1/2)
Pin Name Serial No. Address No. I/O Level Function
RXCLK I
LVTTL Receive clock input.
This pin inputs the clock, up to 104 MHz, used to transfer
receive data.
RXDATA[31:0] O
LVTTL Receive data output.
These pins form a 32-bit data bus through which receives
cell data is output to the ATM device. The data on this bus
is updated at the rising edge of RXCLK. RXDATA31 is the
MSB. RXDATA0 is the LSB.
RXSOC O
LVTTL Receive cell start position signal output.
This pin goes high during the clock cycle in which the first
byte of the receive cell is output to RXDATA, to post
notification to the ATM device.
RXENB_B I
LVTTL Receive enable signal input.
The ATM device enables or disables the receive cell data
output by the µPD98413. The µPD98413 samples
RXENB_B at the rising edge of RXCLK. When it detects
the low level of RXENB_B, it updates the output of RSOC
and RXDATA starting from the next clock cycle, and then
transfers the receive cell data. If RXENB_B is high, the
µPD98413 stops the output of RSOC and RXDATA,
starting from the next clock cycle.
RXPRTY O
LVTTL Receive data path parity.
This pin generates an odd parity bit for the output data on
RXDATA and outputs it from RXPRTY. The parity bit is
always output.
The parity bit to be generated can be changed to even parity
depending on the setting of the PARM bit of MDAPIR
register.
RXCLAV0-3 O
LVTTL Receive cell available.
The
µ PD98413 drives RXCLAV high if one or more cells of
receive data to be transferred exists in the receive FIFO, to
post notification to the ATM device. RXCLAV is held high if
one or more cells of valid data exists in the receive FIFO at
the 2 clock cycle or later after the start of output of the cell;
otherwise, RXCLAV goes low. RXCLAV0 corresponds to
PORT0, while RXCLAV3 corresponds to PORT3.
RXADDR[1:0] I
LVTTL Receive PHY address input.
These pins are used to input a port address for requesting
data output.

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(2/2)
Pin Name Serial No. Address No. I/O Level Function
TXCLK I
LVTTL Transmit clock input.
This pin inputs the clock, up to 104 MHz, used to transfer
transmit data.
TXDATA[31:0] I
LVTTL Transmit data input bus.
These pins form a 32-bit data bus through which transmits
cell data is input. The µPD98413 samples the data on this
bus at the rising edge of TXCLK.
TXSOC I
LVTTL Transmit start of cell input.
This pin is inputted a signal that indicates the start position
of a transmit cell. The
µ PD98413 recognizes the clock cycle
in which TXSOC is high as the first word of a cell.
TXENB_B I
LVTTL Transmit enable signal input.
This signal indicates that the ATM device has output valid
transmit cell data to TXDATA. The
µ PD98413 samples
TXENB_B at the rising edge of TXCLK. If TXENB_B is low,
it loads the data on TXSOC and TXDATA to the transmit
FIFO at the edge of TXCLK. If TXENB_B is high, the data
on TXSOC and TXDATA is not loaded to the transmit FIFO.
TXCLAV0-3 O
LVTTL Transmit cell buffer available.
This signal posts notification of the vacancy of the transmit
FIFO to the ATM device. If the number of cells stored in the
transmit FIFO has reached the threshold value set by the
APHIGH[7:0] bits of the FTHT1 register, the
µ PD98413
drives TXCLAV low. The subsequent cells are dropped and
the µPD98413 reports an overflow of the transmit FIFO.
TXCLAV0 corresponds to PORT0, while TXCLAV3
corresponds to PORT3.
TXPRTY I
LVTTL
(Internal
pull-up)
Transmit data path parity.
This pin inputs the odd parity bit of the data input to
TXDATA. The
µ PD98413 calculates parity based on the
input data and parity bit. If it detects an error, it sets the
PARE bit of the APIET register to report the error. An even
parity can be also used depending on the setting of the
MDAPIT register.
TXADDR[1:0] I
LVTTL Transmit address input.
These pins are used to input a port address for data
transmission.