NEC UPD98413 User manual

µPD98413
(NEASCOT-P65)
QUAD 622M ATM/POS SONET FRAMER
Preliminary User’s Manual rev0.1
Document No. 2SYSM-FAD-0166
Date Published September 2001 CP (K)
NEC Corporation

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• The information contained in this document is being issued in advance of the production cycle for
the device. The parameters for the device may change before final production or NEC Corporation, at
its own discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may
appear in this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability
arising from use of such device. No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Corporation or of others.
• Descriptions of circuits, software, and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software, and information in the design of the customer’s equipment shall be done under the
full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by
the customer or third parties arising from the use of these circuits, software, and information.

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SUMMARY OF CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................................................9
CHAPTER 2 PIN FUNCTION.................................................................................................................................................17
CHAPTER 3 FUNCTIONAL OUTLINE ..................................................................................................................................39
CHAPTER 4 INTERFACES .................................................................................................................................................113
CHAPTER 5 REGISTERS....................................................................................................................................................159
CHAPTER 6 JTAG BOUNDARY SCAN.............................................................................................................................305

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CONTENTS
CHAPTER 1 GENERAL 9
1.1 Features 9
1.2 Ordering Information 10
1.3Application 11
1.4 Block Diagram 12
1.5 Pin Configuration 13
1.6Reference 14
CHAPTER 2 PIN FUNCTION 15
2.1 Pin Configuration 15
2.2 Pin Function 17
2.2.1 Line Interface 17
2.2.2 ATM/POS Interface 19
2.2.3 Management Interface 26
2.2.4 Overhead Interface 27
2.2.5 Section and Line DCC Interface 29
2.2.6 Frame Pulse input pins 30
2.2.7 General-Purpose I/O Port 30
2.2.8 Alarm Signal Input / Output 31
2.2.9 JTAG Boundary Scan 32
2.2.10 Reset pin 32
2.2.11 Power and Grounding Pins 32
2.2.12 Others 32
2.2.13 Handling Unused Pins 33
2.2.14 Initial States of Each Pin 34
CHAPTER 3 FUNCTIONAL OUTLINE 37
3.1 SONET Overhead Processing 41
3.1.1 Transmission Function 41
3.1.2 Reception Function 47
3.2 ATM Function 59
3.2.1 Transmit ATM function 60
3.2.2 Receive ATM function 62
3.3 POS FUNCTIONS 66
3.3.1 Transmission POS functions 67
3.3.2 Reception POS functions 72
3.4 OAM Function 77
3.4.1 Transmitting Alarm 77
3.4.2 Detection of Alarm and Failure 81
3.4.3 Alarm management 85
3.4.4 APS (Automatic Protection Switching) 87
3.4.5 Monitoring Signal Label Byte 90
3.4.6 Monitoring Line Quality (Performance Monitoring) 92
3.5 Overhead Insert/Drop Function 99
3.5.1 Insert Register 100

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3.5.2 Drop Register 100
3.6 Transmission/Reception of J0/J1 Trace Message 101
3.6.1 Transmitting Trace Message 101
3.6.2 Receiving Trace Message 104
3.7 Transmitting Pseudo Frame for Testing 110
3.8 Loopback Function 111
CHAPTER 4 INTERFACES 111
4.1LineInterface 111
4.2ATMInterface 116
4.2.1 Signals 116
4.2.2 Cell Formats 119
4.2.3 Transmit operation 120
4.2.4 Receive operation 123
4.2.5Parity 127
4.2.6 ATM Interface Error Detection 127
4.3POSInterface 129
4.3.1 Signals 129
4.3.2 Packet Formats 133
4.3.3 Transmit operation 134
4.3.4 Receive operation 135
4.3.5Parity 138
4.3.6 POS Interface Error Detection 138
4.4 Overhead Insert/Extract Interfaces and Section/Line DCC Insert/Extract Interface 140
4.4.1 OH Insert Interface 141
4.4.2 OH Extract Interfaces 144
4.4.3 Transmit Section and Line DCC Insert Interface 145
4.4.4 Receive Section and Line DCC Extract Interface 145
4.5 Frame Pulse input pins 146
4.6 General-Purpose Input and Output Ports 147
4.7 Alarm Insertion / Detection Pins 148
4.7.1 Alarm Insertion Pins 148
4.7.2 Alarm Detection Pins 148
4.8 Management Interface 149
4.8.1 Endian 149
4.8.2 Access timing 150
4.8.3 Interrupt 152
CHAPTER 5 REGISTERS 159
5.1 Register Map 160
5.2 Register summary 166
5.3 Function of Registers 169
CHAPTER 6 JTAG BOUNDARY SCAN 305
6.1 Features 305
6.2 Internal Configuration of Boundary Scan Circuit 307
6.2.1 Instruction Register 307

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6.2.2 TAP (Test Access Port) Controller 307
6.2.3 Bypass Register 307
6.2.4 Boundary Scan Register 307
6.3 Pin Function 308
6.3.1 JCK (JTAG Clock) Pin 308
6.3.2 JMS (JTAG Mode Select) Pin 308
6.3.3 JDI (JTAG Data Input) Pin 308
6.3.4 JDO (JTAG Data Output) Pin 308
6.3.5 JRST_B (JTAG Reset) Pin 308
6.4 Operation Description 309
6.4.1 TAP Controller 309
6.4.2 TAP Controller State 309
6.5 TAP Controller Operation 314
6.6 Initializing TAP Controller 317
6.7 Instruction Register 317
6.7.1 BYPASS Instruction 318
6.7.2 EXTEST Instruction 318
6.7.3 SAMPLE/PRELOAD Instruction 318
6.7.4 Boundary Scan Data Bit Definition 318

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CHAPTER 1 GENERAL
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CHAPTER 1 GENERAL
The µPD98413 is a quad 622Mbits/s SONET STS-12c / SDH STM-4c framer. The µPD98413 performs all functions
necessary to insert and extract ATM cells or POS (PPP over SONET) packets into and from SONET/SDH payload.
Applications include ATM/IP switches, Routers, and Access concentrators.
1.1 Features
General
• Quad SONET STS-12c / SDH STM-4 (622Mbps) framing function in compliance with ITU-T G.707, ANSI
T1.105 and Bellcore GR-253-CORE
• Mapping ATM cell or Packet into SONET/SDH payload
• Generic 32-bit microprocessor interface for device control and status monitoring
• 32-bit 104MHzLVTTL interface to be connected with ATM device (UTOPIA level3) or POS device (POS-PHY
level3)
• Four serial 622MHz PECL line interface
• Integrated SERDES, Clock data recovery and Clock synthesis
• Provides loopback functions (line and equipment loopback)
• 1024-byte FIFO for each transmit and receive FIFO
• Provides IEEE 1149.1 JTAG testing
• Industrial temperature range (-40 to 85)
• 576 BGA package and 2.5V power supply
SONET
• Detects LOS, OOF, LOF, Line AIS, Line RDI, LOP, Path AIS, Path RDI (Enhanced and One-bit), Path PLM
and Path UNEQ
• Inserts, detects and counts B1, B2, B3, Line REI and Path REI
• Detects signal fail (SF) and signal degrade (SD) conditions
• Provides buffers to transmit and receive the 16 or 64 bytes section trace (J0) and path trace (J1) message,
also detects Section TIM and Path TIM
• Provides insertion and extraction registers for APS (K1, K2) byte, also detects PSBF
• Generates and interprets payload pointer
• Inserts and extracts registers of overhead bytes, ex. C2 byte
• Inserts and extracts Section and Line DCCs by serial interface
• Inserts and extracts whole overhead bytes by dedicated interface

CHAPTER 1 GENERAL
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ATM • Detects OCD and LCD
• Provides idle/unassigned cell insertion
• Provides cell delineation from SONET/SDH payload and idle/unassigned cell filtering
• Cell scrambling and descrambling
• HEC generation, detection and correction
• Provides performance counters
Transmit valid cell, Receive valid cell, Receive idle cell, HEC error correct cell, HEC error drop cell, Receive
FIFO overflow drop cell
POS • PPP/HDLC processing compliant with RFC 2615(1619) and 1662
• Inserts flag sequence between each POS packet
• Provides packet delineation from SONET/SDH payload by detection flag sequence
• Byte stuffing and destuffing
• Generates and checks 32/16-bit FCS
• Data scrambling and descrambling
• Inserts address and control fields and detects address and control error
• Detects minimum and maximum size packet errors
• Provides performance counters
Transmit valid packet and byte, Transmit abort packet, Transmit FIFO underflow packet, Receive valid
packet and byte, Receive abort packet, Receive address error packet, Receive FCS error packet, Receive
short packet, Receive long packet, Receive FIFO overflow drop packet
1.2 Ordering Information
TBD